1/* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */ 2/* 3 * Copyright (C) 2020-2024 STMicroelectronics - All Rights Reserved 4 * Copyright (C) 2020 Ahmad Fatoum, Pengutronix 5 */ 6 7#include "stm32mp15-pinctrl.dtsi" 8 9&i2c4 { 10 pinctrl-names = "default"; 11 pinctrl-0 = <&i2c4_pins_a>; 12 clock-frequency = <400000>; 13 i2c-scl-rising-time-ns = <185>; 14 i2c-scl-falling-time-ns = <20>; 15 status = "okay"; 16 17 pmic: stpmic@33 { 18 compatible = "st,stpmic1"; 19 reg = <0x33>; 20 interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; 21 interrupt-controller; 22 #interrupt-cells = <2>; 23 24 regulators { 25 compatible = "st,stpmic1-regulators"; 26 27 ldo1-supply = <&v3v3>; 28 ldo6-supply = <&v3v3>; 29 pwr_sw1-supply = <&bst_out>; 30 31 vddcore: buck1 { 32 regulator-name = "vddcore"; 33 regulator-min-microvolt = <1200000>; 34 regulator-max-microvolt = <1350000>; 35 regulator-always-on; 36 regulator-initial-mode = <0>; 37 regulator-over-current-protection; 38 }; 39 40 vdd_ddr: buck2 { 41 regulator-name = "vdd_ddr"; 42 regulator-min-microvolt = <1350000>; 43 regulator-max-microvolt = <1350000>; 44 regulator-always-on; 45 regulator-initial-mode = <0>; 46 regulator-over-current-protection; 47 }; 48 49 vdd: buck3 { 50 regulator-name = "vdd"; 51 regulator-min-microvolt = <3300000>; 52 regulator-max-microvolt = <3300000>; 53 regulator-always-on; 54 st,mask-reset; 55 regulator-initial-mode = <0>; 56 regulator-over-current-protection; 57 }; 58 59 v3v3: buck4 { 60 regulator-name = "v3v3"; 61 regulator-min-microvolt = <3300000>; 62 regulator-max-microvolt = <3300000>; 63 regulator-always-on; 64 regulator-over-current-protection; 65 regulator-initial-mode = <0>; 66 }; 67 68 v1v8_audio: ldo1 { 69 regulator-name = "v1v8_audio"; 70 regulator-min-microvolt = <1800000>; 71 regulator-max-microvolt = <1800000>; 72 regulator-always-on; 73 }; 74 75 v3v3_hdmi: ldo2 { 76 regulator-name = "v3v3_hdmi"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 regulator-always-on; 80 }; 81 82 vtt_ddr: ldo3 { 83 regulator-name = "vtt_ddr"; 84 regulator-always-on; 85 regulator-over-current-protection; 86 st,regulator-sink-source; 87 }; 88 89 vdd_usb: ldo4 { 90 regulator-name = "vdd_usb"; 91 regulator-min-microvolt = <3300000>; 92 regulator-max-microvolt = <3300000>; 93 }; 94 95 vdda: ldo5 { 96 regulator-name = "vdda"; 97 regulator-min-microvolt = <2900000>; 98 regulator-max-microvolt = <2900000>; 99 regulator-boot-on; 100 }; 101 102 v1v2_hdmi: ldo6 { 103 regulator-name = "v1v2_hdmi"; 104 regulator-min-microvolt = <1200000>; 105 regulator-max-microvolt = <1200000>; 106 regulator-always-on; 107 }; 108 109 vref_ddr: vref_ddr { 110 regulator-name = "vref_ddr"; 111 regulator-always-on; 112 }; 113 114 bst_out: boost { 115 regulator-name = "bst_out"; 116 }; 117 118 vbus_otg: pwr_sw1 { 119 regulator-name = "vbus_otg"; 120 regulator-active-discharge; 121 }; 122 123 vbus_sw: pwr_sw2 { 124 regulator-name = "vbus_sw"; 125 regulator-active-discharge; 126 }; 127 }; 128 129 pmic_watchdog: watchdog { 130 compatible = "st,stpmic1-wdt"; 131 status = "disabled"; 132 }; 133 }; 134}; 135 136&rng1 { 137 status = "okay"; 138}; 139 140/* ATF Specific */ 141#include <dt-bindings/clock/stm32mp1-clksrc.h> 142 143/ { 144 aliases { 145 gpio0 = &gpioa; 146 gpio1 = &gpiob; 147 gpio2 = &gpioc; 148 gpio3 = &gpiod; 149 gpio4 = &gpioe; 150 gpio5 = &gpiof; 151 gpio6 = &gpiog; 152 gpio7 = &gpioh; 153 gpio8 = &gpioi; 154 gpio25 = &gpioz; 155 i2c3 = &i2c4; 156 }; 157}; 158 159&bsec { 160 board_id: board-id@ec { 161 reg = <0xec 0x4>; 162 st,non-secure-otp; 163 }; 164}; 165 166&clk_hse { 167 st,digbypass; 168}; 169 170&cpu0 { 171 cpu-supply = <&vddcore>; 172}; 173 174&cpu1 { 175 cpu-supply = <&vddcore>; 176}; 177 178&hash1 { 179 status = "okay"; 180}; 181 182/* CLOCK init */ 183&rcc { 184 st,clksrc = < 185 CLK_MPU_PLL1P 186 CLK_AXI_PLL2P 187 CLK_MCU_PLL3P 188 CLK_RTC_LSE 189 CLK_MCO1_DISABLED 190 CLK_MCO2_DISABLED 191 CLK_CKPER_HSE 192 CLK_FMC_ACLK 193 CLK_QSPI_ACLK 194 CLK_ETH_PLL4P 195 CLK_SDMMC12_PLL4P 196 CLK_DSI_DSIPLL 197 CLK_STGEN_HSE 198 CLK_USBPHY_HSE 199 CLK_SPI2S1_PLL3Q 200 CLK_SPI2S23_PLL3Q 201 CLK_SPI45_HSI 202 CLK_SPI6_HSI 203 CLK_I2C46_HSI 204 CLK_SDMMC3_PLL4P 205 CLK_USBO_USBPHY 206 CLK_ADC_CKPER 207 CLK_CEC_LSE 208 CLK_I2C12_HSI 209 CLK_I2C35_HSI 210 CLK_UART1_HSI 211 CLK_UART24_HSI 212 CLK_UART35_HSI 213 CLK_UART6_HSI 214 CLK_UART78_HSI 215 CLK_SPDIF_PLL4P 216 CLK_FDCAN_PLL4R 217 CLK_SAI1_PLL3Q 218 CLK_SAI2_PLL3Q 219 CLK_SAI3_PLL3Q 220 CLK_SAI4_PLL3Q 221 CLK_RNG1_CSI 222 CLK_RNG2_LSI 223 CLK_LPTIM1_PCLK1 224 CLK_LPTIM23_PCLK3 225 CLK_LPTIM45_LSE 226 >; 227 228 st,clkdiv = < 229 DIV(DIV_MPU, 1) 230 DIV(DIV_AXI, 0) 231 DIV(DIV_MCU, 0) 232 DIV(DIV_APB1, 1) 233 DIV(DIV_APB2, 1) 234 DIV(DIV_APB3, 1) 235 DIV(DIV_APB4, 1) 236 DIV(DIV_APB5, 2) 237 DIV(DIV_RTC, 23) 238 DIV(DIV_MCO1, 0) 239 DIV(DIV_MCO2, 0) 240 >; 241 242 st,pll_vco { 243 pll1_vco_1300Mhz: pll1-vco-1300Mhz { 244 src = < CLK_PLL12_HSE >; 245 divmn = < 2 80 >; 246 frac = < 0x800 >; 247 }; 248 249 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 250 src = <CLK_PLL12_HSE>; 251 divmn = <2 65>; 252 frac = <0x1400>; 253 }; 254 255 pll3_vco_417Mhz: pll3-vco-417Mhz { 256 src = <CLK_PLL3_HSE>; 257 divmn = <1 33>; 258 frac = <0x1a04>; 259 }; 260 261 pll4_vco_594Mhz: pll4-vco-594Mhz { 262 src = <CLK_PLL4_HSE>; 263 divmn = <3 98>; 264 }; 265 }; 266 267 /* VCO = 1300.0 MHz => P = 650 (CPU) */ 268 pll1: st,pll@0 { 269 compatible = "st,stm32mp1-pll"; 270 reg = <0>; 271 272 st,pll = < &pll1_cfg1 >; 273 274 pll1_cfg1: pll1_cfg1 { 275 st,pll_vco = < &pll1_vco_1300Mhz >; 276 st,pll_div_pqr = < 0 0 0 >; 277 }; 278 }; 279 280 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 281 pll2: st,pll@1 { 282 compatible = "st,stm32mp1-pll"; 283 reg = <1>; 284 285 st,pll = <&pll2_cfg1>; 286 287 pll2_cfg1: pll2_cfg1 { 288 st,pll_vco = <&pll2_vco_1066Mhz>; 289 st,pll_div_pqr = <1 0 0>; 290 }; 291 }; 292 293 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 294 pll3: st,pll@2 { 295 compatible = "st,stm32mp1-pll"; 296 reg = <2>; 297 298 st,pll = <&pll3_cfg1>; 299 300 pll3_cfg1: pll3_cfg1 { 301 st,pll_vco = <&pll3_vco_417Mhz>; 302 st,pll_div_pqr = <1 16 36>; 303 }; 304 }; 305 306 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 307 pll4: st,pll@3 { 308 compatible = "st,stm32mp1-pll"; 309 reg = <3>; 310 311 st,pll = <&pll4_cfg1>; 312 313 pll4_cfg1: pll4_cfg1 { 314 st,pll_vco = <&pll4_vco_594Mhz>; 315 st,pll_div_pqr = <5 7 7>; 316 }; 317 }; 318}; 319