1 /* 2 * Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <drivers/st/stm32mp1_rcc.h> 21 #include <dt-bindings/clock/stm32mp1-clksrc.h> 22 #include <lib/mmio.h> 23 #include <lib/spinlock.h> 24 #include <lib/utils_def.h> 25 #include <libfdt.h> 26 #include <plat/common/platform.h> 27 28 #include <platform_def.h> 29 30 enum stm32mp1_pllcfg { 31 PLLCFG_M, 32 PLLCFG_N, 33 PLL_DIV_MN_NB, 34 PLLCFG_P = PLL_DIV_MN_NB, 35 PLLCFG_Q, 36 PLLCFG_R, 37 PLLCFG_O, 38 PLLCFG_NB 39 }; 40 41 #define PLL_DIV_MN_NB 2 42 #define PLL_DIV_PQR_NB 3 43 44 enum stm32mp1_pllcsg { 45 PLLCSG_MOD_PER, 46 PLLCSG_INC_STEP, 47 PLLCSG_SSCG_MODE, 48 PLLCSG_NB 49 }; 50 51 struct stm32_pll_dt_cfg { 52 bool status; 53 uint32_t src; 54 uint32_t cfg[PLLCFG_NB]; 55 uint32_t frac; 56 bool csg_enabled; 57 uint32_t csg[PLLCSG_NB]; 58 }; 59 60 struct stm32_clk_platdata { 61 uint32_t npll; 62 struct stm32_pll_dt_cfg *pll; 63 uint32_t nclksrc; 64 uint32_t *clksrc; 65 uint32_t nclkdiv; 66 uint32_t *clkdiv; 67 }; 68 69 struct stm32_clk_priv { 70 uintptr_t base; 71 const struct mux_cfg *parents; 72 const uint32_t nb_parents; 73 const struct div_cfg *div; 74 const uint32_t nb_div; 75 void *pdata; 76 }; 77 78 static struct stm32_clk_priv *stm32_clock_data; 79 80 static struct stm32_clk_priv *clk_stm32_get_priv(void) 81 { 82 return stm32_clock_data; 83 } 84 85 static int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base) 86 { 87 stm32_clock_data = priv; 88 89 priv->base = base; 90 91 return 0; 92 } 93 94 #define MAX_HSI_HZ 64000000 95 #define USB_PHY_48_MHZ 48000000 96 97 #define TIMEOUT_US_200MS U(200000) 98 #define TIMEOUT_US_1S U(1000000) 99 100 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 101 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 102 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 103 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 104 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 105 106 struct mux_cfg { 107 uint16_t offset; 108 uint8_t shift; 109 uint8_t width; 110 uint8_t bitrdy; 111 }; 112 113 struct div_cfg { 114 uint16_t offset; 115 uint8_t shift; 116 uint8_t width; 117 uint8_t bitrdy; 118 }; 119 120 #define DIV_NO_BIT_RDY UINT8_MAX 121 122 #define DIV_CFG(_id, _offset, _shift, _width, _bitrdy)\ 123 [(_id)] = {\ 124 .offset = (_offset),\ 125 .shift = (_shift),\ 126 .width = (_width),\ 127 .bitrdy = (_bitrdy),\ 128 } 129 130 static const struct div_cfg dividers_mp15[] = { 131 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 31), 132 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 31), 133 DIV_CFG(DIV_MCU, RCC_MCUDIVR, 0, 4, 31), 134 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 31), 135 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 31), 136 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 31), 137 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 31), 138 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 31), 139 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, DIV_NO_BIT_RDY), 140 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, DIV_NO_BIT_RDY), 141 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, DIV_NO_BIT_RDY), 142 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, DIV_NO_BIT_RDY), 143 DIV_CFG(DIV_ETHPTP, RCC_ETHCKSELR, 4, 4, DIV_NO_BIT_RDY), 144 }; 145 146 /* 147 * MUX CONFIG 148 */ 149 150 #define MUX_NO_BIT_RDY UINT8_MAX 151 152 #define MUXRDY_CFG(_id, _offset, _shift, _width, _bitrdy)\ 153 [(_id)] = {\ 154 .offset = (_offset),\ 155 .shift = (_shift),\ 156 .width = (_width),\ 157 .bitrdy = (_bitrdy),\ 158 } 159 160 #define MUX_CFG(_id, _offset, _shift, _width)\ 161 MUXRDY_CFG(_id, _offset, _shift, _width, MUX_NO_BIT_RDY) 162 163 static const struct mux_cfg parent_mp15[MUX_NB] = { 164 MUX_CFG(MUX_PLL12, RCC_RCK12SELR, 0, 2), 165 MUX_CFG(MUX_PLL3, RCC_RCK3SELR, 0, 2), 166 MUX_CFG(MUX_PLL4, RCC_RCK4SELR, 0, 2), 167 MUX_CFG(MUX_CKPER, RCC_CPERCKSELR, 0, 2), 168 MUXRDY_CFG(MUX_MPU, RCC_MPCKSELR, 0, 2, 31), 169 MUXRDY_CFG(MUX_AXI, RCC_ASSCKSELR, 0, 3, 31), 170 MUXRDY_CFG(MUX_MCU, RCC_MSSCKSELR, 0, 2, 31), 171 MUX_CFG(MUX_RTC, RCC_BDCR, 16, 2), 172 MUX_CFG(MUX_SDMMC12, RCC_SDMMC12CKSELR, 0, 3), 173 MUX_CFG(MUX_SPI2S23, RCC_SPI2S23CKSELR, 0, 3), 174 MUX_CFG(MUX_SPI45, RCC_SPI45CKSELR, 0, 3), 175 MUX_CFG(MUX_I2C12, RCC_I2C12CKSELR, 0, 3), 176 MUX_CFG(MUX_I2C35, RCC_I2C35CKSELR, 0, 3), 177 MUX_CFG(MUX_LPTIM23, RCC_LPTIM23CKSELR, 0, 3), 178 MUX_CFG(MUX_LPTIM45, RCC_LPTIM45CKSELR, 0, 3), 179 MUX_CFG(MUX_UART24, RCC_UART24CKSELR, 0, 3), 180 MUX_CFG(MUX_UART35, RCC_UART35CKSELR, 0, 3), 181 MUX_CFG(MUX_UART78, RCC_UART78CKSELR, 0, 3), 182 MUX_CFG(MUX_SAI1, RCC_SAI1CKSELR, 0, 3), 183 MUX_CFG(MUX_ETH, RCC_ETHCKSELR, 0, 2), 184 MUX_CFG(MUX_I2C46, RCC_I2C46CKSELR, 0, 3), 185 MUX_CFG(MUX_RNG2, RCC_RNG2CKSELR, 0, 2), 186 MUX_CFG(MUX_SDMMC3, RCC_SDMMC3CKSELR, 0, 3), 187 MUX_CFG(MUX_FMC, RCC_FMCCKSELR, 0, 2), 188 MUX_CFG(MUX_QSPI, RCC_QSPICKSELR, 0, 2), 189 MUX_CFG(MUX_USBPHY, RCC_USBCKSELR, 0, 2), 190 MUX_CFG(MUX_USBO, RCC_USBCKSELR, 4, 1), 191 MUX_CFG(MUX_SPDIF, RCC_SPDIFCKSELR, 0, 2), 192 MUX_CFG(MUX_SPI2S1, RCC_SPI2S1CKSELR, 0, 3), 193 MUX_CFG(MUX_CEC, RCC_CECCKSELR, 0, 2), 194 MUX_CFG(MUX_LPTIM1, RCC_LPTIM1CKSELR, 0, 3), 195 MUX_CFG(MUX_UART6, RCC_UART6CKSELR, 0, 3), 196 MUX_CFG(MUX_FDCAN, RCC_FDCANCKSELR, 0, 2), 197 MUX_CFG(MUX_SAI2, RCC_SAI2CKSELR, 0, 3), 198 MUX_CFG(MUX_SAI3, RCC_SAI3CKSELR, 0, 3), 199 MUX_CFG(MUX_SAI4, RCC_SAI4CKSELR, 0, 3), 200 MUX_CFG(MUX_ADC, RCC_ADCCKSELR, 0, 2), 201 MUX_CFG(MUX_DSI, RCC_DSICKSELR, 0, 1), 202 MUX_CFG(MUX_RNG1, RCC_RNG1CKSELR, 0, 2), 203 MUX_CFG(MUX_STGEN, RCC_STGENCKSELR, 0, 2), 204 MUX_CFG(MUX_UART1, RCC_UART1CKSELR, 0, 3), 205 MUX_CFG(MUX_SPI6, RCC_SPI6CKSELR, 0, 3), 206 MUX_CFG(MUX_MCO1, RCC_MCO1CFGR, 0, 3), 207 MUX_CFG(MUX_MCO2, RCC_MCO2CFGR, 0, 3), 208 }; 209 210 #define MASK_WIDTH_SHIFT(_width, _shift) \ 211 GENMASK(((_width) + (_shift) - 1U), (_shift)) 212 213 int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id) 214 { 215 const struct mux_cfg *mux; 216 uint32_t mask; 217 218 if (mux_id >= priv->nb_parents) { 219 panic(); 220 } 221 222 mux = &priv->parents[mux_id]; 223 224 mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); 225 226 return (mmio_read_32(priv->base + mux->offset) & mask) >> mux->shift; 227 } 228 229 static int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel) 230 { 231 const struct mux_cfg *mux = &priv->parents[pid]; 232 uintptr_t address = priv->base + mux->offset; 233 uint32_t mask; 234 uint64_t timeout; 235 236 mask = MASK_WIDTH_SHIFT(mux->width, mux->shift); 237 238 mmio_clrsetbits_32(address, mask, (sel << mux->shift) & mask); 239 240 if (mux->bitrdy == MUX_NO_BIT_RDY) { 241 return 0; 242 } 243 244 timeout = timeout_init_us(CLKSRC_TIMEOUT); 245 246 mask = BIT(mux->bitrdy); 247 248 while ((mmio_read_32(address) & mask) == 0U) { 249 if (timeout_elapsed(timeout)) { 250 return -ETIMEDOUT; 251 } 252 } 253 254 return 0; 255 } 256 257 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t val) 258 { 259 uint32_t data = val & CMD_DATA_MASK; 260 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 261 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 262 263 return clk_mux_set_parent(priv, mux, sel); 264 } 265 266 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value) 267 { 268 const struct div_cfg *divider; 269 uintptr_t address; 270 uint64_t timeout; 271 uint32_t mask; 272 273 if (div_id >= priv->nb_div) { 274 panic(); 275 } 276 277 divider = &priv->div[div_id]; 278 address = priv->base + divider->offset; 279 280 mask = MASK_WIDTH_SHIFT(divider->width, divider->shift); 281 mmio_clrsetbits_32(address, mask, (value << divider->shift) & mask); 282 283 if (divider->bitrdy == DIV_NO_BIT_RDY) { 284 return 0; 285 } 286 287 timeout = timeout_init_us(CLKSRC_TIMEOUT); 288 mask = BIT(divider->bitrdy); 289 290 while ((mmio_read_32(address) & mask) == 0U) { 291 if (timeout_elapsed(timeout)) { 292 return -ETIMEDOUT; 293 } 294 } 295 296 return 0; 297 } 298 299 const char *stm32mp_osc_node_label[NB_OSC] = { 300 [_LSI] = "clk-lsi", 301 [_LSE] = "clk-lse", 302 [_HSI] = "clk-hsi", 303 [_HSE] = "clk-hse", 304 [_CSI] = "clk-csi", 305 [_I2S_CKIN] = "i2s_ckin", 306 }; 307 308 enum stm32mp1_parent_id { 309 /* Oscillators are defined in enum stm32mp_osc_id */ 310 311 /* Other parent source */ 312 _HSI_KER = NB_OSC, 313 _HSE_KER, 314 _HSE_KER_DIV2, 315 _HSE_RTC, 316 _CSI_KER, 317 _PLL1_P, 318 _PLL1_Q, 319 _PLL1_R, 320 _PLL2_P, 321 _PLL2_Q, 322 _PLL2_R, 323 _PLL3_P, 324 _PLL3_Q, 325 _PLL3_R, 326 _PLL4_P, 327 _PLL4_Q, 328 _PLL4_R, 329 _ACLK, 330 _PCLK1, 331 _PCLK2, 332 _PCLK3, 333 _PCLK4, 334 _PCLK5, 335 _HCLK6, 336 _HCLK2, 337 _CK_PER, 338 _CK_MPU, 339 _CK_MCU, 340 _USB_PHY_48, 341 _PARENT_NB, 342 _UNKNOWN_ID = 0xff, 343 }; 344 345 /* Lists only the parent clock we are interested in */ 346 enum stm32mp1_parent_sel { 347 _I2C12_SEL, 348 _I2C35_SEL, 349 _STGEN_SEL, 350 _I2C46_SEL, 351 _SPI6_SEL, 352 _UART1_SEL, 353 _RNG1_SEL, 354 _UART6_SEL, 355 _UART24_SEL, 356 _UART35_SEL, 357 _UART78_SEL, 358 _SDMMC12_SEL, 359 _SDMMC3_SEL, 360 _QSPI_SEL, 361 _FMC_SEL, 362 _AXIS_SEL, 363 _MCUS_SEL, 364 _USBPHY_SEL, 365 _USBO_SEL, 366 _MPU_SEL, 367 _CKPER_SEL, 368 _RTC_SEL, 369 _PARENT_SEL_NB, 370 _UNKNOWN_SEL = 0xff, 371 }; 372 373 /* State the parent clock ID straight related to a clock */ 374 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 375 [_HSE] = CK_HSE, 376 [_HSI] = CK_HSI, 377 [_CSI] = CK_CSI, 378 [_LSE] = CK_LSE, 379 [_LSI] = CK_LSI, 380 [_I2S_CKIN] = _UNKNOWN_ID, 381 [_USB_PHY_48] = _UNKNOWN_ID, 382 [_HSI_KER] = CK_HSI, 383 [_HSE_KER] = CK_HSE, 384 [_HSE_KER_DIV2] = CK_HSE_DIV2, 385 [_HSE_RTC] = _UNKNOWN_ID, 386 [_CSI_KER] = CK_CSI, 387 [_PLL1_P] = PLL1_P, 388 [_PLL1_Q] = PLL1_Q, 389 [_PLL1_R] = PLL1_R, 390 [_PLL2_P] = PLL2_P, 391 [_PLL2_Q] = PLL2_Q, 392 [_PLL2_R] = PLL2_R, 393 [_PLL3_P] = PLL3_P, 394 [_PLL3_Q] = PLL3_Q, 395 [_PLL3_R] = PLL3_R, 396 [_PLL4_P] = PLL4_P, 397 [_PLL4_Q] = PLL4_Q, 398 [_PLL4_R] = PLL4_R, 399 [_ACLK] = CK_AXI, 400 [_PCLK1] = CK_AXI, 401 [_PCLK2] = CK_AXI, 402 [_PCLK3] = CK_AXI, 403 [_PCLK4] = CK_AXI, 404 [_PCLK5] = CK_AXI, 405 [_CK_PER] = CK_PER, 406 [_CK_MPU] = CK_MPU, 407 [_CK_MCU] = CK_MCU, 408 }; 409 410 static unsigned int clock_id2parent_id(unsigned long id) 411 { 412 unsigned int n; 413 414 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 415 if (parent_id_clock_id[n] == id) { 416 return n; 417 } 418 } 419 420 return _UNKNOWN_ID; 421 } 422 423 enum stm32mp1_pll_id { 424 _PLL1, 425 _PLL2, 426 _PLL3, 427 _PLL4, 428 _PLL_NB 429 }; 430 431 enum stm32mp1_div_id { 432 _DIV_P, 433 _DIV_Q, 434 _DIV_R, 435 _DIV_NB, 436 }; 437 438 enum stm32mp1_clksrc_id { 439 CLKSRC_MPU, 440 CLKSRC_AXI, 441 CLKSRC_MCU, 442 CLKSRC_PLL12, 443 CLKSRC_PLL3, 444 CLKSRC_PLL4, 445 CLKSRC_RTC, 446 CLKSRC_MCO1, 447 CLKSRC_MCO2, 448 CLKSRC_NB 449 }; 450 451 enum stm32mp1_clkdiv_id { 452 CLKDIV_MPU, 453 CLKDIV_AXI, 454 CLKDIV_MCU, 455 CLKDIV_APB1, 456 CLKDIV_APB2, 457 CLKDIV_APB3, 458 CLKDIV_APB4, 459 CLKDIV_APB5, 460 CLKDIV_RTC, 461 CLKDIV_MCO1, 462 CLKDIV_MCO2, 463 CLKDIV_NB 464 }; 465 466 enum stm32mp1_plltype { 467 PLL_800, 468 PLL_1600, 469 PLL_TYPE_NB 470 }; 471 472 struct stm32mp1_pll { 473 uint8_t refclk_min; 474 uint8_t refclk_max; 475 }; 476 477 struct stm32mp1_clk_gate { 478 uint16_t offset; 479 uint8_t bit; 480 uint8_t index; 481 uint8_t set_clr; 482 uint8_t secure; 483 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 484 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 485 }; 486 487 struct stm32mp1_clk_sel { 488 uint16_t offset; 489 uint8_t src; 490 uint8_t msk; 491 uint8_t nb_parent; 492 const uint8_t *parent; 493 }; 494 495 #define REFCLK_SIZE 4 496 struct stm32mp1_clk_pll { 497 enum stm32mp1_plltype plltype; 498 uint16_t rckxselr; 499 uint16_t pllxcfgr1; 500 uint16_t pllxcfgr2; 501 uint16_t pllxfracr; 502 uint16_t pllxcr; 503 uint16_t pllxcsgr; 504 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 505 }; 506 507 /* Clocks with selectable source and non set/clr register access */ 508 #define _CLK_SELEC(sec, off, b, idx, s) \ 509 { \ 510 .offset = (off), \ 511 .bit = (b), \ 512 .index = (idx), \ 513 .set_clr = 0, \ 514 .secure = (sec), \ 515 .sel = (s), \ 516 .fixed = _UNKNOWN_ID, \ 517 } 518 519 /* Clocks with fixed source and non set/clr register access */ 520 #define _CLK_FIXED(sec, off, b, idx, f) \ 521 { \ 522 .offset = (off), \ 523 .bit = (b), \ 524 .index = (idx), \ 525 .set_clr = 0, \ 526 .secure = (sec), \ 527 .sel = _UNKNOWN_SEL, \ 528 .fixed = (f), \ 529 } 530 531 /* Clocks with selectable source and set/clr register access */ 532 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 533 { \ 534 .offset = (off), \ 535 .bit = (b), \ 536 .index = (idx), \ 537 .set_clr = 1, \ 538 .secure = (sec), \ 539 .sel = (s), \ 540 .fixed = _UNKNOWN_ID, \ 541 } 542 543 /* Clocks with fixed source and set/clr register access */ 544 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 545 { \ 546 .offset = (off), \ 547 .bit = (b), \ 548 .index = (idx), \ 549 .set_clr = 1, \ 550 .secure = (sec), \ 551 .sel = _UNKNOWN_SEL, \ 552 .fixed = (f), \ 553 } 554 555 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 556 [_ ## _label ## _SEL] = { \ 557 .offset = _rcc_selr, \ 558 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 559 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 560 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 561 .parent = (_parents), \ 562 .nb_parent = ARRAY_SIZE(_parents) \ 563 } 564 565 #define _CLK_PLL(idx, type, off1, off2, off3, \ 566 off4, off5, off6, \ 567 p1, p2, p3, p4) \ 568 [(idx)] = { \ 569 .plltype = (type), \ 570 .rckxselr = (off1), \ 571 .pllxcfgr1 = (off2), \ 572 .pllxcfgr2 = (off3), \ 573 .pllxfracr = (off4), \ 574 .pllxcr = (off5), \ 575 .pllxcsgr = (off6), \ 576 .refclk[0] = (p1), \ 577 .refclk[1] = (p2), \ 578 .refclk[2] = (p3), \ 579 .refclk[3] = (p4), \ 580 } 581 582 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 583 584 #define SEC 1 585 #define N_S 0 586 587 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 588 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 589 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 590 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 591 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 592 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 593 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 594 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 595 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 596 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 597 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 598 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 599 600 #if defined(IMAGE_BL32) 601 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 602 #endif 603 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 604 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 605 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 606 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 607 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 608 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 609 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 610 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 611 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 612 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 613 614 #if defined(IMAGE_BL32) 615 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 616 #endif 617 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 618 619 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 620 621 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 622 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 623 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 624 625 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 626 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 627 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 628 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 629 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 630 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 631 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 632 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 633 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 634 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 635 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 636 637 #if defined(IMAGE_BL32) 638 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 639 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 640 #endif 641 642 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 643 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 644 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 645 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 646 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 647 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 648 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 649 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 650 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 651 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 652 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 653 654 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 655 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 656 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 657 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 658 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 659 660 #if defined(IMAGE_BL2) 661 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 662 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 663 #endif 664 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 665 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 666 #if defined(IMAGE_BL32) 667 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 668 #endif 669 670 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 671 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 672 }; 673 674 static const uint8_t i2c12_parents[] = { 675 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 676 }; 677 678 static const uint8_t i2c35_parents[] = { 679 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 680 }; 681 682 static const uint8_t stgen_parents[] = { 683 _HSI_KER, _HSE_KER 684 }; 685 686 static const uint8_t i2c46_parents[] = { 687 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 688 }; 689 690 static const uint8_t spi6_parents[] = { 691 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 692 }; 693 694 static const uint8_t usart1_parents[] = { 695 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 696 }; 697 698 static const uint8_t rng1_parents[] = { 699 _CSI, _PLL4_R, _LSE, _LSI 700 }; 701 702 static const uint8_t uart6_parents[] = { 703 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 704 }; 705 706 static const uint8_t uart234578_parents[] = { 707 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 708 }; 709 710 static const uint8_t sdmmc12_parents[] = { 711 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 712 }; 713 714 static const uint8_t sdmmc3_parents[] = { 715 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 716 }; 717 718 static const uint8_t qspi_parents[] = { 719 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 720 }; 721 722 static const uint8_t fmc_parents[] = { 723 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 724 }; 725 726 static const uint8_t axiss_parents[] = { 727 _HSI, _HSE, _PLL2_P 728 }; 729 730 static const uint8_t mcuss_parents[] = { 731 _HSI, _HSE, _CSI, _PLL3_P 732 }; 733 734 static const uint8_t usbphy_parents[] = { 735 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 736 }; 737 738 static const uint8_t usbo_parents[] = { 739 _PLL4_R, _USB_PHY_48 740 }; 741 742 static const uint8_t mpu_parents[] = { 743 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 744 }; 745 746 static const uint8_t per_parents[] = { 747 _HSI, _HSE, _CSI, 748 }; 749 750 static const uint8_t rtc_parents[] = { 751 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 752 }; 753 754 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 755 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 756 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 757 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 758 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 759 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 760 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 761 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 762 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 763 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 764 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 765 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 766 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 767 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 768 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 769 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 770 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 771 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 772 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 773 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 774 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 775 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 776 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 777 }; 778 779 /* Define characteristic of PLL according type */ 780 #define POST_DIVM_MIN 8000000U 781 #define POST_DIVM_MAX 16000000U 782 #define DIVM_MIN 0U 783 #define DIVM_MAX 63U 784 #define DIVN_MIN 24U 785 #define DIVN_MAX 99U 786 #define DIVP_MIN 0U 787 #define DIVP_MAX 127U 788 #define FRAC_MAX 8192U 789 #define VCO_MIN 800000000U 790 #define VCO_MAX 1600000000U 791 792 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 793 [PLL_800] = { 794 .refclk_min = 4, 795 .refclk_max = 16, 796 }, 797 [PLL_1600] = { 798 .refclk_min = 8, 799 .refclk_max = 16, 800 }, 801 }; 802 803 /* PLLNCFGR2 register divider by output */ 804 static const uint8_t pllncfgr2[_DIV_NB] = { 805 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 806 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 807 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 808 }; 809 810 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 811 _CLK_PLL(_PLL1, PLL_1600, 812 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 813 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 814 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 815 _CLK_PLL(_PLL2, PLL_1600, 816 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 817 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 818 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 819 _CLK_PLL(_PLL3, PLL_800, 820 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 821 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 822 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 823 _CLK_PLL(_PLL4, PLL_800, 824 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 825 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 826 _HSI, _HSE, _CSI, _I2S_CKIN), 827 }; 828 829 /* Prescaler table lookups for clock computation */ 830 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 831 static const uint8_t stm32mp1_mcu_div[16] = { 832 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 833 }; 834 835 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 836 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 837 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 838 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 839 0, 1, 2, 3, 4, 4, 4, 4 840 }; 841 842 /* div = /1 /2 /3 /4 */ 843 static const uint8_t stm32mp1_axi_div[8] = { 844 1, 2, 3, 4, 4, 4, 4, 4 845 }; 846 847 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 848 [_HSI] = "HSI", 849 [_HSE] = "HSE", 850 [_CSI] = "CSI", 851 [_LSI] = "LSI", 852 [_LSE] = "LSE", 853 [_I2S_CKIN] = "I2S_CKIN", 854 [_HSI_KER] = "HSI_KER", 855 [_HSE_KER] = "HSE_KER", 856 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 857 [_HSE_RTC] = "HSE_RTC", 858 [_CSI_KER] = "CSI_KER", 859 [_PLL1_P] = "PLL1_P", 860 [_PLL1_Q] = "PLL1_Q", 861 [_PLL1_R] = "PLL1_R", 862 [_PLL2_P] = "PLL2_P", 863 [_PLL2_Q] = "PLL2_Q", 864 [_PLL2_R] = "PLL2_R", 865 [_PLL3_P] = "PLL3_P", 866 [_PLL3_Q] = "PLL3_Q", 867 [_PLL3_R] = "PLL3_R", 868 [_PLL4_P] = "PLL4_P", 869 [_PLL4_Q] = "PLL4_Q", 870 [_PLL4_R] = "PLL4_R", 871 [_ACLK] = "ACLK", 872 [_PCLK1] = "PCLK1", 873 [_PCLK2] = "PCLK2", 874 [_PCLK3] = "PCLK3", 875 [_PCLK4] = "PCLK4", 876 [_PCLK5] = "PCLK5", 877 [_HCLK6] = "KCLK6", 878 [_HCLK2] = "HCLK2", 879 [_CK_PER] = "CK_PER", 880 [_CK_MPU] = "CK_MPU", 881 [_CK_MCU] = "CK_MCU", 882 [_USB_PHY_48] = "USB_PHY_48", 883 }; 884 885 /* RCC clock device driver private */ 886 static unsigned long stm32mp1_osc[NB_OSC]; 887 static struct spinlock reg_lock; 888 static unsigned int gate_refcounts[NB_GATES]; 889 static struct spinlock refcount_lock; 890 891 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 892 { 893 return &stm32mp1_clk_gate[idx]; 894 } 895 896 #if defined(IMAGE_BL32) 897 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 898 { 899 return gate->secure == N_S; 900 } 901 #endif 902 903 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 904 { 905 return &stm32mp1_clk_sel[idx]; 906 } 907 908 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 909 { 910 return &stm32mp1_clk_pll[idx]; 911 } 912 913 static void stm32mp1_clk_lock(struct spinlock *lock) 914 { 915 if (stm32mp_lock_available()) { 916 /* Assume interrupts are masked */ 917 spin_lock(lock); 918 } 919 } 920 921 static void stm32mp1_clk_unlock(struct spinlock *lock) 922 { 923 if (stm32mp_lock_available()) { 924 spin_unlock(lock); 925 } 926 } 927 928 bool stm32mp1_rcc_is_secure(void) 929 { 930 uintptr_t rcc_base = stm32mp_rcc_base(); 931 uint32_t mask = RCC_TZCR_TZEN; 932 933 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 934 } 935 936 bool stm32mp1_rcc_is_mckprot(void) 937 { 938 uintptr_t rcc_base = stm32mp_rcc_base(); 939 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 940 941 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 942 } 943 944 void stm32mp1_clk_rcc_regs_lock(void) 945 { 946 stm32mp1_clk_lock(®_lock); 947 } 948 949 void stm32mp1_clk_rcc_regs_unlock(void) 950 { 951 stm32mp1_clk_unlock(®_lock); 952 } 953 954 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 955 { 956 if (idx >= NB_OSC) { 957 return 0; 958 } 959 960 return stm32mp1_osc[idx]; 961 } 962 963 static int stm32mp1_clk_get_gated_id(unsigned long id) 964 { 965 unsigned int i; 966 967 for (i = 0U; i < NB_GATES; i++) { 968 if (gate_ref(i)->index == id) { 969 return i; 970 } 971 } 972 973 ERROR("%s: clk id %lu not found\n", __func__, id); 974 975 return -EINVAL; 976 } 977 978 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 979 { 980 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 981 } 982 983 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 984 { 985 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 986 } 987 988 static int stm32mp1_clk_get_parent(unsigned long id) 989 { 990 const struct stm32mp1_clk_sel *sel; 991 uint32_t p_sel; 992 int i; 993 enum stm32mp1_parent_id p; 994 enum stm32mp1_parent_sel s; 995 uintptr_t rcc_base = stm32mp_rcc_base(); 996 997 /* Few non gateable clock have a static parent ID, find them */ 998 i = (int)clock_id2parent_id(id); 999 if (i != _UNKNOWN_ID) { 1000 return i; 1001 } 1002 1003 i = stm32mp1_clk_get_gated_id(id); 1004 if (i < 0) { 1005 panic(); 1006 } 1007 1008 p = stm32mp1_clk_get_fixed_parent(i); 1009 if (p < _PARENT_NB) { 1010 return (int)p; 1011 } 1012 1013 s = stm32mp1_clk_get_sel(i); 1014 if (s == _UNKNOWN_SEL) { 1015 return -EINVAL; 1016 } 1017 if (s >= _PARENT_SEL_NB) { 1018 panic(); 1019 } 1020 1021 sel = clk_sel_ref(s); 1022 p_sel = (mmio_read_32(rcc_base + sel->offset) & 1023 (sel->msk << sel->src)) >> sel->src; 1024 if (p_sel < sel->nb_parent) { 1025 return (int)sel->parent[p_sel]; 1026 } 1027 1028 return -EINVAL; 1029 } 1030 1031 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 1032 { 1033 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 1034 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 1035 1036 return stm32mp1_clk_get_fixed(pll->refclk[src]); 1037 } 1038 1039 /* 1040 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 1041 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 1042 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 1043 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 1044 */ 1045 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 1046 { 1047 unsigned long refclk, fvco; 1048 uint32_t cfgr1, fracr, divm, divn; 1049 uintptr_t rcc_base = stm32mp_rcc_base(); 1050 1051 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 1052 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 1053 1054 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 1055 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 1056 1057 refclk = stm32mp1_pll_get_fref(pll); 1058 1059 /* 1060 * With FRACV : 1061 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 1062 * Without FRACV 1063 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 1064 */ 1065 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 1066 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 1067 RCC_PLLNFRACR_FRACV_SHIFT; 1068 unsigned long long numerator, denominator; 1069 1070 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 1071 numerator = refclk * numerator; 1072 denominator = ((unsigned long long)divm + 1U) << 13; 1073 fvco = (unsigned long)(numerator / denominator); 1074 } else { 1075 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 1076 } 1077 1078 return fvco; 1079 } 1080 1081 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 1082 enum stm32mp1_div_id div_id) 1083 { 1084 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1085 unsigned long dfout; 1086 uint32_t cfgr2, divy; 1087 1088 if (div_id >= _DIV_NB) { 1089 return 0; 1090 } 1091 1092 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 1093 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 1094 1095 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 1096 1097 return dfout; 1098 } 1099 1100 static unsigned long get_clock_rate(int p) 1101 { 1102 uint32_t reg, clkdiv; 1103 unsigned long clock = 0; 1104 uintptr_t rcc_base = stm32mp_rcc_base(); 1105 1106 switch (p) { 1107 case _CK_MPU: 1108 /* MPU sub system */ 1109 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 1110 switch (reg & RCC_SELR_SRC_MASK) { 1111 case RCC_MPCKSELR_HSI: 1112 clock = stm32mp1_clk_get_fixed(_HSI); 1113 break; 1114 case RCC_MPCKSELR_HSE: 1115 clock = stm32mp1_clk_get_fixed(_HSE); 1116 break; 1117 case RCC_MPCKSELR_PLL: 1118 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1119 break; 1120 case RCC_MPCKSELR_PLL_MPUDIV: 1121 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1122 1123 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 1124 clkdiv = reg & RCC_MPUDIV_MASK; 1125 clock >>= stm32mp1_mpu_div[clkdiv]; 1126 break; 1127 default: 1128 break; 1129 } 1130 break; 1131 /* AXI sub system */ 1132 case _ACLK: 1133 case _HCLK2: 1134 case _HCLK6: 1135 case _PCLK4: 1136 case _PCLK5: 1137 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 1138 switch (reg & RCC_SELR_SRC_MASK) { 1139 case RCC_ASSCKSELR_HSI: 1140 clock = stm32mp1_clk_get_fixed(_HSI); 1141 break; 1142 case RCC_ASSCKSELR_HSE: 1143 clock = stm32mp1_clk_get_fixed(_HSE); 1144 break; 1145 case RCC_ASSCKSELR_PLL: 1146 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1147 break; 1148 default: 1149 break; 1150 } 1151 1152 /* System clock divider */ 1153 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 1154 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 1155 1156 switch (p) { 1157 case _PCLK4: 1158 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 1159 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1160 break; 1161 case _PCLK5: 1162 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 1163 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1164 break; 1165 default: 1166 break; 1167 } 1168 break; 1169 /* MCU sub system */ 1170 case _CK_MCU: 1171 case _PCLK1: 1172 case _PCLK2: 1173 case _PCLK3: 1174 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 1175 switch (reg & RCC_SELR_SRC_MASK) { 1176 case RCC_MSSCKSELR_HSI: 1177 clock = stm32mp1_clk_get_fixed(_HSI); 1178 break; 1179 case RCC_MSSCKSELR_HSE: 1180 clock = stm32mp1_clk_get_fixed(_HSE); 1181 break; 1182 case RCC_MSSCKSELR_CSI: 1183 clock = stm32mp1_clk_get_fixed(_CSI); 1184 break; 1185 case RCC_MSSCKSELR_PLL: 1186 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1187 break; 1188 default: 1189 break; 1190 } 1191 1192 /* MCU clock divider */ 1193 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 1194 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 1195 1196 switch (p) { 1197 case _PCLK1: 1198 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 1199 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1200 break; 1201 case _PCLK2: 1202 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 1203 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1204 break; 1205 case _PCLK3: 1206 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 1207 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 1208 break; 1209 case _CK_MCU: 1210 default: 1211 break; 1212 } 1213 break; 1214 case _CK_PER: 1215 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 1216 switch (reg & RCC_SELR_SRC_MASK) { 1217 case RCC_CPERCKSELR_HSI: 1218 clock = stm32mp1_clk_get_fixed(_HSI); 1219 break; 1220 case RCC_CPERCKSELR_HSE: 1221 clock = stm32mp1_clk_get_fixed(_HSE); 1222 break; 1223 case RCC_CPERCKSELR_CSI: 1224 clock = stm32mp1_clk_get_fixed(_CSI); 1225 break; 1226 default: 1227 break; 1228 } 1229 break; 1230 case _HSI: 1231 case _HSI_KER: 1232 clock = stm32mp1_clk_get_fixed(_HSI); 1233 break; 1234 case _CSI: 1235 case _CSI_KER: 1236 clock = stm32mp1_clk_get_fixed(_CSI); 1237 break; 1238 case _HSE: 1239 case _HSE_KER: 1240 clock = stm32mp1_clk_get_fixed(_HSE); 1241 break; 1242 case _HSE_KER_DIV2: 1243 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 1244 break; 1245 case _HSE_RTC: 1246 clock = stm32mp1_clk_get_fixed(_HSE); 1247 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 1248 break; 1249 case _LSI: 1250 clock = stm32mp1_clk_get_fixed(_LSI); 1251 break; 1252 case _LSE: 1253 clock = stm32mp1_clk_get_fixed(_LSE); 1254 break; 1255 /* PLL */ 1256 case _PLL1_P: 1257 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1258 break; 1259 case _PLL1_Q: 1260 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1261 break; 1262 case _PLL1_R: 1263 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1264 break; 1265 case _PLL2_P: 1266 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1267 break; 1268 case _PLL2_Q: 1269 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1270 break; 1271 case _PLL2_R: 1272 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1273 break; 1274 case _PLL3_P: 1275 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1276 break; 1277 case _PLL3_Q: 1278 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1279 break; 1280 case _PLL3_R: 1281 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1282 break; 1283 case _PLL4_P: 1284 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1285 break; 1286 case _PLL4_Q: 1287 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1288 break; 1289 case _PLL4_R: 1290 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1291 break; 1292 /* Other */ 1293 case _USB_PHY_48: 1294 clock = USB_PHY_48_MHZ; 1295 break; 1296 default: 1297 break; 1298 } 1299 1300 return clock; 1301 } 1302 1303 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1304 { 1305 uintptr_t rcc_base = stm32mp_rcc_base(); 1306 1307 VERBOSE("Enable clock %u\n", gate->index); 1308 1309 if (gate->set_clr != 0U) { 1310 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1311 } else { 1312 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1313 } 1314 } 1315 1316 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1317 { 1318 uintptr_t rcc_base = stm32mp_rcc_base(); 1319 1320 VERBOSE("Disable clock %u\n", gate->index); 1321 1322 if (gate->set_clr != 0U) { 1323 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1324 BIT(gate->bit)); 1325 } else { 1326 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1327 } 1328 } 1329 1330 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1331 { 1332 uintptr_t rcc_base = stm32mp_rcc_base(); 1333 1334 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1335 } 1336 1337 /* Oscillators and PLLs are not gated at runtime */ 1338 static bool clock_is_always_on(unsigned long id) 1339 { 1340 switch (id) { 1341 case CK_HSE: 1342 case CK_CSI: 1343 case CK_LSI: 1344 case CK_LSE: 1345 case CK_HSI: 1346 case CK_HSE_DIV2: 1347 case PLL1_Q: 1348 case PLL1_R: 1349 case PLL2_P: 1350 case PLL2_Q: 1351 case PLL2_R: 1352 case PLL3_P: 1353 case PLL3_Q: 1354 case PLL3_R: 1355 case CK_AXI: 1356 case CK_MPU: 1357 case CK_MCU: 1358 case RTC: 1359 return true; 1360 default: 1361 return false; 1362 } 1363 } 1364 1365 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1366 { 1367 const struct stm32mp1_clk_gate *gate; 1368 int i; 1369 1370 if (clock_is_always_on(id)) { 1371 return; 1372 } 1373 1374 i = stm32mp1_clk_get_gated_id(id); 1375 if (i < 0) { 1376 ERROR("Clock %lu can't be enabled\n", id); 1377 panic(); 1378 } 1379 1380 gate = gate_ref(i); 1381 1382 if (!with_refcnt) { 1383 __clk_enable(gate); 1384 return; 1385 } 1386 1387 #if defined(IMAGE_BL32) 1388 if (gate_is_non_secure(gate)) { 1389 /* Enable non-secure clock w/o any refcounting */ 1390 __clk_enable(gate); 1391 return; 1392 } 1393 #endif 1394 1395 stm32mp1_clk_lock(&refcount_lock); 1396 1397 if (gate_refcounts[i] == 0U) { 1398 __clk_enable(gate); 1399 } 1400 1401 gate_refcounts[i]++; 1402 if (gate_refcounts[i] == UINT_MAX) { 1403 ERROR("Clock %lu refcount reached max value\n", id); 1404 panic(); 1405 } 1406 1407 stm32mp1_clk_unlock(&refcount_lock); 1408 } 1409 1410 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1411 { 1412 const struct stm32mp1_clk_gate *gate; 1413 int i; 1414 1415 if (clock_is_always_on(id)) { 1416 return; 1417 } 1418 1419 i = stm32mp1_clk_get_gated_id(id); 1420 if (i < 0) { 1421 ERROR("Clock %lu can't be disabled\n", id); 1422 panic(); 1423 } 1424 1425 gate = gate_ref(i); 1426 1427 if (!with_refcnt) { 1428 __clk_disable(gate); 1429 return; 1430 } 1431 1432 #if defined(IMAGE_BL32) 1433 if (gate_is_non_secure(gate)) { 1434 /* Don't disable non-secure clocks */ 1435 return; 1436 } 1437 #endif 1438 1439 stm32mp1_clk_lock(&refcount_lock); 1440 1441 if (gate_refcounts[i] == 0U) { 1442 ERROR("Clock %lu refcount reached 0\n", id); 1443 panic(); 1444 } 1445 gate_refcounts[i]--; 1446 1447 if (gate_refcounts[i] == 0U) { 1448 __clk_disable(gate); 1449 } 1450 1451 stm32mp1_clk_unlock(&refcount_lock); 1452 } 1453 1454 static int stm32mp_clk_enable(unsigned long id) 1455 { 1456 __stm32mp1_clk_enable(id, true); 1457 1458 return 0; 1459 } 1460 1461 static void stm32mp_clk_disable(unsigned long id) 1462 { 1463 __stm32mp1_clk_disable(id, true); 1464 } 1465 1466 static bool stm32mp_clk_is_enabled(unsigned long id) 1467 { 1468 int i; 1469 1470 if (clock_is_always_on(id)) { 1471 return true; 1472 } 1473 1474 i = stm32mp1_clk_get_gated_id(id); 1475 if (i < 0) { 1476 panic(); 1477 } 1478 1479 return __clk_is_enabled(gate_ref(i)); 1480 } 1481 1482 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1483 { 1484 uintptr_t rcc_base = stm32mp_rcc_base(); 1485 int p = stm32mp1_clk_get_parent(id); 1486 uint32_t prescaler, timpre; 1487 unsigned long parent_rate; 1488 1489 if (p < 0) { 1490 return 0; 1491 } 1492 1493 parent_rate = get_clock_rate(p); 1494 1495 switch (id) { 1496 case TIM2_K: 1497 case TIM3_K: 1498 case TIM4_K: 1499 case TIM5_K: 1500 case TIM6_K: 1501 case TIM7_K: 1502 case TIM12_K: 1503 case TIM13_K: 1504 case TIM14_K: 1505 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1506 RCC_APBXDIV_MASK; 1507 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1508 RCC_TIMGXPRER_TIMGXPRE; 1509 break; 1510 1511 case TIM1_K: 1512 case TIM8_K: 1513 case TIM15_K: 1514 case TIM16_K: 1515 case TIM17_K: 1516 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1517 RCC_APBXDIV_MASK; 1518 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1519 RCC_TIMGXPRER_TIMGXPRE; 1520 break; 1521 1522 default: 1523 return parent_rate; 1524 } 1525 1526 if (prescaler == 0U) { 1527 return parent_rate; 1528 } 1529 1530 return parent_rate * (timpre + 1U) * 2U; 1531 } 1532 1533 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1534 { 1535 uintptr_t address = stm32mp_rcc_base() + offset; 1536 1537 if (enable) { 1538 mmio_setbits_32(address, mask_on); 1539 } else { 1540 mmio_clrbits_32(address, mask_on); 1541 } 1542 } 1543 1544 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1545 { 1546 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1547 uintptr_t address = stm32mp_rcc_base() + offset; 1548 1549 mmio_write_32(address, mask_on); 1550 } 1551 1552 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1553 { 1554 uint64_t timeout; 1555 uint32_t mask_test; 1556 uintptr_t address = stm32mp_rcc_base() + offset; 1557 1558 if (enable) { 1559 mask_test = mask_rdy; 1560 } else { 1561 mask_test = 0; 1562 } 1563 1564 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1565 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1566 if (timeout_elapsed(timeout)) { 1567 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1568 mask_rdy, address, enable, mmio_read_32(address)); 1569 return -ETIMEDOUT; 1570 } 1571 } 1572 1573 return 0; 1574 } 1575 1576 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1577 { 1578 uint32_t value; 1579 uintptr_t rcc_base = stm32mp_rcc_base(); 1580 1581 /* Do not reconfigure LSE if it is already ON */ 1582 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { 1583 return; 1584 } 1585 1586 if (digbyp) { 1587 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1588 } 1589 1590 if (bypass || digbyp) { 1591 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1592 } 1593 1594 /* 1595 * Warning: not recommended to switch directly from "high drive" 1596 * to "medium low drive", and vice-versa. 1597 */ 1598 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1599 RCC_BDCR_LSEDRV_SHIFT; 1600 1601 while (value != lsedrv) { 1602 if (value > lsedrv) { 1603 value--; 1604 } else { 1605 value++; 1606 } 1607 1608 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1609 RCC_BDCR_LSEDRV_MASK, 1610 value << RCC_BDCR_LSEDRV_SHIFT); 1611 } 1612 1613 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1614 } 1615 1616 static void stm32mp1_lse_wait(void) 1617 { 1618 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1619 VERBOSE("%s: failed\n", __func__); 1620 } 1621 } 1622 1623 static void stm32mp1_lsi_set(bool enable) 1624 { 1625 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1626 1627 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1628 VERBOSE("%s: failed\n", __func__); 1629 } 1630 } 1631 1632 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1633 { 1634 uintptr_t rcc_base = stm32mp_rcc_base(); 1635 1636 if (digbyp) { 1637 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1638 } 1639 1640 if (bypass || digbyp) { 1641 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1642 } 1643 1644 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1645 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1646 VERBOSE("%s: failed\n", __func__); 1647 } 1648 1649 if (css) { 1650 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1651 } 1652 1653 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1654 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1655 (!(digbyp || bypass))) { 1656 panic(); 1657 } 1658 #endif 1659 } 1660 1661 static void stm32mp1_csi_set(bool enable) 1662 { 1663 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1664 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1665 VERBOSE("%s: failed\n", __func__); 1666 } 1667 } 1668 1669 static void stm32mp1_hsi_set(bool enable) 1670 { 1671 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1672 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1673 VERBOSE("%s: failed\n", __func__); 1674 } 1675 } 1676 1677 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1678 { 1679 uint64_t timeout; 1680 uintptr_t rcc_base = stm32mp_rcc_base(); 1681 uintptr_t address = rcc_base + RCC_OCRDYR; 1682 1683 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1684 RCC_HSICFGR_HSIDIV_MASK, 1685 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1686 1687 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1688 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1689 if (timeout_elapsed(timeout)) { 1690 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1691 address, mmio_read_32(address)); 1692 return -ETIMEDOUT; 1693 } 1694 } 1695 1696 return 0; 1697 } 1698 1699 static int stm32mp1_hsidiv(unsigned long hsifreq) 1700 { 1701 uint8_t hsidiv; 1702 uint32_t hsidivfreq = MAX_HSI_HZ; 1703 1704 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1705 if (hsidivfreq == hsifreq) { 1706 break; 1707 } 1708 1709 hsidivfreq /= 2U; 1710 } 1711 1712 if (hsidiv == 4U) { 1713 ERROR("Invalid clk-hsi frequency\n"); 1714 return -1; 1715 } 1716 1717 if (hsidiv != 0U) { 1718 return stm32mp1_set_hsidiv(hsidiv); 1719 } 1720 1721 return 0; 1722 } 1723 1724 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1725 unsigned int clksrc, 1726 uint32_t *pllcfg, uint32_t fracv) 1727 { 1728 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1729 uintptr_t rcc_base = stm32mp_rcc_base(); 1730 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1731 enum stm32mp1_plltype type = pll->plltype; 1732 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1733 unsigned long refclk; 1734 uint32_t ifrge = 0U; 1735 uint32_t src, value; 1736 1737 /* Check PLL output */ 1738 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1739 return false; 1740 } 1741 1742 /* Check current clksrc */ 1743 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1744 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1745 return false; 1746 } 1747 1748 /* Check Div */ 1749 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1750 1751 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1752 (pllcfg[PLLCFG_M] + 1U); 1753 1754 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1755 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1756 return false; 1757 } 1758 1759 if ((type == PLL_800) && (refclk >= 8000000U)) { 1760 ifrge = 1U; 1761 } 1762 1763 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1764 RCC_PLLNCFGR1_DIVN_MASK; 1765 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1766 RCC_PLLNCFGR1_DIVM_MASK; 1767 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1768 RCC_PLLNCFGR1_IFRGE_MASK; 1769 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1770 return false; 1771 } 1772 1773 /* Fractional configuration */ 1774 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1775 value |= RCC_PLLNFRACR_FRACLE; 1776 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1777 return false; 1778 } 1779 1780 /* Output config */ 1781 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1782 RCC_PLLNCFGR2_DIVP_MASK; 1783 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1784 RCC_PLLNCFGR2_DIVQ_MASK; 1785 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1786 RCC_PLLNCFGR2_DIVR_MASK; 1787 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1788 return false; 1789 } 1790 1791 return true; 1792 } 1793 1794 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1795 { 1796 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1797 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1798 1799 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1800 mmio_clrsetbits_32(pllxcr, 1801 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1802 RCC_PLLNCR_DIVREN, 1803 RCC_PLLNCR_PLLON); 1804 } 1805 1806 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1807 { 1808 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1809 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1810 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1811 1812 /* Wait PLL lock */ 1813 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1814 if (timeout_elapsed(timeout)) { 1815 ERROR("PLL%u start failed @ 0x%lx: 0x%x\n", 1816 pll_id, pllxcr, mmio_read_32(pllxcr)); 1817 return -ETIMEDOUT; 1818 } 1819 } 1820 1821 /* Start the requested output */ 1822 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1823 1824 return 0; 1825 } 1826 1827 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1828 { 1829 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1830 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1831 uint64_t timeout; 1832 1833 /* Stop all output */ 1834 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1835 RCC_PLLNCR_DIVREN); 1836 1837 /* Stop PLL */ 1838 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1839 1840 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1841 /* Wait PLL stopped */ 1842 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1843 if (timeout_elapsed(timeout)) { 1844 ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n", 1845 pll_id, pllxcr, mmio_read_32(pllxcr)); 1846 return -ETIMEDOUT; 1847 } 1848 } 1849 1850 return 0; 1851 } 1852 1853 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1854 uint32_t *pllcfg) 1855 { 1856 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1857 uintptr_t rcc_base = stm32mp_rcc_base(); 1858 uint32_t value; 1859 1860 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1861 RCC_PLLNCFGR2_DIVP_MASK; 1862 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1863 RCC_PLLNCFGR2_DIVQ_MASK; 1864 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1865 RCC_PLLNCFGR2_DIVR_MASK; 1866 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1867 } 1868 1869 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1870 uint32_t *pllcfg, uint32_t fracv) 1871 { 1872 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1873 uintptr_t rcc_base = stm32mp_rcc_base(); 1874 enum stm32mp1_plltype type = pll->plltype; 1875 unsigned long refclk; 1876 uint32_t ifrge = 0; 1877 uint32_t src, value; 1878 1879 src = mmio_read_32(rcc_base + pll->rckxselr) & 1880 RCC_SELR_REFCLK_SRC_MASK; 1881 1882 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1883 (pllcfg[PLLCFG_M] + 1U); 1884 1885 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1886 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1887 return -EINVAL; 1888 } 1889 1890 if ((type == PLL_800) && (refclk >= 8000000U)) { 1891 ifrge = 1U; 1892 } 1893 1894 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1895 RCC_PLLNCFGR1_DIVN_MASK; 1896 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1897 RCC_PLLNCFGR1_DIVM_MASK; 1898 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1899 RCC_PLLNCFGR1_IFRGE_MASK; 1900 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1901 1902 /* Fractional configuration */ 1903 value = 0; 1904 mmio_write_32(rcc_base + pll->pllxfracr, value); 1905 1906 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1907 mmio_write_32(rcc_base + pll->pllxfracr, value); 1908 1909 value |= RCC_PLLNFRACR_FRACLE; 1910 mmio_write_32(rcc_base + pll->pllxfracr, value); 1911 1912 stm32mp1_pll_config_output(pll_id, pllcfg); 1913 1914 return 0; 1915 } 1916 1917 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1918 { 1919 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1920 uint32_t pllxcsg = 0; 1921 1922 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1923 RCC_PLLNCSGR_MOD_PER_MASK; 1924 1925 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1926 RCC_PLLNCSGR_INC_STEP_MASK; 1927 1928 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1929 RCC_PLLNCSGR_SSCG_MODE_MASK; 1930 1931 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1932 1933 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1934 RCC_PLLNCR_SSCG_CTRL); 1935 } 1936 1937 static int clk_compute_pll1_settings(unsigned long input_freq, 1938 uint32_t freq_khz, 1939 uint32_t *pllcfg, uint32_t *fracv) 1940 { 1941 unsigned long long best_diff = ULLONG_MAX; 1942 unsigned int divm; 1943 1944 /* Following parameters have always the same value */ 1945 pllcfg[PLLCFG_Q] = 0U; 1946 pllcfg[PLLCFG_R] = 0U; 1947 pllcfg[PLLCFG_O] = PQR(1, 0, 0); 1948 1949 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) { 1950 unsigned long post_divm = input_freq / divm; 1951 unsigned int divp; 1952 1953 if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) { 1954 continue; 1955 } 1956 1957 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) { 1958 unsigned long long output_freq = freq_khz * 1000ULL; 1959 unsigned long long freq; 1960 unsigned long long divn; 1961 unsigned long long frac; 1962 unsigned int i; 1963 1964 freq = output_freq * divm * (divp + 1U); 1965 1966 divn = (freq / input_freq) - 1U; 1967 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { 1968 continue; 1969 } 1970 1971 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); 1972 1973 /* 2 loops to refine the fractional part */ 1974 for (i = 2U; i != 0U; i--) { 1975 unsigned long long diff; 1976 unsigned long long vco; 1977 1978 if (frac > FRAC_MAX) { 1979 break; 1980 } 1981 1982 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); 1983 1984 if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) { 1985 frac++; 1986 continue; 1987 } 1988 1989 freq = vco / (divp + 1U); 1990 if (output_freq < freq) { 1991 diff = freq - output_freq; 1992 } else { 1993 diff = output_freq - freq; 1994 } 1995 1996 if (diff < best_diff) { 1997 pllcfg[PLLCFG_M] = divm - 1U; 1998 pllcfg[PLLCFG_N] = (uint32_t)divn; 1999 pllcfg[PLLCFG_P] = divp; 2000 *fracv = (uint32_t)frac; 2001 2002 if (diff == 0U) { 2003 return 0; 2004 } 2005 2006 best_diff = diff; 2007 } 2008 2009 frac++; 2010 } 2011 } 2012 } 2013 2014 if (best_diff == ULLONG_MAX) { 2015 return -EINVAL; 2016 } 2017 2018 return 0; 2019 } 2020 2021 static int clk_get_pll1_settings(uint32_t clksrc, uint32_t freq_khz, 2022 uint32_t *pllcfg, uint32_t *fracv) 2023 { 2024 unsigned long input_freq = 0UL; 2025 2026 assert(pllcfg != NULL); 2027 assert(fracv != NULL); 2028 2029 switch (clksrc) { 2030 case CLK_PLL12_HSI: 2031 input_freq = stm32mp_clk_get_rate(CK_HSI); 2032 break; 2033 case CLK_PLL12_HSE: 2034 input_freq = stm32mp_clk_get_rate(CK_HSE); 2035 break; 2036 default: 2037 break; 2038 } 2039 2040 if (input_freq == 0UL) { 2041 panic(); 2042 } 2043 2044 return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv); 2045 } 2046 2047 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv) 2048 { 2049 struct stm32_clk_platdata *pdata = priv->pdata; 2050 uint32_t i; 2051 2052 for (i = 0U; i < pdata->nclkdiv; i++) { 2053 uint32_t div_id, div_n; 2054 uint32_t val; 2055 int ret; 2056 2057 val = pdata->clkdiv[i] & CMD_DATA_MASK; 2058 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; 2059 div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 2060 2061 ret = clk_stm32_set_div(priv, div_id, div_n); 2062 if (ret != 0) { 2063 return ret; 2064 } 2065 } 2066 2067 return 0; 2068 } 2069 2070 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) 2071 { 2072 uint32_t sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 2073 uint32_t enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; 2074 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; 2075 2076 if (binding_id == RTC) { 2077 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 2078 2079 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || (enable != 0U)) { 2080 mmio_clrsetbits_32(address, RCC_BDCR_RTCSRC_MASK, 2081 (sel & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 2082 2083 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 2084 } 2085 } 2086 2087 return 0; 2088 } 2089 2090 static int stm32_clk_configure_by_addr_val(struct stm32_clk_priv *priv, 2091 uint32_t data) 2092 { 2093 uint32_t addr = data >> CLK_ADDR_SHIFT; 2094 uint32_t val = data & CLK_ADDR_VAL_MASK; 2095 2096 mmio_setbits_32(priv->base + addr, val); 2097 2098 return 0; 2099 } 2100 2101 static int stm32_clk_source_configure(struct stm32_clk_priv *priv) 2102 { 2103 struct stm32_clk_platdata *pdata = priv->pdata; 2104 bool ckper_disabled = false; 2105 uint32_t i; 2106 2107 for (i = 0U; i < pdata->nclksrc; i++) { 2108 uint32_t val = pdata->clksrc[i]; 2109 uint32_t cmd, cmd_data; 2110 int ret; 2111 2112 if (val & CMD_ADDR_BIT) { 2113 ret = stm32_clk_configure_by_addr_val(priv, val & ~CMD_ADDR_BIT); 2114 if (ret != 0) { 2115 return ret; 2116 } 2117 2118 continue; 2119 } 2120 2121 if (val == (uint32_t)CLK_CKPER_DISABLED) { 2122 ckper_disabled = true; 2123 continue; 2124 } 2125 2126 cmd = (val & CMD_MASK) >> CMD_SHIFT; 2127 cmd_data = val & ~CMD_MASK; 2128 2129 switch (cmd) { 2130 case CMD_MUX: 2131 ret = stm32_clk_configure_mux(priv, cmd_data); 2132 break; 2133 2134 case CMD_CLK: 2135 ret = stm32_clk_configure_clk(priv, cmd_data); 2136 break; 2137 default: 2138 ret = -EINVAL; 2139 break; 2140 } 2141 2142 if (ret != 0) { 2143 return ret; 2144 } 2145 } 2146 2147 /* 2148 * CKPER is source for some peripheral clocks 2149 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2150 * only if previous clock is still ON 2151 * => deactivate CKPER only after switching clock 2152 */ 2153 if (!ckper_disabled) { 2154 return 0; 2155 } 2156 2157 return stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED); 2158 } 2159 2160 static int stm32mp1_pll_configure_src(struct stm32_clk_priv *priv, int pll_idx) 2161 { 2162 struct stm32_clk_platdata *pdata = priv->pdata; 2163 struct stm32_pll_dt_cfg *pll_conf = &pdata->pll[pll_idx]; 2164 2165 if (!pll_conf->status) { 2166 return 0; 2167 } 2168 2169 return stm32_clk_configure_mux(priv, pll_conf->src); 2170 } 2171 2172 int stm32mp1_clk_init(void) 2173 { 2174 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 2175 struct stm32_clk_platdata *pdata = priv->pdata; 2176 struct stm32_pll_dt_cfg *pll_conf = pdata->pll; 2177 int ret; 2178 enum stm32mp1_pll_id i; 2179 bool lse_css = false; 2180 bool pll3_preserve = false; 2181 bool pll4_preserve = false; 2182 bool pll4_bootrom = false; 2183 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 2184 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 2185 uint32_t usbreg_bootrom = 0U; 2186 2187 if (!pll_conf[_PLL1].status) { 2188 ret = clk_get_pll1_settings(pll_conf[_PLL2].src, PLL1_NOMINAL_FREQ_IN_KHZ, 2189 pll_conf[_PLL1].cfg, &pll_conf[_PLL1].frac); 2190 if (ret != 0) { 2191 return ret; 2192 } 2193 2194 pll_conf[_PLL1].status = true; 2195 pll_conf[_PLL1].src = pll_conf[_PLL2].src; 2196 } 2197 2198 /* 2199 * Switch ON oscillator found in device-tree. 2200 * Note: HSI already ON after BootROM stage. 2201 */ 2202 if (stm32mp1_osc[_LSI] != 0U) { 2203 stm32mp1_lsi_set(true); 2204 } 2205 if (stm32mp1_osc[_LSE] != 0U) { 2206 const char *name = stm32mp_osc_node_label[_LSE]; 2207 bool bypass, digbyp; 2208 uint32_t lsedrv; 2209 2210 bypass = fdt_clk_read_bool(name, "st,bypass"); 2211 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 2212 lse_css = fdt_clk_read_bool(name, "st,css"); 2213 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 2214 LSEDRV_MEDIUM_HIGH); 2215 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 2216 } 2217 if (stm32mp1_osc[_HSE] != 0U) { 2218 const char *name = stm32mp_osc_node_label[_HSE]; 2219 bool bypass, digbyp, css; 2220 2221 bypass = fdt_clk_read_bool(name, "st,bypass"); 2222 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 2223 css = fdt_clk_read_bool(name, "st,css"); 2224 stm32mp1_hse_enable(bypass, digbyp, css); 2225 } 2226 /* 2227 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 2228 * => switch on CSI even if node is not present in device tree 2229 */ 2230 stm32mp1_csi_set(true); 2231 2232 /* Come back to HSI */ 2233 ret = stm32_clk_configure_mux(priv, CLK_MPU_HSI); 2234 if (ret != 0) { 2235 return ret; 2236 } 2237 ret = stm32_clk_configure_mux(priv, CLK_AXI_HSI); 2238 if (ret != 0) { 2239 return ret; 2240 } 2241 ret = stm32_clk_configure_mux(priv, CLK_MCU_HSI); 2242 if (ret != 0) { 2243 return ret; 2244 } 2245 if ((mmio_read_32(priv->base + RCC_MP_RSTSCLRR) & 2246 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 2247 pll3_preserve = stm32mp1_check_pll_conf(_PLL3, 2248 pll_conf[_PLL3].src, 2249 pll_conf[_PLL3].cfg, 2250 pll_conf[_PLL3].frac); 2251 pll4_preserve = stm32mp1_check_pll_conf(_PLL4, 2252 pll_conf[_PLL4].src, 2253 pll_conf[_PLL4].cfg, 2254 pll_conf[_PLL4].frac); 2255 } 2256 /* Don't initialize PLL4, when used by BOOTROM */ 2257 if ((stm32mp_get_boot_itf_selected() == 2258 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 2259 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 2260 pll4_bootrom = true; 2261 pll4_preserve = true; 2262 } 2263 2264 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2265 if (((i == _PLL3) && pll3_preserve) || 2266 ((i == _PLL4) && pll4_preserve)) { 2267 continue; 2268 } 2269 2270 ret = stm32mp1_pll_stop(i); 2271 if (ret != 0) { 2272 return ret; 2273 } 2274 } 2275 2276 /* Configure HSIDIV */ 2277 if (stm32mp1_osc[_HSI] != 0U) { 2278 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 2279 if (ret != 0) { 2280 return ret; 2281 } 2282 2283 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2284 } 2285 2286 /* Configure dividers */ 2287 ret = stm32_clk_dividers_configure(priv); 2288 if (ret != 0) { 2289 return ret; 2290 } 2291 2292 /* Configure PLLs source */ 2293 ret = stm32mp1_pll_configure_src(priv, _PLL1); 2294 if (ret != 0) { 2295 return ret; 2296 } 2297 2298 if (!pll3_preserve) { 2299 ret = stm32mp1_pll_configure_src(priv, _PLL3); 2300 if (ret != 0) { 2301 return ret; 2302 } 2303 } 2304 2305 if (!pll4_preserve) { 2306 ret = stm32mp1_pll_configure_src(priv, _PLL4); 2307 if (ret != 0) { 2308 return ret; 2309 } 2310 } 2311 2312 /* Configure and start PLLs */ 2313 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2314 if (((i == _PLL3) && pll3_preserve) || 2315 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2316 continue; 2317 } 2318 2319 if (!pll_conf[i].status) { 2320 continue; 2321 } 2322 2323 if ((i == _PLL4) && pll4_bootrom) { 2324 /* Set output divider if not done by the Bootrom */ 2325 stm32mp1_pll_config_output(i, pll_conf[i].cfg); 2326 continue; 2327 } 2328 2329 ret = stm32mp1_pll_config(i, pll_conf[i].cfg, pll_conf[i].frac); 2330 if (ret != 0) { 2331 return ret; 2332 } 2333 2334 if (pll_conf[i].csg_enabled) { 2335 stm32mp1_pll_csg(i, pll_conf[i].csg); 2336 } 2337 2338 stm32mp1_pll_start(i); 2339 } 2340 /* Wait and start PLLs output when ready */ 2341 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2342 if (!pll_conf[i].status) { 2343 continue; 2344 } 2345 2346 ret = stm32mp1_pll_output(i, pll_conf[i].cfg[PLLCFG_O]); 2347 if (ret != 0) { 2348 return ret; 2349 } 2350 } 2351 /* Wait LSE ready before to use it */ 2352 if (stm32mp1_osc[_LSE] != 0U) { 2353 stm32mp1_lse_wait(); 2354 } 2355 2356 if (pll4_bootrom) { 2357 usbreg_bootrom = mmio_read_32(priv->base + RCC_USBCKSELR); 2358 } 2359 2360 /* Configure with expected clock source */ 2361 ret = stm32_clk_source_configure(priv); 2362 if (ret != 0) { 2363 panic(); 2364 } 2365 2366 if (pll4_bootrom) { 2367 uint32_t usbreg_value, usbreg_mask; 2368 const struct stm32mp1_clk_sel *sel; 2369 2370 sel = clk_sel_ref(_USBPHY_SEL); 2371 usbreg_mask = (uint32_t)sel->msk << sel->src; 2372 sel = clk_sel_ref(_USBO_SEL); 2373 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2374 2375 usbreg_value = mmio_read_32(priv->base + RCC_USBCKSELR) & 2376 usbreg_mask; 2377 usbreg_bootrom &= usbreg_mask; 2378 if (usbreg_bootrom != usbreg_value) { 2379 VERBOSE("forbidden new USB clk path\n"); 2380 VERBOSE("vs bootrom on USB boot\n"); 2381 return -FDT_ERR_BADVALUE; 2382 } 2383 } 2384 2385 if (lse_css) { 2386 mmio_setbits_32(priv->base + RCC_BDCR, RCC_BDCR_LSECSSON); 2387 } 2388 2389 /* Switch OFF HSI if not found in device-tree */ 2390 if (stm32mp1_osc[_HSI] == 0U) { 2391 stm32mp1_hsi_set(false); 2392 } 2393 2394 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2395 2396 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2397 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, 2398 RCC_DDRITFCR_DDRCKMOD_MASK, 2399 RCC_DDRITFCR_DDRCKMOD_SSR << 2400 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2401 2402 return 0; 2403 } 2404 2405 static void stm32mp1_osc_clk_init(const char *name, 2406 enum stm32mp_osc_id index) 2407 { 2408 uint32_t frequency; 2409 2410 if (fdt_osc_read_freq(name, &frequency) == 0) { 2411 stm32mp1_osc[index] = frequency; 2412 } 2413 } 2414 2415 static void stm32mp1_osc_init(void) 2416 { 2417 enum stm32mp_osc_id i; 2418 2419 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2420 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2421 } 2422 } 2423 2424 #ifdef STM32MP_SHARED_RESOURCES 2425 /* 2426 * Get the parent ID of the target parent clock, for tagging as secure 2427 * shared clock dependencies. 2428 */ 2429 static int get_parent_id_parent(unsigned int parent_id) 2430 { 2431 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2432 enum stm32mp1_pll_id pll_id; 2433 uint32_t p_sel; 2434 uintptr_t rcc_base = stm32mp_rcc_base(); 2435 2436 switch (parent_id) { 2437 case _ACLK: 2438 case _PCLK4: 2439 case _PCLK5: 2440 s = _AXIS_SEL; 2441 break; 2442 case _PLL1_P: 2443 case _PLL1_Q: 2444 case _PLL1_R: 2445 pll_id = _PLL1; 2446 break; 2447 case _PLL2_P: 2448 case _PLL2_Q: 2449 case _PLL2_R: 2450 pll_id = _PLL2; 2451 break; 2452 case _PLL3_P: 2453 case _PLL3_Q: 2454 case _PLL3_R: 2455 pll_id = _PLL3; 2456 break; 2457 case _PLL4_P: 2458 case _PLL4_Q: 2459 case _PLL4_R: 2460 pll_id = _PLL4; 2461 break; 2462 case _PCLK1: 2463 case _PCLK2: 2464 case _HCLK2: 2465 case _HCLK6: 2466 case _CK_PER: 2467 case _CK_MPU: 2468 case _CK_MCU: 2469 case _USB_PHY_48: 2470 /* We do not expect to access these */ 2471 panic(); 2472 break; 2473 default: 2474 /* Other parents have no parent */ 2475 return -1; 2476 } 2477 2478 if (s != _UNKNOWN_SEL) { 2479 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2480 2481 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2482 sel->msk; 2483 2484 if (p_sel < sel->nb_parent) { 2485 return (int)sel->parent[p_sel]; 2486 } 2487 } else { 2488 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2489 2490 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2491 RCC_SELR_REFCLK_SRC_MASK; 2492 2493 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2494 return (int)pll->refclk[p_sel]; 2495 } 2496 } 2497 2498 VERBOSE("No parent selected for %s\n", 2499 stm32mp1_clk_parent_name[parent_id]); 2500 2501 return -1; 2502 } 2503 2504 static void secure_parent_clocks(unsigned long parent_id) 2505 { 2506 int grandparent_id; 2507 2508 switch (parent_id) { 2509 case _PLL3_P: 2510 case _PLL3_Q: 2511 case _PLL3_R: 2512 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2513 break; 2514 2515 /* These clocks are always secure when RCC is secure */ 2516 case _ACLK: 2517 case _HCLK2: 2518 case _HCLK6: 2519 case _PCLK4: 2520 case _PCLK5: 2521 case _PLL1_P: 2522 case _PLL1_Q: 2523 case _PLL1_R: 2524 case _PLL2_P: 2525 case _PLL2_Q: 2526 case _PLL2_R: 2527 case _HSI: 2528 case _HSI_KER: 2529 case _LSI: 2530 case _CSI: 2531 case _CSI_KER: 2532 case _HSE: 2533 case _HSE_KER: 2534 case _HSE_KER_DIV2: 2535 case _HSE_RTC: 2536 case _LSE: 2537 break; 2538 2539 default: 2540 VERBOSE("Cannot secure parent clock %s\n", 2541 stm32mp1_clk_parent_name[parent_id]); 2542 panic(); 2543 } 2544 2545 grandparent_id = get_parent_id_parent(parent_id); 2546 if (grandparent_id >= 0) { 2547 secure_parent_clocks(grandparent_id); 2548 } 2549 } 2550 2551 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2552 { 2553 int parent_id; 2554 2555 if (!stm32mp1_rcc_is_secure()) { 2556 return; 2557 } 2558 2559 switch (clock_id) { 2560 case PLL1: 2561 case PLL2: 2562 /* PLL1/PLL2 are always secure: nothing to do */ 2563 break; 2564 case PLL3: 2565 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2566 break; 2567 case PLL4: 2568 ERROR("PLL4 cannot be secured\n"); 2569 panic(); 2570 break; 2571 default: 2572 /* Others are expected gateable clock */ 2573 parent_id = stm32mp1_clk_get_parent(clock_id); 2574 if (parent_id < 0) { 2575 INFO("No parent found for clock %lu\n", clock_id); 2576 } else { 2577 secure_parent_clocks(parent_id); 2578 } 2579 break; 2580 } 2581 } 2582 #endif /* STM32MP_SHARED_RESOURCES */ 2583 2584 void stm32mp1_clk_mcuss_protect(bool enable) 2585 { 2586 uintptr_t rcc_base = stm32mp_rcc_base(); 2587 2588 if (enable) { 2589 mmio_setbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2590 } else { 2591 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2592 } 2593 } 2594 2595 static void sync_earlyboot_clocks_state(void) 2596 { 2597 unsigned int idx; 2598 const unsigned long secure_enable[] = { 2599 AXIDCG, 2600 BSEC, 2601 DDRC1, DDRC1LP, 2602 DDRC2, DDRC2LP, 2603 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2604 DDRPHYC, DDRPHYCLP, 2605 RTCAPB, 2606 TZC1, TZC2, 2607 TZPC, 2608 STGEN_K, 2609 }; 2610 2611 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2612 stm32mp_clk_enable(secure_enable[idx]); 2613 } 2614 } 2615 2616 static const struct clk_ops stm32mp_clk_ops = { 2617 .enable = stm32mp_clk_enable, 2618 .disable = stm32mp_clk_disable, 2619 .is_enabled = stm32mp_clk_is_enabled, 2620 .get_rate = stm32mp_clk_get_rate, 2621 .get_parent = stm32mp1_clk_get_parent, 2622 }; 2623 2624 struct stm32_pll_dt_cfg mp15_pll[_PLL_NB]; 2625 uint32_t mp15_clksrc[MUX_NB]; 2626 uint32_t mp15_clkdiv[DIV_NB]; 2627 2628 struct stm32_clk_platdata stm32mp15_clock_pdata = { 2629 .pll = mp15_pll, 2630 .npll = _PLL_NB, 2631 .clksrc = mp15_clksrc, 2632 .nclksrc = MUX_NB, 2633 .clkdiv = mp15_clkdiv, 2634 .nclkdiv = DIV_NB, 2635 }; 2636 2637 static struct stm32_clk_priv stm32mp15_clock_data = { 2638 .base = RCC_BASE, 2639 .parents = parent_mp15, 2640 .nb_parents = ARRAY_SIZE(parent_mp15), 2641 .div = dividers_mp15, 2642 .nb_div = ARRAY_SIZE(dividers_mp15), 2643 .pdata = &stm32mp15_clock_pdata, 2644 }; 2645 2646 static int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, 2647 uint32_t *tab, uint32_t *nb) 2648 { 2649 const fdt32_t *cell; 2650 int len = 0; 2651 uint32_t i; 2652 2653 cell = fdt_getprop(fdt, node, name, &len); 2654 if (cell == NULL) { 2655 *nb = 0U; 2656 return 0; 2657 } 2658 2659 for (i = 0U; i < ((uint32_t)len / sizeof(uint32_t)); i++) { 2660 tab[i] = fdt32_to_cpu(cell[i]); 2661 } 2662 2663 *nb = (uint32_t)len / sizeof(uint32_t); 2664 2665 return 0; 2666 } 2667 2668 #define RCC_PLL_NAME_SIZE 12 2669 2670 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2671 { 2672 int err; 2673 2674 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, &pll->cfg[PLLCFG_M]); 2675 if (err != 0) { 2676 return err; 2677 } 2678 2679 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLLCSG_NB, pll->csg); 2680 if (err == 0) { 2681 pll->csg_enabled = true; 2682 } else if (err == -FDT_ERR_NOTFOUND) { 2683 pll->csg_enabled = false; 2684 } else { 2685 return err; 2686 } 2687 2688 pll->status = true; 2689 2690 pll->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0); 2691 2692 pll->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX); 2693 2694 return 0; 2695 } 2696 2697 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2698 { 2699 int err; 2700 2701 err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB, 2702 &pll->cfg[PLLCFG_P]); 2703 if (err != 0) { 2704 return err; 2705 } 2706 2707 pll->cfg[PLLCFG_O] = PQR(1, 1, 1); 2708 2709 return 0; 2710 } 2711 2712 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2713 { 2714 const fdt32_t *cuint; 2715 int subnode_pll; 2716 int subnode_vco; 2717 int err; 2718 2719 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 2720 if (cuint == NULL) { 2721 /* Case of no pll is defined */ 2722 return 0; 2723 } 2724 2725 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2726 if (subnode_pll < 0) { 2727 return -FDT_ERR_NOTFOUND; 2728 } 2729 2730 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL); 2731 if (cuint == NULL) { 2732 return -FDT_ERR_NOTFOUND; 2733 } 2734 2735 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2736 if (subnode_vco < 0) { 2737 return -FDT_ERR_NOTFOUND; 2738 } 2739 2740 err = clk_stm32_load_vco_config(fdt, subnode_vco, pll); 2741 if (err != 0) { 2742 return err; 2743 } 2744 2745 err = clk_stm32_load_output_config(fdt, subnode_pll, pll); 2746 if (err != 0) { 2747 return err; 2748 } 2749 2750 return 0; 2751 } 2752 2753 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) 2754 { 2755 size_t i = 0U; 2756 2757 for (i = _PLL1; i < pdata->npll; i++) { 2758 struct stm32_pll_dt_cfg *pll = pdata->pll + i; 2759 char name[RCC_PLL_NAME_SIZE]; 2760 int subnode; 2761 int err; 2762 2763 snprintf(name, sizeof(name), "st,pll@%u", i); 2764 2765 subnode = fdt_subnode_offset(fdt, node, name); 2766 if (!fdt_check_node(subnode)) { 2767 continue; 2768 } 2769 2770 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 2771 if (err != 0) { 2772 panic(); 2773 } 2774 } 2775 2776 return 0; 2777 } 2778 2779 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) 2780 { 2781 void *fdt = NULL; 2782 int node; 2783 uint32_t err; 2784 2785 if (fdt_get_address(&fdt) == 0) { 2786 return -ENOENT; 2787 } 2788 2789 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); 2790 if (node < 0) { 2791 panic(); 2792 } 2793 2794 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 2795 if (err != 0) { 2796 return err; 2797 } 2798 2799 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv); 2800 if (err != 0) { 2801 return err; 2802 } 2803 2804 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc); 2805 if (err != 0) { 2806 return err; 2807 } 2808 2809 return 0; 2810 } 2811 2812 int stm32mp1_clk_probe(void) 2813 { 2814 uintptr_t base = RCC_BASE; 2815 int ret; 2816 2817 #if defined(IMAGE_BL32) 2818 if (!fdt_get_rcc_secure_state()) { 2819 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U); 2820 } 2821 #endif 2822 2823 stm32mp1_osc_init(); 2824 2825 ret = stm32_clk_parse_fdt(&stm32mp15_clock_pdata); 2826 if (ret != 0) { 2827 return ret; 2828 } 2829 2830 ret = clk_stm32_init(&stm32mp15_clock_data, base); 2831 if (ret != 0) { 2832 return ret; 2833 } 2834 2835 sync_earlyboot_clocks_state(); 2836 2837 clk_register(&stm32mp_clk_ops); 2838 2839 return 0; 2840 } 2841