1 /* 2 * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <limits.h> 10 #include <stdint.h> 11 #include <stdio.h> 12 13 #include <arch.h> 14 #include <arch_helpers.h> 15 #include "clk-stm32-core.h" 16 #include <common/debug.h> 17 #include <common/fdt_wrappers.h> 18 #include <drivers/clk.h> 19 #include <drivers/delay_timer.h> 20 #include <drivers/st/stm32mp13_rcc.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp_clkfunc.h> 23 #include <dt-bindings/clock/stm32mp13-clksrc.h> 24 #include <lib/mmio.h> 25 #include <lib/spinlock.h> 26 #include <lib/utils_def.h> 27 #include <libfdt.h> 28 #include <plat/common/platform.h> 29 30 #include <platform_def.h> 31 32 struct stm32_osci_dt_cfg { 33 unsigned long freq; 34 bool bypass; 35 bool digbyp; 36 bool css; 37 uint32_t drive; 38 }; 39 40 enum pll_mn { 41 PLL_CFG_M, 42 PLL_CFG_N, 43 PLL_DIV_MN_NB 44 }; 45 46 enum pll_pqr { 47 PLL_CFG_P, 48 PLL_CFG_Q, 49 PLL_CFG_R, 50 PLL_DIV_PQR_NB 51 }; 52 53 enum pll_csg { 54 PLL_CSG_MOD_PER, 55 PLL_CSG_INC_STEP, 56 PLL_CSG_SSCG_MODE, 57 PLL_CSG_NB 58 }; 59 60 struct stm32_pll_vco { 61 uint32_t status; 62 uint32_t src; 63 uint32_t div_mn[PLL_DIV_MN_NB]; 64 uint32_t frac; 65 bool csg_enabled; 66 uint32_t csg[PLL_CSG_NB]; 67 }; 68 69 struct stm32_pll_output { 70 uint32_t output[PLL_DIV_PQR_NB]; 71 }; 72 73 struct stm32_pll_dt_cfg { 74 struct stm32_pll_vco vco; 75 struct stm32_pll_output output; 76 }; 77 78 struct stm32_clk_platdata { 79 uint32_t nosci; 80 struct stm32_osci_dt_cfg *osci; 81 uint32_t npll; 82 struct stm32_pll_dt_cfg *pll; 83 uint32_t nclksrc; 84 uint32_t *clksrc; 85 uint32_t nclkdiv; 86 uint32_t *clkdiv; 87 }; 88 89 enum stm32_clock { 90 /* ROOT CLOCKS */ 91 _CK_OFF, 92 _CK_HSI, 93 _CK_HSE, 94 _CK_CSI, 95 _CK_LSI, 96 _CK_LSE, 97 _I2SCKIN, 98 _CSI_DIV122, 99 _HSE_DIV, 100 _HSE_DIV2, 101 _CK_PLL1, 102 _CK_PLL2, 103 _CK_PLL3, 104 _CK_PLL4, 105 _PLL1P, 106 _PLL1P_DIV, 107 _PLL2P, 108 _PLL2Q, 109 _PLL2R, 110 _PLL3P, 111 _PLL3Q, 112 _PLL3R, 113 _PLL4P, 114 _PLL4Q, 115 _PLL4R, 116 _PCLK1, 117 _PCLK2, 118 _PCLK3, 119 _PCLK4, 120 _PCLK5, 121 _PCLK6, 122 _CKMPU, 123 _CKAXI, 124 _CKMLAHB, 125 _CKPER, 126 _CKTIMG1, 127 _CKTIMG2, 128 _CKTIMG3, 129 _USB_PHY_48, 130 _MCO1_K, 131 _MCO2_K, 132 _TRACECK, 133 /* BUS and KERNEL CLOCKS */ 134 _DDRC1, 135 _DDRC1LP, 136 _DDRPHYC, 137 _DDRPHYCLP, 138 _DDRCAPB, 139 _DDRCAPBLP, 140 _AXIDCG, 141 _DDRPHYCAPB, 142 _DDRPHYCAPBLP, 143 _SYSCFG, 144 _DDRPERFM, 145 _IWDG2APB, 146 _USBPHY_K, 147 _USBO_K, 148 _RTCAPB, 149 _TZC, 150 _ETZPC, 151 _IWDG1APB, 152 _BSEC, 153 _STGENC, 154 _USART1_K, 155 _USART2_K, 156 _I2C3_K, 157 _I2C4_K, 158 _I2C5_K, 159 _TIM12, 160 _TIM15, 161 _RTCCK, 162 _GPIOA, 163 _GPIOB, 164 _GPIOC, 165 _GPIOD, 166 _GPIOE, 167 _GPIOF, 168 _GPIOG, 169 _GPIOH, 170 _GPIOI, 171 _PKA, 172 _SAES_K, 173 _CRYP1, 174 _HASH1, 175 _RNG1_K, 176 _BKPSRAM, 177 _SDMMC1_K, 178 _SDMMC2_K, 179 _DBGCK, 180 _USART3_K, 181 _UART4_K, 182 _UART5_K, 183 _UART7_K, 184 _UART8_K, 185 _USART6_K, 186 _MCE, 187 _FMC_K, 188 _QSPI_K, 189 #if defined(IMAGE_BL32) 190 _LTDC, 191 _DMA1, 192 _DMA2, 193 _MDMA, 194 _ETH1MAC, 195 _USBH, 196 _TIM2, 197 _TIM3, 198 _TIM4, 199 _TIM5, 200 _TIM6, 201 _TIM7, 202 _LPTIM1_K, 203 _SPI2_K, 204 _SPI3_K, 205 _SPDIF_K, 206 _TIM1, 207 _TIM8, 208 _SPI1_K, 209 _SAI1_K, 210 _SAI2_K, 211 _DFSDM, 212 _FDCAN_K, 213 _TIM13, 214 _TIM14, 215 _TIM16, 216 _TIM17, 217 _SPI4_K, 218 _SPI5_K, 219 _I2C1_K, 220 _I2C2_K, 221 _ADFSDM, 222 _LPTIM2_K, 223 _LPTIM3_K, 224 _LPTIM4_K, 225 _LPTIM5_K, 226 _VREF, 227 _DTS, 228 _PMBCTRL, 229 _HDP, 230 _STGENRO, 231 _DCMIPP_K, 232 _DMAMUX1, 233 _DMAMUX2, 234 _DMA3, 235 _ADC1_K, 236 _ADC2_K, 237 _TSC, 238 _AXIMC, 239 _ETH1CK, 240 _ETH1TX, 241 _ETH1RX, 242 _CRC1, 243 _ETH2CK, 244 _ETH2TX, 245 _ETH2RX, 246 _ETH2MAC, 247 #endif 248 CK_LAST 249 }; 250 251 /* PARENT CONFIG */ 252 static const uint16_t RTC_src[] = { 253 _CK_OFF, _CK_LSE, _CK_LSI, _CK_HSE 254 }; 255 256 static const uint16_t MCO1_src[] = { 257 _CK_HSI, _CK_HSE, _CK_CSI, _CK_LSI, _CK_LSE 258 }; 259 260 static const uint16_t MCO2_src[] = { 261 _CKMPU, _CKAXI, _CKMLAHB, _PLL4P, _CK_HSE, _CK_HSI 262 }; 263 264 static const uint16_t PLL12_src[] = { 265 _CK_HSI, _CK_HSE 266 }; 267 268 static const uint16_t PLL3_src[] = { 269 _CK_HSI, _CK_HSE, _CK_CSI 270 }; 271 272 static const uint16_t PLL4_src[] = { 273 _CK_HSI, _CK_HSE, _CK_CSI, _I2SCKIN 274 }; 275 276 static const uint16_t MPU_src[] = { 277 _CK_HSI, _CK_HSE, _PLL1P, _PLL1P_DIV 278 }; 279 280 static const uint16_t AXI_src[] = { 281 _CK_HSI, _CK_HSE, _PLL2P 282 }; 283 284 static const uint16_t MLAHBS_src[] = { 285 _CK_HSI, _CK_HSE, _CK_CSI, _PLL3P 286 }; 287 288 static const uint16_t CKPER_src[] = { 289 _CK_HSI, _CK_CSI, _CK_HSE, _CK_OFF 290 }; 291 292 static const uint16_t I2C12_src[] = { 293 _PCLK1, _PLL4R, _CK_HSI, _CK_CSI 294 }; 295 296 static const uint16_t I2C3_src[] = { 297 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI 298 }; 299 300 static const uint16_t I2C4_src[] = { 301 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI 302 }; 303 304 static const uint16_t I2C5_src[] = { 305 _PCLK6, _PLL4R, _CK_HSI, _CK_CSI 306 }; 307 308 static const uint16_t SPI1_src[] = { 309 _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R 310 }; 311 312 static const uint16_t SPI23_src[] = { 313 _PLL4P, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R 314 }; 315 316 static const uint16_t SPI4_src[] = { 317 _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE, _I2SCKIN 318 }; 319 320 static const uint16_t SPI5_src[] = { 321 _PCLK6, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE 322 }; 323 324 static const uint16_t UART1_src[] = { 325 _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE 326 }; 327 328 static const uint16_t UART2_src[] = { 329 _PCLK6, _PLL3Q, _CK_HSI, _CK_CSI, _PLL4Q, _CK_HSE 330 }; 331 332 static const uint16_t UART35_src[] = { 333 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE 334 }; 335 336 static const uint16_t UART4_src[] = { 337 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE 338 }; 339 340 static const uint16_t UART6_src[] = { 341 _PCLK2, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE 342 }; 343 344 static const uint16_t UART78_src[] = { 345 _PCLK1, _PLL4Q, _CK_HSI, _CK_CSI, _CK_HSE 346 }; 347 348 static const uint16_t LPTIM1_src[] = { 349 _PCLK1, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER 350 }; 351 352 static const uint16_t LPTIM2_src[] = { 353 _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI 354 }; 355 356 static const uint16_t LPTIM3_src[] = { 357 _PCLK3, _PLL4Q, _CKPER, _CK_LSE, _CK_LSI 358 }; 359 360 static const uint16_t LPTIM45_src[] = { 361 _PCLK3, _PLL4P, _PLL3Q, _CK_LSE, _CK_LSI, _CKPER 362 }; 363 364 static const uint16_t SAI1_src[] = { 365 _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _PLL3R 366 }; 367 368 static const uint16_t SAI2_src[] = { 369 _PLL4Q, _PLL3Q, _I2SCKIN, _CKPER, _NO_ID, _PLL3R 370 }; 371 372 static const uint16_t FDCAN_src[] = { 373 _CK_HSE, _PLL3Q, _PLL4Q, _PLL4R 374 }; 375 376 static const uint16_t SPDIF_src[] = { 377 _PLL4P, _PLL3Q, _CK_HSI 378 }; 379 380 static const uint16_t ADC1_src[] = { 381 _PLL4R, _CKPER, _PLL3Q 382 }; 383 384 static const uint16_t ADC2_src[] = { 385 _PLL4R, _CKPER, _PLL3Q 386 }; 387 388 static const uint16_t SDMMC1_src[] = { 389 _CKAXI, _PLL3R, _PLL4P, _CK_HSI 390 }; 391 392 static const uint16_t SDMMC2_src[] = { 393 _CKAXI, _PLL3R, _PLL4P, _CK_HSI 394 }; 395 396 static const uint16_t ETH1_src[] = { 397 _PLL4P, _PLL3Q 398 }; 399 400 static const uint16_t ETH2_src[] = { 401 _PLL4P, _PLL3Q 402 }; 403 404 static const uint16_t USBPHY_src[] = { 405 _CK_HSE, _PLL4R, _HSE_DIV2 406 }; 407 408 static const uint16_t USBO_src[] = { 409 _PLL4R, _USB_PHY_48 410 }; 411 412 static const uint16_t QSPI_src[] = { 413 _CKAXI, _PLL3R, _PLL4P, _CKPER 414 }; 415 416 static const uint16_t FMC_src[] = { 417 _CKAXI, _PLL3R, _PLL4P, _CKPER 418 }; 419 420 /* Position 2 of RNG1 mux is reserved */ 421 static const uint16_t RNG1_src[] = { 422 _CK_CSI, _PLL4R, _CK_OFF, _CK_LSI 423 }; 424 425 static const uint16_t STGEN_src[] = { 426 _CK_HSI, _CK_HSE 427 }; 428 429 static const uint16_t DCMIPP_src[] = { 430 _CKAXI, _PLL2Q, _PLL4P, _CKPER 431 }; 432 433 static const uint16_t SAES_src[] = { 434 _CKAXI, _CKPER, _PLL4R, _CK_LSI 435 }; 436 437 #define MUX_CFG(id, src, _offset, _shift, _witdh)[id] = {\ 438 .id_parents = src,\ 439 .num_parents = ARRAY_SIZE(src),\ 440 .mux = &(struct mux_cfg) {\ 441 .offset = (_offset),\ 442 .shift = (_shift),\ 443 .width = (_witdh),\ 444 .bitrdy = MUX_NO_BIT_RDY,\ 445 },\ 446 } 447 448 #define MUX_RDY_CFG(id, src, _offset, _shift, _witdh)[id] = {\ 449 .id_parents = src,\ 450 .num_parents = ARRAY_SIZE(src),\ 451 .mux = &(struct mux_cfg) {\ 452 .offset = (_offset),\ 453 .shift = (_shift),\ 454 .width = (_witdh),\ 455 .bitrdy = 31,\ 456 },\ 457 } 458 459 static const struct parent_cfg parent_mp13[MUX_MAX] = { 460 MUX_CFG(MUX_ADC1, ADC1_src, RCC_ADC12CKSELR, 0, 2), 461 MUX_CFG(MUX_ADC2, ADC2_src, RCC_ADC12CKSELR, 2, 2), 462 MUX_RDY_CFG(MUX_AXI, AXI_src, RCC_ASSCKSELR, 0, 3), 463 MUX_CFG(MUX_CKPER, CKPER_src, RCC_CPERCKSELR, 0, 2), 464 MUX_CFG(MUX_DCMIPP, DCMIPP_src, RCC_DCMIPPCKSELR, 0, 2), 465 MUX_CFG(MUX_ETH1, ETH1_src, RCC_ETH12CKSELR, 0, 2), 466 MUX_CFG(MUX_ETH2, ETH2_src, RCC_ETH12CKSELR, 8, 2), 467 MUX_CFG(MUX_FDCAN, FDCAN_src, RCC_FDCANCKSELR, 0, 2), 468 MUX_CFG(MUX_FMC, FMC_src, RCC_FMCCKSELR, 0, 2), 469 MUX_CFG(MUX_I2C12, I2C12_src, RCC_I2C12CKSELR, 0, 3), 470 MUX_CFG(MUX_I2C3, I2C3_src, RCC_I2C345CKSELR, 0, 3), 471 MUX_CFG(MUX_I2C4, I2C4_src, RCC_I2C345CKSELR, 3, 3), 472 MUX_CFG(MUX_I2C5, I2C5_src, RCC_I2C345CKSELR, 6, 3), 473 MUX_CFG(MUX_LPTIM1, LPTIM1_src, RCC_LPTIM1CKSELR, 0, 3), 474 MUX_CFG(MUX_LPTIM2, LPTIM2_src, RCC_LPTIM23CKSELR, 0, 3), 475 MUX_CFG(MUX_LPTIM3, LPTIM3_src, RCC_LPTIM23CKSELR, 3, 3), 476 MUX_CFG(MUX_LPTIM45, LPTIM45_src, RCC_LPTIM45CKSELR, 0, 3), 477 MUX_CFG(MUX_MCO1, MCO1_src, RCC_MCO1CFGR, 0, 3), 478 MUX_CFG(MUX_MCO2, MCO2_src, RCC_MCO2CFGR, 0, 3), 479 MUX_RDY_CFG(MUX_MLAHB, MLAHBS_src, RCC_MSSCKSELR, 0, 2), 480 MUX_RDY_CFG(MUX_MPU, MPU_src, RCC_MPCKSELR, 0, 2), 481 MUX_RDY_CFG(MUX_PLL12, PLL12_src, RCC_RCK12SELR, 0, 2), 482 MUX_RDY_CFG(MUX_PLL3, PLL3_src, RCC_RCK3SELR, 0, 2), 483 MUX_RDY_CFG(MUX_PLL4, PLL4_src, RCC_RCK4SELR, 0, 2), 484 MUX_CFG(MUX_QSPI, QSPI_src, RCC_QSPICKSELR, 0, 2), 485 MUX_CFG(MUX_RNG1, RNG1_src, RCC_RNG1CKSELR, 0, 2), 486 MUX_CFG(MUX_RTC, RTC_src, RCC_BDCR, 16, 2), 487 MUX_CFG(MUX_SAES, SAES_src, RCC_SAESCKSELR, 0, 2), 488 MUX_CFG(MUX_SAI1, SAI1_src, RCC_SAI1CKSELR, 0, 3), 489 MUX_CFG(MUX_SAI2, SAI2_src, RCC_SAI2CKSELR, 0, 3), 490 MUX_CFG(MUX_SDMMC1, SDMMC1_src, RCC_SDMMC12CKSELR, 0, 3), 491 MUX_CFG(MUX_SDMMC2, SDMMC2_src, RCC_SDMMC12CKSELR, 3, 3), 492 MUX_CFG(MUX_SPDIF, SPDIF_src, RCC_SPDIFCKSELR, 0, 2), 493 MUX_CFG(MUX_SPI1, SPI1_src, RCC_SPI2S1CKSELR, 0, 3), 494 MUX_CFG(MUX_SPI23, SPI23_src, RCC_SPI2S23CKSELR, 0, 3), 495 MUX_CFG(MUX_SPI4, SPI4_src, RCC_SPI45CKSELR, 0, 3), 496 MUX_CFG(MUX_SPI5, SPI5_src, RCC_SPI45CKSELR, 3, 3), 497 MUX_CFG(MUX_STGEN, STGEN_src, RCC_STGENCKSELR, 0, 2), 498 MUX_CFG(MUX_UART1, UART1_src, RCC_UART12CKSELR, 0, 3), 499 MUX_CFG(MUX_UART2, UART2_src, RCC_UART12CKSELR, 3, 3), 500 MUX_CFG(MUX_UART35, UART35_src, RCC_UART35CKSELR, 0, 3), 501 MUX_CFG(MUX_UART4, UART4_src, RCC_UART4CKSELR, 0, 3), 502 MUX_CFG(MUX_UART6, UART6_src, RCC_UART6CKSELR, 0, 3), 503 MUX_CFG(MUX_UART78, UART78_src, RCC_UART78CKSELR, 0, 3), 504 MUX_CFG(MUX_USBO, USBO_src, RCC_USBCKSELR, 4, 1), 505 MUX_CFG(MUX_USBPHY, USBPHY_src, RCC_USBCKSELR, 0, 2), 506 }; 507 508 /* 509 * GATE CONFIG 510 */ 511 512 enum enum_gate_cfg { 513 GATE_ZERO, /* reserved for no gate */ 514 GATE_LSE, 515 GATE_RTCCK, 516 GATE_LSI, 517 GATE_HSI, 518 GATE_CSI, 519 GATE_HSE, 520 GATE_LSI_RDY, 521 GATE_CSI_RDY, 522 GATE_LSE_RDY, 523 GATE_HSE_RDY, 524 GATE_HSI_RDY, 525 GATE_MCO1, 526 GATE_MCO2, 527 GATE_DBGCK, 528 GATE_TRACECK, 529 GATE_PLL1, 530 GATE_PLL1_DIVP, 531 GATE_PLL1_DIVQ, 532 GATE_PLL1_DIVR, 533 GATE_PLL2, 534 GATE_PLL2_DIVP, 535 GATE_PLL2_DIVQ, 536 GATE_PLL2_DIVR, 537 GATE_PLL3, 538 GATE_PLL3_DIVP, 539 GATE_PLL3_DIVQ, 540 GATE_PLL3_DIVR, 541 GATE_PLL4, 542 GATE_PLL4_DIVP, 543 GATE_PLL4_DIVQ, 544 GATE_PLL4_DIVR, 545 GATE_DDRC1, 546 GATE_DDRC1LP, 547 GATE_DDRPHYC, 548 GATE_DDRPHYCLP, 549 GATE_DDRCAPB, 550 GATE_DDRCAPBLP, 551 GATE_AXIDCG, 552 GATE_DDRPHYCAPB, 553 GATE_DDRPHYCAPBLP, 554 GATE_TIM2, 555 GATE_TIM3, 556 GATE_TIM4, 557 GATE_TIM5, 558 GATE_TIM6, 559 GATE_TIM7, 560 GATE_LPTIM1, 561 GATE_SPI2, 562 GATE_SPI3, 563 GATE_USART3, 564 GATE_UART4, 565 GATE_UART5, 566 GATE_UART7, 567 GATE_UART8, 568 GATE_I2C1, 569 GATE_I2C2, 570 GATE_SPDIF, 571 GATE_TIM1, 572 GATE_TIM8, 573 GATE_SPI1, 574 GATE_USART6, 575 GATE_SAI1, 576 GATE_SAI2, 577 GATE_DFSDM, 578 GATE_ADFSDM, 579 GATE_FDCAN, 580 GATE_LPTIM2, 581 GATE_LPTIM3, 582 GATE_LPTIM4, 583 GATE_LPTIM5, 584 GATE_VREF, 585 GATE_DTS, 586 GATE_PMBCTRL, 587 GATE_HDP, 588 GATE_SYSCFG, 589 GATE_DCMIPP, 590 GATE_DDRPERFM, 591 GATE_IWDG2APB, 592 GATE_USBPHY, 593 GATE_STGENRO, 594 GATE_LTDC, 595 GATE_RTCAPB, 596 GATE_TZC, 597 GATE_ETZPC, 598 GATE_IWDG1APB, 599 GATE_BSEC, 600 GATE_STGENC, 601 GATE_USART1, 602 GATE_USART2, 603 GATE_SPI4, 604 GATE_SPI5, 605 GATE_I2C3, 606 GATE_I2C4, 607 GATE_I2C5, 608 GATE_TIM12, 609 GATE_TIM13, 610 GATE_TIM14, 611 GATE_TIM15, 612 GATE_TIM16, 613 GATE_TIM17, 614 GATE_DMA1, 615 GATE_DMA2, 616 GATE_DMAMUX1, 617 GATE_DMA3, 618 GATE_DMAMUX2, 619 GATE_ADC1, 620 GATE_ADC2, 621 GATE_USBO, 622 GATE_TSC, 623 GATE_GPIOA, 624 GATE_GPIOB, 625 GATE_GPIOC, 626 GATE_GPIOD, 627 GATE_GPIOE, 628 GATE_GPIOF, 629 GATE_GPIOG, 630 GATE_GPIOH, 631 GATE_GPIOI, 632 GATE_PKA, 633 GATE_SAES, 634 GATE_CRYP1, 635 GATE_HASH1, 636 GATE_RNG1, 637 GATE_BKPSRAM, 638 GATE_AXIMC, 639 GATE_MCE, 640 GATE_ETH1CK, 641 GATE_ETH1TX, 642 GATE_ETH1RX, 643 GATE_ETH1MAC, 644 GATE_FMC, 645 GATE_QSPI, 646 GATE_SDMMC1, 647 GATE_SDMMC2, 648 GATE_CRC1, 649 GATE_USBH, 650 GATE_ETH2CK, 651 GATE_ETH2TX, 652 GATE_ETH2RX, 653 GATE_ETH2MAC, 654 GATE_MDMA, 655 656 LAST_GATE 657 }; 658 659 #define GATE_CFG(id, _offset, _bit_idx, _offset_clr)[id] = {\ 660 .offset = (_offset),\ 661 .bit_idx = (_bit_idx),\ 662 .set_clr = (_offset_clr),\ 663 } 664 665 static const struct gate_cfg gates_mp13[LAST_GATE] = { 666 GATE_CFG(GATE_LSE, RCC_BDCR, 0, 0), 667 GATE_CFG(GATE_RTCCK, RCC_BDCR, 20, 0), 668 GATE_CFG(GATE_LSI, RCC_RDLSICR, 0, 0), 669 GATE_CFG(GATE_HSI, RCC_OCENSETR, 0, 1), 670 GATE_CFG(GATE_CSI, RCC_OCENSETR, 4, 1), 671 GATE_CFG(GATE_HSE, RCC_OCENSETR, 8, 1), 672 GATE_CFG(GATE_LSI_RDY, RCC_RDLSICR, 1, 0), 673 GATE_CFG(GATE_CSI_RDY, RCC_OCRDYR, 4, 0), 674 GATE_CFG(GATE_LSE_RDY, RCC_BDCR, 2, 0), 675 GATE_CFG(GATE_HSE_RDY, RCC_OCRDYR, 8, 0), 676 GATE_CFG(GATE_HSI_RDY, RCC_OCRDYR, 0, 0), 677 GATE_CFG(GATE_MCO1, RCC_MCO1CFGR, 12, 0), 678 GATE_CFG(GATE_MCO2, RCC_MCO2CFGR, 12, 0), 679 GATE_CFG(GATE_DBGCK, RCC_DBGCFGR, 8, 0), 680 GATE_CFG(GATE_TRACECK, RCC_DBGCFGR, 9, 0), 681 GATE_CFG(GATE_PLL1, RCC_PLL1CR, 0, 0), 682 GATE_CFG(GATE_PLL1_DIVP, RCC_PLL1CR, 4, 0), 683 GATE_CFG(GATE_PLL1_DIVQ, RCC_PLL1CR, 5, 0), 684 GATE_CFG(GATE_PLL1_DIVR, RCC_PLL1CR, 6, 0), 685 GATE_CFG(GATE_PLL2, RCC_PLL2CR, 0, 0), 686 GATE_CFG(GATE_PLL2_DIVP, RCC_PLL2CR, 4, 0), 687 GATE_CFG(GATE_PLL2_DIVQ, RCC_PLL2CR, 5, 0), 688 GATE_CFG(GATE_PLL2_DIVR, RCC_PLL2CR, 6, 0), 689 GATE_CFG(GATE_PLL3, RCC_PLL3CR, 0, 0), 690 GATE_CFG(GATE_PLL3_DIVP, RCC_PLL3CR, 4, 0), 691 GATE_CFG(GATE_PLL3_DIVQ, RCC_PLL3CR, 5, 0), 692 GATE_CFG(GATE_PLL3_DIVR, RCC_PLL3CR, 6, 0), 693 GATE_CFG(GATE_PLL4, RCC_PLL4CR, 0, 0), 694 GATE_CFG(GATE_PLL4_DIVP, RCC_PLL4CR, 4, 0), 695 GATE_CFG(GATE_PLL4_DIVQ, RCC_PLL4CR, 5, 0), 696 GATE_CFG(GATE_PLL4_DIVR, RCC_PLL4CR, 6, 0), 697 GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0), 698 GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0), 699 GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0), 700 GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0), 701 GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0), 702 GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0), 703 GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0), 704 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0), 705 GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0), 706 GATE_CFG(GATE_TIM2, RCC_MP_APB1ENSETR, 0, 1), 707 GATE_CFG(GATE_TIM3, RCC_MP_APB1ENSETR, 1, 1), 708 GATE_CFG(GATE_TIM4, RCC_MP_APB1ENSETR, 2, 1), 709 GATE_CFG(GATE_TIM5, RCC_MP_APB1ENSETR, 3, 1), 710 GATE_CFG(GATE_TIM6, RCC_MP_APB1ENSETR, 4, 1), 711 GATE_CFG(GATE_TIM7, RCC_MP_APB1ENSETR, 5, 1), 712 GATE_CFG(GATE_LPTIM1, RCC_MP_APB1ENSETR, 9, 1), 713 GATE_CFG(GATE_SPI2, RCC_MP_APB1ENSETR, 11, 1), 714 GATE_CFG(GATE_SPI3, RCC_MP_APB1ENSETR, 12, 1), 715 GATE_CFG(GATE_USART3, RCC_MP_APB1ENSETR, 15, 1), 716 GATE_CFG(GATE_UART4, RCC_MP_APB1ENSETR, 16, 1), 717 GATE_CFG(GATE_UART5, RCC_MP_APB1ENSETR, 17, 1), 718 GATE_CFG(GATE_UART7, RCC_MP_APB1ENSETR, 18, 1), 719 GATE_CFG(GATE_UART8, RCC_MP_APB1ENSETR, 19, 1), 720 GATE_CFG(GATE_I2C1, RCC_MP_APB1ENSETR, 21, 1), 721 GATE_CFG(GATE_I2C2, RCC_MP_APB1ENSETR, 22, 1), 722 GATE_CFG(GATE_SPDIF, RCC_MP_APB1ENSETR, 26, 1), 723 GATE_CFG(GATE_TIM1, RCC_MP_APB2ENSETR, 0, 1), 724 GATE_CFG(GATE_TIM8, RCC_MP_APB2ENSETR, 1, 1), 725 GATE_CFG(GATE_SPI1, RCC_MP_APB2ENSETR, 8, 1), 726 GATE_CFG(GATE_USART6, RCC_MP_APB2ENSETR, 13, 1), 727 GATE_CFG(GATE_SAI1, RCC_MP_APB2ENSETR, 16, 1), 728 GATE_CFG(GATE_SAI2, RCC_MP_APB2ENSETR, 17, 1), 729 GATE_CFG(GATE_DFSDM, RCC_MP_APB2ENSETR, 20, 1), 730 GATE_CFG(GATE_ADFSDM, RCC_MP_APB2ENSETR, 21, 1), 731 GATE_CFG(GATE_FDCAN, RCC_MP_APB2ENSETR, 24, 1), 732 GATE_CFG(GATE_LPTIM2, RCC_MP_APB3ENSETR, 0, 1), 733 GATE_CFG(GATE_LPTIM3, RCC_MP_APB3ENSETR, 1, 1), 734 GATE_CFG(GATE_LPTIM4, RCC_MP_APB3ENSETR, 2, 1), 735 GATE_CFG(GATE_LPTIM5, RCC_MP_APB3ENSETR, 3, 1), 736 GATE_CFG(GATE_VREF, RCC_MP_APB3ENSETR, 13, 1), 737 GATE_CFG(GATE_DTS, RCC_MP_APB3ENSETR, 16, 1), 738 GATE_CFG(GATE_PMBCTRL, RCC_MP_APB3ENSETR, 17, 1), 739 GATE_CFG(GATE_HDP, RCC_MP_APB3ENSETR, 20, 1), 740 GATE_CFG(GATE_SYSCFG, RCC_MP_S_APB3ENSETR, 0, 1), 741 GATE_CFG(GATE_DCMIPP, RCC_MP_APB4ENSETR, 1, 1), 742 GATE_CFG(GATE_DDRPERFM, RCC_MP_APB4ENSETR, 8, 1), 743 GATE_CFG(GATE_IWDG2APB, RCC_MP_APB4ENSETR, 15, 1), 744 GATE_CFG(GATE_USBPHY, RCC_MP_APB4ENSETR, 16, 1), 745 GATE_CFG(GATE_STGENRO, RCC_MP_APB4ENSETR, 20, 1), 746 GATE_CFG(GATE_LTDC, RCC_MP_S_APB4ENSETR, 0, 1), 747 GATE_CFG(GATE_RTCAPB, RCC_MP_APB5ENSETR, 8, 1), 748 GATE_CFG(GATE_TZC, RCC_MP_APB5ENSETR, 11, 1), 749 GATE_CFG(GATE_ETZPC, RCC_MP_APB5ENSETR, 13, 1), 750 GATE_CFG(GATE_IWDG1APB, RCC_MP_APB5ENSETR, 15, 1), 751 GATE_CFG(GATE_BSEC, RCC_MP_APB5ENSETR, 16, 1), 752 GATE_CFG(GATE_STGENC, RCC_MP_APB5ENSETR, 20, 1), 753 GATE_CFG(GATE_USART1, RCC_MP_APB6ENSETR, 0, 1), 754 GATE_CFG(GATE_USART2, RCC_MP_APB6ENSETR, 1, 1), 755 GATE_CFG(GATE_SPI4, RCC_MP_APB6ENSETR, 2, 1), 756 GATE_CFG(GATE_SPI5, RCC_MP_APB6ENSETR, 3, 1), 757 GATE_CFG(GATE_I2C3, RCC_MP_APB6ENSETR, 4, 1), 758 GATE_CFG(GATE_I2C4, RCC_MP_APB6ENSETR, 5, 1), 759 GATE_CFG(GATE_I2C5, RCC_MP_APB6ENSETR, 6, 1), 760 GATE_CFG(GATE_TIM12, RCC_MP_APB6ENSETR, 7, 1), 761 GATE_CFG(GATE_TIM13, RCC_MP_APB6ENSETR, 8, 1), 762 GATE_CFG(GATE_TIM14, RCC_MP_APB6ENSETR, 9, 1), 763 GATE_CFG(GATE_TIM15, RCC_MP_APB6ENSETR, 10, 1), 764 GATE_CFG(GATE_TIM16, RCC_MP_APB6ENSETR, 11, 1), 765 GATE_CFG(GATE_TIM17, RCC_MP_APB6ENSETR, 12, 1), 766 GATE_CFG(GATE_DMA1, RCC_MP_AHB2ENSETR, 0, 1), 767 GATE_CFG(GATE_DMA2, RCC_MP_AHB2ENSETR, 1, 1), 768 GATE_CFG(GATE_DMAMUX1, RCC_MP_AHB2ENSETR, 2, 1), 769 GATE_CFG(GATE_DMA3, RCC_MP_AHB2ENSETR, 3, 1), 770 GATE_CFG(GATE_DMAMUX2, RCC_MP_AHB2ENSETR, 4, 1), 771 GATE_CFG(GATE_ADC1, RCC_MP_AHB2ENSETR, 5, 1), 772 GATE_CFG(GATE_ADC2, RCC_MP_AHB2ENSETR, 6, 1), 773 GATE_CFG(GATE_USBO, RCC_MP_AHB2ENSETR, 8, 1), 774 GATE_CFG(GATE_TSC, RCC_MP_AHB4ENSETR, 15, 1), 775 776 GATE_CFG(GATE_GPIOA, RCC_MP_S_AHB4ENSETR, 0, 1), 777 GATE_CFG(GATE_GPIOB, RCC_MP_S_AHB4ENSETR, 1, 1), 778 GATE_CFG(GATE_GPIOC, RCC_MP_S_AHB4ENSETR, 2, 1), 779 GATE_CFG(GATE_GPIOD, RCC_MP_S_AHB4ENSETR, 3, 1), 780 GATE_CFG(GATE_GPIOE, RCC_MP_S_AHB4ENSETR, 4, 1), 781 GATE_CFG(GATE_GPIOF, RCC_MP_S_AHB4ENSETR, 5, 1), 782 GATE_CFG(GATE_GPIOG, RCC_MP_S_AHB4ENSETR, 6, 1), 783 GATE_CFG(GATE_GPIOH, RCC_MP_S_AHB4ENSETR, 7, 1), 784 GATE_CFG(GATE_GPIOI, RCC_MP_S_AHB4ENSETR, 8, 1), 785 786 GATE_CFG(GATE_PKA, RCC_MP_AHB5ENSETR, 2, 1), 787 GATE_CFG(GATE_SAES, RCC_MP_AHB5ENSETR, 3, 1), 788 GATE_CFG(GATE_CRYP1, RCC_MP_AHB5ENSETR, 4, 1), 789 GATE_CFG(GATE_HASH1, RCC_MP_AHB5ENSETR, 5, 1), 790 GATE_CFG(GATE_RNG1, RCC_MP_AHB5ENSETR, 6, 1), 791 GATE_CFG(GATE_BKPSRAM, RCC_MP_AHB5ENSETR, 8, 1), 792 GATE_CFG(GATE_AXIMC, RCC_MP_AHB5ENSETR, 16, 1), 793 GATE_CFG(GATE_MCE, RCC_MP_AHB6ENSETR, 1, 1), 794 GATE_CFG(GATE_ETH1CK, RCC_MP_AHB6ENSETR, 7, 1), 795 GATE_CFG(GATE_ETH1TX, RCC_MP_AHB6ENSETR, 8, 1), 796 GATE_CFG(GATE_ETH1RX, RCC_MP_AHB6ENSETR, 9, 1), 797 GATE_CFG(GATE_ETH1MAC, RCC_MP_AHB6ENSETR, 10, 1), 798 GATE_CFG(GATE_FMC, RCC_MP_AHB6ENSETR, 12, 1), 799 GATE_CFG(GATE_QSPI, RCC_MP_AHB6ENSETR, 14, 1), 800 GATE_CFG(GATE_SDMMC1, RCC_MP_AHB6ENSETR, 16, 1), 801 GATE_CFG(GATE_SDMMC2, RCC_MP_AHB6ENSETR, 17, 1), 802 GATE_CFG(GATE_CRC1, RCC_MP_AHB6ENSETR, 20, 1), 803 GATE_CFG(GATE_USBH, RCC_MP_AHB6ENSETR, 24, 1), 804 GATE_CFG(GATE_ETH2CK, RCC_MP_AHB6ENSETR, 27, 1), 805 GATE_CFG(GATE_ETH2TX, RCC_MP_AHB6ENSETR, 28, 1), 806 GATE_CFG(GATE_ETH2RX, RCC_MP_AHB6ENSETR, 29, 1), 807 GATE_CFG(GATE_ETH2MAC, RCC_MP_AHB6ENSETR, 30, 1), 808 GATE_CFG(GATE_MDMA, RCC_MP_S_AHB6ENSETR, 0, 1), 809 }; 810 811 /* 812 * DIV CONFIG 813 */ 814 815 static const struct clk_div_table axi_div_table[] = { 816 { 0, 1 }, { 1, 2 }, { 2, 3 }, { 3, 4 }, 817 { 4, 4 }, { 5, 4 }, { 6, 4 }, { 7, 4 }, 818 { 0 }, 819 }; 820 821 static const struct clk_div_table mlahb_div_table[] = { 822 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 823 { 4, 16 }, { 5, 32 }, { 6, 64 }, { 7, 128 }, 824 { 8, 256 }, { 9, 512 }, { 10, 512}, { 11, 512 }, 825 { 12, 512 }, { 13, 512 }, { 14, 512}, { 15, 512 }, 826 { 0 }, 827 }; 828 829 static const struct clk_div_table apb_div_table[] = { 830 { 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 }, 831 { 4, 16 }, { 5, 16 }, { 6, 16 }, { 7, 16 }, 832 { 0 }, 833 }; 834 835 #define DIV_CFG(id, _offset, _shift, _width, _flags, _table, _bitrdy)[id] = {\ 836 .offset = _offset,\ 837 .shift = _shift,\ 838 .width = _width,\ 839 .flags = _flags,\ 840 .table = _table,\ 841 .bitrdy = _bitrdy,\ 842 } 843 844 static const struct div_cfg dividers_mp13[DIV_MAX] = { 845 DIV_CFG(DIV_PLL1DIVP, RCC_PLL1CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), 846 DIV_CFG(DIV_PLL2DIVP, RCC_PLL2CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), 847 DIV_CFG(DIV_PLL2DIVQ, RCC_PLL2CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), 848 DIV_CFG(DIV_PLL2DIVR, RCC_PLL2CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), 849 DIV_CFG(DIV_PLL3DIVP, RCC_PLL3CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), 850 DIV_CFG(DIV_PLL3DIVQ, RCC_PLL3CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), 851 DIV_CFG(DIV_PLL3DIVR, RCC_PLL3CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), 852 DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY), 853 DIV_CFG(DIV_PLL4DIVQ, RCC_PLL4CFGR2, 8, 7, 0, NULL, DIV_NO_BIT_RDY), 854 DIV_CFG(DIV_PLL4DIVR, RCC_PLL4CFGR2, 16, 7, 0, NULL, DIV_NO_BIT_RDY), 855 DIV_CFG(DIV_MPU, RCC_MPCKDIVR, 0, 4, 0, NULL, DIV_NO_BIT_RDY), 856 DIV_CFG(DIV_AXI, RCC_AXIDIVR, 0, 3, 0, axi_div_table, 31), 857 DIV_CFG(DIV_MLAHB, RCC_MLAHBDIVR, 0, 4, 0, mlahb_div_table, 31), 858 DIV_CFG(DIV_APB1, RCC_APB1DIVR, 0, 3, 0, apb_div_table, 31), 859 DIV_CFG(DIV_APB2, RCC_APB2DIVR, 0, 3, 0, apb_div_table, 31), 860 DIV_CFG(DIV_APB3, RCC_APB3DIVR, 0, 3, 0, apb_div_table, 31), 861 DIV_CFG(DIV_APB4, RCC_APB4DIVR, 0, 3, 0, apb_div_table, 31), 862 DIV_CFG(DIV_APB5, RCC_APB5DIVR, 0, 3, 0, apb_div_table, 31), 863 DIV_CFG(DIV_APB6, RCC_APB6DIVR, 0, 3, 0, apb_div_table, 31), 864 DIV_CFG(DIV_RTC, RCC_RTCDIVR, 0, 6, 0, NULL, DIV_NO_BIT_RDY), 865 DIV_CFG(DIV_MCO1, RCC_MCO1CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), 866 DIV_CFG(DIV_MCO2, RCC_MCO2CFGR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), 867 868 DIV_CFG(DIV_HSI, RCC_HSICFGR, 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY), 869 DIV_CFG(DIV_TRACE, RCC_DBGCFGR, 0, 3, CLK_DIVIDER_POWER_OF_TWO, NULL, DIV_NO_BIT_RDY), 870 871 DIV_CFG(DIV_ETH1PTP, RCC_ETH12CKSELR, 4, 4, 0, NULL, DIV_NO_BIT_RDY), 872 DIV_CFG(DIV_ETH2PTP, RCC_ETH12CKSELR, 12, 4, 0, NULL, DIV_NO_BIT_RDY), 873 }; 874 875 #define MAX_HSI_HZ 64000000 876 #define USB_PHY_48_MHZ 48000000 877 878 #define TIMEOUT_US_200MS U(200000) 879 #define TIMEOUT_US_1S U(1000000) 880 881 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 882 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 883 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 884 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 885 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 886 887 enum stm32_osc { 888 OSC_HSI, 889 OSC_HSE, 890 OSC_CSI, 891 OSC_LSI, 892 OSC_LSE, 893 OSC_I2SCKIN, 894 NB_OSCILLATOR 895 }; 896 897 enum stm32mp1_pll_id { 898 _PLL1, 899 _PLL2, 900 _PLL3, 901 _PLL4, 902 _PLL_NB 903 }; 904 905 enum stm32mp1_plltype { 906 PLL_800, 907 PLL_1600, 908 PLL_2000, 909 PLL_TYPE_NB 910 }; 911 912 #define RCC_OFFSET_PLLXCR 0 913 #define RCC_OFFSET_PLLXCFGR1 4 914 #define RCC_OFFSET_PLLXCFGR2 8 915 #define RCC_OFFSET_PLLXFRACR 12 916 #define RCC_OFFSET_PLLXCSGR 16 917 918 struct stm32_clk_pll { 919 enum stm32mp1_plltype plltype; 920 uint16_t clk_id; 921 uint16_t reg_pllxcr; 922 }; 923 924 struct stm32mp1_pll { 925 uint8_t refclk_min; 926 uint8_t refclk_max; 927 }; 928 929 /* Define characteristic of PLL according type */ 930 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 931 [PLL_800] = { 932 .refclk_min = 4, 933 .refclk_max = 16, 934 }, 935 [PLL_1600] = { 936 .refclk_min = 8, 937 .refclk_max = 16, 938 }, 939 [PLL_2000] = { 940 .refclk_min = 8, 941 .refclk_max = 16, 942 }, 943 }; 944 945 #if STM32MP_USB_PROGRAMMER 946 static bool pll4_bootrom; 947 #endif 948 949 /* RCC clock device driver private */ 950 static unsigned int refcounts_mp13[CK_LAST]; 951 952 static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx); 953 954 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 955 static void clk_oscillator_check_bypass(struct stm32_clk_priv *priv, int idx, 956 bool digbyp, bool bypass) 957 { 958 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, idx); 959 struct stm32_clk_bypass *bypass_data = osc_data->bypass; 960 uintptr_t address; 961 962 if (bypass_data == NULL) { 963 return; 964 } 965 966 address = priv->base + bypass_data->offset; 967 if ((mmio_read_32(address) & RCC_OCENR_HSEBYP) && 968 (!(digbyp || bypass))) { 969 panic(); 970 } 971 } 972 #endif 973 974 static void stm32_enable_oscillator_hse(struct stm32_clk_priv *priv) 975 { 976 struct stm32_clk_platdata *pdata = priv->pdata; 977 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_HSE]; 978 bool digbyp = osci->digbyp; 979 bool bypass = osci->bypass; 980 bool css = osci->css; 981 982 if (_clk_stm32_get_rate(priv, _CK_HSE) == 0U) { 983 return; 984 } 985 986 clk_oscillator_set_bypass(priv, _CK_HSE, digbyp, bypass); 987 988 _clk_stm32_enable(priv, _CK_HSE); 989 990 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 991 clk_oscillator_check_bypass(priv, _CK_HSE, digbyp, bypass); 992 #endif 993 994 clk_oscillator_set_css(priv, _CK_HSE, css); 995 } 996 997 static void stm32_enable_oscillator_lse(struct stm32_clk_priv *priv) 998 { 999 struct clk_oscillator_data *osc_data = clk_oscillator_get_data(priv, _CK_LSE); 1000 struct stm32_clk_platdata *pdata = priv->pdata; 1001 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 1002 bool digbyp = osci->digbyp; 1003 bool bypass = osci->bypass; 1004 uint8_t drive = osci->drive; 1005 1006 if (_clk_stm32_get_rate(priv, _CK_LSE) == 0U) { 1007 return; 1008 } 1009 1010 /* Do not reconfigure LSE if already enabled */ 1011 if (_clk_stm32_gate_is_enabled(priv, osc_data->gate_id)) { 1012 return; 1013 } 1014 1015 clk_oscillator_set_bypass(priv, _CK_LSE, digbyp, bypass); 1016 1017 clk_oscillator_set_drive(priv, _CK_LSE, drive); 1018 1019 _clk_stm32_gate_enable(priv, osc_data->gate_id); 1020 } 1021 1022 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1023 { 1024 uint64_t timeout; 1025 uintptr_t rcc_base = stm32mp_rcc_base(); 1026 uintptr_t address = rcc_base + RCC_OCRDYR; 1027 1028 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1029 RCC_HSICFGR_HSIDIV_MASK, 1030 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1031 1032 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1033 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1034 if (timeout_elapsed(timeout)) { 1035 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1036 address, mmio_read_32(address)); 1037 return -ETIMEDOUT; 1038 } 1039 } 1040 1041 return 0; 1042 } 1043 1044 static int stm32mp1_hsidiv(unsigned long hsifreq) 1045 { 1046 uint8_t hsidiv; 1047 uint32_t hsidivfreq = MAX_HSI_HZ; 1048 1049 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1050 if (hsidivfreq == hsifreq) { 1051 break; 1052 } 1053 1054 hsidivfreq /= 2U; 1055 } 1056 1057 if (hsidiv == 4U) { 1058 ERROR("Invalid clk-hsi frequency\n"); 1059 return -EINVAL; 1060 } 1061 1062 if (hsidiv != 0U) { 1063 return stm32mp1_set_hsidiv(hsidiv); 1064 } 1065 1066 return 0; 1067 } 1068 1069 static int stm32_clk_oscillators_lse_set_css(struct stm32_clk_priv *priv) 1070 { 1071 struct stm32_clk_platdata *pdata = priv->pdata; 1072 struct stm32_osci_dt_cfg *osci = &pdata->osci[OSC_LSE]; 1073 1074 clk_oscillator_set_css(priv, _CK_LSE, osci->css); 1075 1076 return 0; 1077 } 1078 1079 static int stm32mp1_come_back_to_hsi(void) 1080 { 1081 int ret; 1082 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1083 1084 /* Come back to HSI */ 1085 ret = _clk_stm32_set_parent(priv, _CKMPU, _CK_HSI); 1086 if (ret != 0) { 1087 return ret; 1088 } 1089 1090 ret = _clk_stm32_set_parent(priv, _CKAXI, _CK_HSI); 1091 if (ret != 0) { 1092 return ret; 1093 } 1094 1095 ret = _clk_stm32_set_parent(priv, _CKMLAHB, _CK_HSI); 1096 if (ret != 0) { 1097 return ret; 1098 } 1099 1100 return 0; 1101 } 1102 1103 static int stm32_clk_configure_clk_get_binding_id(struct stm32_clk_priv *priv, uint32_t data) 1104 { 1105 unsigned long binding_id = ((unsigned long)data & CLK_ID_MASK) >> CLK_ID_SHIFT; 1106 1107 return clk_get_index(priv, binding_id); 1108 } 1109 1110 static int stm32_clk_configure_clk(struct stm32_clk_priv *priv, uint32_t data) 1111 { 1112 int sel = (data & CLK_SEL_MASK) >> CLK_SEL_SHIFT; 1113 int enable = (data & CLK_ON_MASK) >> CLK_ON_SHIFT; 1114 int clk_id; 1115 int ret; 1116 1117 clk_id = stm32_clk_configure_clk_get_binding_id(priv, data); 1118 if (clk_id < 0) { 1119 return clk_id; 1120 } 1121 1122 ret = _clk_stm32_set_parent_by_index(priv, clk_id, sel); 1123 if (ret != 0) { 1124 return ret; 1125 } 1126 1127 if (enable != 0) { 1128 clk_stm32_enable_call_ops(priv, clk_id); 1129 } else { 1130 clk_stm32_disable_call_ops(priv, clk_id); 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int stm32_clk_configure_mux(struct stm32_clk_priv *priv, uint32_t data) 1137 { 1138 int mux = (data & MUX_ID_MASK) >> MUX_ID_SHIFT; 1139 int sel = (data & MUX_SEL_MASK) >> MUX_SEL_SHIFT; 1140 1141 return clk_mux_set_parent(priv, mux, sel); 1142 } 1143 1144 static int stm32_clk_dividers_configure(struct stm32_clk_priv *priv) 1145 { 1146 struct stm32_clk_platdata *pdata = priv->pdata; 1147 uint32_t i; 1148 1149 for (i = 0; i < pdata->nclkdiv; i++) { 1150 int div_id, div_n; 1151 int val; 1152 int ret; 1153 1154 val = pdata->clkdiv[i] & CMD_DATA_MASK; 1155 div_id = (val & DIV_ID_MASK) >> DIV_ID_SHIFT; 1156 div_n = (val & DIV_DIVN_MASK) >> DIV_DIVN_SHIFT; 1157 1158 ret = clk_stm32_set_div(priv, div_id, div_n); 1159 if (ret != 0) { 1160 return ret; 1161 } 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int stm32_clk_source_configure(struct stm32_clk_priv *priv) 1168 { 1169 struct stm32_clk_platdata *pdata = priv->pdata; 1170 bool ckper_disabled = false; 1171 int clk_id; 1172 int ret; 1173 uint32_t i; 1174 1175 for (i = 0; i < pdata->nclksrc; i++) { 1176 uint32_t val = pdata->clksrc[i]; 1177 uint32_t cmd, cmd_data; 1178 1179 if (val == (uint32_t)CLK_CKPER_DISABLED) { 1180 ckper_disabled = true; 1181 continue; 1182 } 1183 1184 if (val == (uint32_t)CLK_RTC_DISABLED) { 1185 continue; 1186 } 1187 1188 cmd = (val & CMD_MASK) >> CMD_SHIFT; 1189 cmd_data = val & ~CMD_MASK; 1190 1191 switch (cmd) { 1192 case CMD_MUX: 1193 ret = stm32_clk_configure_mux(priv, cmd_data); 1194 break; 1195 1196 case CMD_CLK: 1197 clk_id = stm32_clk_configure_clk_get_binding_id(priv, cmd_data); 1198 1199 if (clk_id == _RTCCK) { 1200 if ((_clk_stm32_is_enabled(priv, _RTCCK) == true)) { 1201 continue; 1202 } 1203 } 1204 1205 ret = stm32_clk_configure_clk(priv, cmd_data); 1206 break; 1207 default: 1208 ret = -EINVAL; 1209 break; 1210 } 1211 1212 if (ret != 0) { 1213 return ret; 1214 } 1215 } 1216 1217 /* 1218 * CKPER is source for some peripheral clocks 1219 * (FMC-NAND / QPSI-NOR) and switching source is allowed 1220 * only if previous clock is still ON 1221 * => deactivate CKPER only after switching clock 1222 */ 1223 if (ckper_disabled) { 1224 ret = stm32_clk_configure_mux(priv, CLK_CKPER_DISABLED); 1225 if (ret != 0) { 1226 return ret; 1227 } 1228 } 1229 1230 return 0; 1231 } 1232 1233 static int stm32_clk_stgen_configure(struct stm32_clk_priv *priv, int id) 1234 { 1235 unsigned long stgen_freq; 1236 1237 stgen_freq = _clk_stm32_get_rate(priv, id); 1238 1239 stm32mp_stgen_config(stgen_freq); 1240 1241 return 0; 1242 } 1243 1244 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ 1245 [(_idx)] = {\ 1246 .clk_id = (_clk_id),\ 1247 .plltype = (_type),\ 1248 .reg_pllxcr = (_reg),\ 1249 } 1250 1251 static int clk_stm32_pll_compute_cfgr1(struct stm32_clk_priv *priv, 1252 const struct stm32_clk_pll *pll, 1253 struct stm32_pll_vco *vco, 1254 uint32_t *value) 1255 { 1256 uint32_t divm = vco->div_mn[PLL_CFG_M]; 1257 uint32_t divn = vco->div_mn[PLL_CFG_N]; 1258 unsigned long prate = 0UL; 1259 unsigned long refclk = 0UL; 1260 1261 prate = _clk_stm32_get_parent_rate(priv, pll->clk_id); 1262 refclk = prate / (divm + 1U); 1263 1264 if ((refclk < (stm32mp1_pll[pll->plltype].refclk_min * 1000000U)) || 1265 (refclk > (stm32mp1_pll[pll->plltype].refclk_max * 1000000U))) { 1266 return -EINVAL; 1267 } 1268 1269 *value = 0; 1270 1271 if ((pll->plltype == PLL_800) && (refclk >= 8000000U)) { 1272 *value = 1U << RCC_PLLNCFGR1_IFRGE_SHIFT; 1273 } 1274 1275 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; 1276 *value |= (divm << RCC_PLLNCFGR1_DIVM_SHIFT) & RCC_PLLNCFGR1_DIVM_MASK; 1277 1278 return 0; 1279 } 1280 1281 static uint32_t clk_stm32_pll_compute_cfgr2(struct stm32_pll_output *out) 1282 { 1283 uint32_t value = 0; 1284 1285 value |= (out->output[PLL_CFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & RCC_PLLNCFGR2_DIVP_MASK; 1286 value |= (out->output[PLL_CFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & RCC_PLLNCFGR2_DIVQ_MASK; 1287 value |= (out->output[PLL_CFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & RCC_PLLNCFGR2_DIVR_MASK; 1288 1289 return value; 1290 } 1291 1292 static void clk_stm32_pll_config_vco(struct stm32_clk_priv *priv, 1293 const struct stm32_clk_pll *pll, 1294 struct stm32_pll_vco *vco) 1295 { 1296 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1297 uint32_t value = 0; 1298 1299 if (clk_stm32_pll_compute_cfgr1(priv, pll, vco, &value) != 0) { 1300 ERROR("Invalid Vref clock !\n"); 1301 panic(); 1302 } 1303 1304 /* Write N / M / IFREGE fields */ 1305 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR1, value); 1306 1307 /* Fractional configuration */ 1308 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, 0); 1309 1310 /* Frac must be enabled only once its configuration is loaded */ 1311 mmio_write_32(pll_base + RCC_OFFSET_PLLXFRACR, vco->frac << RCC_PLLNFRACR_FRACV_SHIFT); 1312 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXFRACR, RCC_PLLNFRACR_FRACLE); 1313 } 1314 1315 static void clk_stm32_pll_config_csg(struct stm32_clk_priv *priv, 1316 const struct stm32_clk_pll *pll, 1317 struct stm32_pll_vco *vco) 1318 { 1319 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1320 uint32_t mod_per = 0; 1321 uint32_t inc_step = 0; 1322 uint32_t sscg_mode = 0; 1323 uint32_t value = 0; 1324 1325 if (!vco->csg_enabled) { 1326 return; 1327 } 1328 1329 mod_per = vco->csg[PLL_CSG_MOD_PER]; 1330 inc_step = vco->csg[PLL_CSG_INC_STEP]; 1331 sscg_mode = vco->csg[PLL_CSG_SSCG_MODE]; 1332 1333 value |= (mod_per << RCC_PLLNCSGR_MOD_PER_SHIFT) & RCC_PLLNCSGR_MOD_PER_MASK; 1334 value |= (inc_step << RCC_PLLNCSGR_INC_STEP_SHIFT) & RCC_PLLNCSGR_INC_STEP_MASK; 1335 value |= (sscg_mode << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & RCC_PLLNCSGR_SSCG_MODE_MASK; 1336 1337 mmio_write_32(pll_base + RCC_OFFSET_PLLXCSGR, value); 1338 mmio_setbits_32(pll_base + RCC_OFFSET_PLLXCR, RCC_PLLNCR_SSCG_CTRL); 1339 } 1340 1341 static void clk_stm32_pll_config_out(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll, 1342 struct stm32_pll_output *out) 1343 { 1344 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1345 uint32_t value = 0; 1346 1347 value = clk_stm32_pll_compute_cfgr2(out); 1348 1349 mmio_write_32(pll_base + RCC_OFFSET_PLLXCFGR2, value); 1350 } 1351 1352 static inline struct stm32_pll_dt_cfg *clk_stm32_pll_get_pdata(int pll_idx) 1353 { 1354 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1355 struct stm32_clk_platdata *pdata = priv->pdata; 1356 1357 return &pdata->pll[pll_idx]; 1358 } 1359 1360 static bool _clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 1361 { 1362 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1363 1364 return ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLON) != 0U); 1365 } 1366 1367 static void _clk_stm32_pll_set_on(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 1368 { 1369 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1370 1371 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1372 mmio_clrsetbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN, 1373 RCC_PLLNCR_PLLON); 1374 } 1375 1376 static void _clk_stm32_pll_set_off(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 1377 { 1378 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1379 1380 /* Stop all output */ 1381 mmio_clrbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1382 1383 /* Stop PLL */ 1384 mmio_clrbits_32(pll_base, RCC_PLLNCR_PLLON); 1385 } 1386 1387 static int _clk_stm32_pll_wait_ready_on(struct stm32_clk_priv *priv, 1388 const struct stm32_clk_pll *pll) 1389 { 1390 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1391 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1392 1393 /* Wait PLL lock */ 1394 while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) == 0U) { 1395 if (timeout_elapsed(timeout)) { 1396 ERROR("PLL%d start failed @ 0x%x: 0x%x\n", 1397 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base)); 1398 return -EINVAL; 1399 } 1400 } 1401 1402 return 0; 1403 } 1404 1405 static int _clk_stm32_pll_wait_ready_off(struct stm32_clk_priv *priv, 1406 const struct stm32_clk_pll *pll) 1407 { 1408 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1409 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1410 1411 /* Wait PLL lock */ 1412 while ((mmio_read_32(pll_base) & RCC_PLLNCR_PLLRDY) != 0U) { 1413 if (timeout_elapsed(timeout)) { 1414 ERROR("PLL%d stop failed @ 0x%x: 0x%x\n", 1415 pll->clk_id - _CK_PLL1 + 1, pll->reg_pllxcr, mmio_read_32(pll_base)); 1416 return -EINVAL; 1417 } 1418 } 1419 1420 return 0; 1421 } 1422 1423 static int _clk_stm32_pll_enable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 1424 { 1425 if (_clk_stm32_pll_is_enabled(priv, pll)) { 1426 return 0; 1427 } 1428 1429 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1430 _clk_stm32_pll_set_on(priv, pll); 1431 1432 /* Wait PLL lock */ 1433 return _clk_stm32_pll_wait_ready_on(priv, pll); 1434 } 1435 1436 static void _clk_stm32_pll_disable(struct stm32_clk_priv *priv, const struct stm32_clk_pll *pll) 1437 { 1438 if (!_clk_stm32_pll_is_enabled(priv, pll)) { 1439 return; 1440 } 1441 1442 /* Stop all outputs and the PLL */ 1443 _clk_stm32_pll_set_off(priv, pll); 1444 1445 /* Wait PLL stopped */ 1446 _clk_stm32_pll_wait_ready_off(priv, pll); 1447 } 1448 1449 static int _clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx, 1450 struct stm32_pll_dt_cfg *pll_conf) 1451 { 1452 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_idx); 1453 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1454 int ret = 0; 1455 1456 /* Configure PLLs source */ 1457 ret = stm32_clk_configure_mux(priv, pll_conf->vco.src); 1458 if (ret != 0) { 1459 return ret; 1460 } 1461 1462 #if STM32MP_USB_PROGRAMMER 1463 if ((pll_idx == _PLL4) && pll4_bootrom) { 1464 clk_stm32_pll_config_out(priv, pll, &pll_conf->output); 1465 1466 mmio_setbits_32(pll_base, 1467 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1468 1469 return 0; 1470 } 1471 #endif 1472 /* Stop the PLL before */ 1473 _clk_stm32_pll_disable(priv, pll); 1474 1475 clk_stm32_pll_config_vco(priv, pll, &pll_conf->vco); 1476 clk_stm32_pll_config_out(priv, pll, &pll_conf->output); 1477 clk_stm32_pll_config_csg(priv, pll, &pll_conf->vco); 1478 1479 ret = _clk_stm32_pll_enable(priv, pll); 1480 if (ret != 0) { 1481 return ret; 1482 } 1483 1484 mmio_setbits_32(pll_base, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN); 1485 1486 return 0; 1487 } 1488 1489 static int clk_stm32_pll_init(struct stm32_clk_priv *priv, int pll_idx) 1490 { 1491 struct stm32_pll_dt_cfg *pll_conf = clk_stm32_pll_get_pdata(pll_idx); 1492 1493 if (pll_conf->vco.status != 0U) { 1494 return _clk_stm32_pll_init(priv, pll_idx, pll_conf); 1495 } 1496 1497 return 0; 1498 } 1499 1500 static int stm32_clk_pll_configure(struct stm32_clk_priv *priv) 1501 { 1502 int err = 0; 1503 1504 err = clk_stm32_pll_init(priv, _PLL1); 1505 if (err != 0) { 1506 return err; 1507 } 1508 1509 err = clk_stm32_pll_init(priv, _PLL2); 1510 if (err != 0) { 1511 return err; 1512 } 1513 1514 err = clk_stm32_pll_init(priv, _PLL3); 1515 if (err != 0) { 1516 return err; 1517 } 1518 1519 err = clk_stm32_pll_init(priv, _PLL4); 1520 if (err != 0) { 1521 return err; 1522 } 1523 1524 return 0; 1525 } 1526 1527 static int stm32_clk_oscillators_wait_lse_ready(struct stm32_clk_priv *priv) 1528 { 1529 int ret = 0; 1530 1531 if (_clk_stm32_get_rate(priv, _CK_LSE) != 0U) { 1532 ret = clk_oscillator_wait_ready_on(priv, _CK_LSE); 1533 } 1534 1535 return ret; 1536 } 1537 1538 static void stm32_clk_oscillators_enable(struct stm32_clk_priv *priv) 1539 { 1540 stm32_enable_oscillator_hse(priv); 1541 stm32_enable_oscillator_lse(priv); 1542 _clk_stm32_enable(priv, _CK_LSI); 1543 _clk_stm32_enable(priv, _CK_CSI); 1544 } 1545 1546 static int stm32_clk_hsidiv_configure(struct stm32_clk_priv *priv) 1547 { 1548 return stm32mp1_hsidiv(_clk_stm32_get_rate(priv, _CK_HSI)); 1549 } 1550 1551 #if STM32MP_USB_PROGRAMMER 1552 static bool stm32mp1_clk_is_pll4_used_by_bootrom(struct stm32_clk_priv *priv, int usbphy_p) 1553 { 1554 /* Don't initialize PLL4, when used by BOOTROM */ 1555 if ((stm32mp_get_boot_itf_selected() == 1556 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 1557 (usbphy_p == _PLL4R)) { 1558 return true; 1559 } 1560 1561 return false; 1562 } 1563 1564 static int stm32mp1_clk_check_usb_conflict(struct stm32_clk_priv *priv, int usbphy_p, int usbo_p) 1565 { 1566 int _usbo_p; 1567 int _usbphy_p; 1568 1569 if (!pll4_bootrom) { 1570 return 0; 1571 } 1572 1573 _usbo_p = _clk_stm32_get_parent(priv, _USBO_K); 1574 _usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); 1575 1576 if ((_usbo_p != usbo_p) || (_usbphy_p != usbphy_p)) { 1577 return -FDT_ERR_BADVALUE; 1578 } 1579 1580 return 0; 1581 } 1582 #endif 1583 1584 static struct clk_oscillator_data stm32mp13_osc_data[NB_OSCILLATOR] = { 1585 OSCILLATOR(OSC_HSI, _CK_HSI, "clk-hsi", GATE_HSI, GATE_HSI_RDY, 1586 NULL, NULL, NULL), 1587 1588 OSCILLATOR(OSC_LSI, _CK_LSI, "clk-lsi", GATE_LSI, GATE_LSI_RDY, 1589 NULL, NULL, NULL), 1590 1591 OSCILLATOR(OSC_CSI, _CK_CSI, "clk-csi", GATE_CSI, GATE_CSI_RDY, 1592 NULL, NULL, NULL), 1593 1594 OSCILLATOR(OSC_LSE, _CK_LSE, "clk-lse", GATE_LSE, GATE_LSE_RDY, 1595 BYPASS(RCC_BDCR, 1, 3), 1596 CSS(RCC_BDCR, 8), 1597 DRIVE(RCC_BDCR, 4, 2, 2)), 1598 1599 OSCILLATOR(OSC_HSE, _CK_HSE, "clk-hse", GATE_HSE, GATE_HSE_RDY, 1600 BYPASS(RCC_OCENSETR, 10, 7), 1601 CSS(RCC_OCENSETR, 11), 1602 NULL), 1603 1604 OSCILLATOR(OSC_I2SCKIN, _I2SCKIN, "i2s_ckin", NO_GATE, NO_GATE, 1605 NULL, NULL, NULL), 1606 }; 1607 1608 static const char *clk_stm32_get_oscillator_name(enum stm32_osc id) 1609 { 1610 if (id < NB_OSCILLATOR) { 1611 return stm32mp13_osc_data[id].name; 1612 } 1613 1614 return NULL; 1615 } 1616 1617 #define CLK_PLL_CFG(_idx, _clk_id, _type, _reg)\ 1618 [(_idx)] = {\ 1619 .clk_id = (_clk_id),\ 1620 .plltype = (_type),\ 1621 .reg_pllxcr = (_reg),\ 1622 } 1623 1624 static const struct stm32_clk_pll stm32_mp13_clk_pll[_PLL_NB] = { 1625 CLK_PLL_CFG(_PLL1, _CK_PLL1, PLL_2000, RCC_PLL1CR), 1626 CLK_PLL_CFG(_PLL2, _CK_PLL2, PLL_1600, RCC_PLL2CR), 1627 CLK_PLL_CFG(_PLL3, _CK_PLL3, PLL_800, RCC_PLL3CR), 1628 CLK_PLL_CFG(_PLL4, _CK_PLL4, PLL_800, RCC_PLL4CR), 1629 }; 1630 1631 static const struct stm32_clk_pll *clk_st32_pll_data(unsigned int idx) 1632 { 1633 return &stm32_mp13_clk_pll[idx]; 1634 } 1635 1636 struct stm32_pll_cfg { 1637 int pll_id; 1638 }; 1639 1640 static unsigned long clk_stm32_pll_recalc_rate(struct stm32_clk_priv *priv, int id, 1641 unsigned long prate) 1642 { 1643 const struct clk_stm32 *clk = _clk_get(priv, id); 1644 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 1645 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); 1646 uintptr_t pll_base = priv->base + pll->reg_pllxcr; 1647 uint32_t cfgr1, fracr, divm, divn; 1648 unsigned long fvco; 1649 1650 cfgr1 = mmio_read_32(pll_base + RCC_OFFSET_PLLXCFGR1); 1651 fracr = mmio_read_32(pll_base + RCC_OFFSET_PLLXFRACR); 1652 1653 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 1654 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 1655 1656 /* 1657 * With FRACV : 1658 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 1659 * Without FRACV 1660 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 1661 */ 1662 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 1663 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 1664 RCC_PLLNFRACR_FRACV_SHIFT; 1665 unsigned long long numerator, denominator; 1666 1667 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 1668 numerator = prate * numerator; 1669 denominator = ((unsigned long long)divm + 1U) << 13; 1670 fvco = (unsigned long)(numerator / denominator); 1671 } else { 1672 fvco = (unsigned long)(prate * (divn + 1U) / (divm + 1U)); 1673 } 1674 1675 return fvco; 1676 }; 1677 1678 static bool clk_stm32_pll_is_enabled(struct stm32_clk_priv *priv, int id) 1679 { 1680 const struct clk_stm32 *clk = _clk_get(priv, id); 1681 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 1682 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); 1683 1684 return _clk_stm32_pll_is_enabled(priv, pll); 1685 } 1686 1687 static int clk_stm32_pll_enable(struct stm32_clk_priv *priv, int id) 1688 { 1689 const struct clk_stm32 *clk = _clk_get(priv, id); 1690 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 1691 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); 1692 1693 return _clk_stm32_pll_enable(priv, pll); 1694 } 1695 1696 static void clk_stm32_pll_disable(struct stm32_clk_priv *priv, int id) 1697 { 1698 const struct clk_stm32 *clk = _clk_get(priv, id); 1699 struct stm32_pll_cfg *pll_cfg = clk->clock_cfg; 1700 const struct stm32_clk_pll *pll = clk_st32_pll_data(pll_cfg->pll_id); 1701 1702 _clk_stm32_pll_disable(priv, pll); 1703 } 1704 1705 static const struct stm32_clk_ops clk_stm32_pll_ops = { 1706 .recalc_rate = clk_stm32_pll_recalc_rate, 1707 .enable = clk_stm32_pll_enable, 1708 .disable = clk_stm32_pll_disable, 1709 .is_enabled = clk_stm32_pll_is_enabled, 1710 }; 1711 1712 #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ 1713 .binding = _idx,\ 1714 .parent = _parent,\ 1715 .flags = (_flags),\ 1716 .clock_cfg = &(struct stm32_pll_cfg) {\ 1717 .pll_id = _pll_id,\ 1718 },\ 1719 .ops = &clk_stm32_pll_ops,\ 1720 } 1721 1722 struct clk_stm32_composite_cfg { 1723 int gate_id; 1724 int div_id; 1725 }; 1726 1727 static unsigned long clk_stm32_composite_recalc_rate(struct stm32_clk_priv *priv, 1728 int idx, unsigned long prate) 1729 { 1730 const struct clk_stm32 *clk = _clk_get(priv, idx); 1731 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; 1732 1733 return _clk_stm32_divider_recalc(priv, composite_cfg->div_id, prate); 1734 }; 1735 1736 static bool clk_stm32_composite_gate_is_enabled(struct stm32_clk_priv *priv, int idx) 1737 { 1738 const struct clk_stm32 *clk = _clk_get(priv, idx); 1739 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; 1740 1741 return _clk_stm32_gate_is_enabled(priv, composite_cfg->gate_id); 1742 } 1743 1744 static int clk_stm32_composite_gate_enable(struct stm32_clk_priv *priv, int idx) 1745 { 1746 const struct clk_stm32 *clk = _clk_get(priv, idx); 1747 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; 1748 1749 return _clk_stm32_gate_enable(priv, composite_cfg->gate_id); 1750 } 1751 1752 static void clk_stm32_composite_gate_disable(struct stm32_clk_priv *priv, int idx) 1753 { 1754 const struct clk_stm32 *clk = _clk_get(priv, idx); 1755 struct clk_stm32_composite_cfg *composite_cfg = clk->clock_cfg; 1756 1757 _clk_stm32_gate_disable(priv, composite_cfg->gate_id); 1758 } 1759 1760 static const struct stm32_clk_ops clk_stm32_composite_ops = { 1761 .recalc_rate = clk_stm32_composite_recalc_rate, 1762 .is_enabled = clk_stm32_composite_gate_is_enabled, 1763 .enable = clk_stm32_composite_gate_enable, 1764 .disable = clk_stm32_composite_gate_disable, 1765 }; 1766 1767 #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ 1768 _div_id)[idx] = {\ 1769 .binding = (_binding),\ 1770 .parent = (_parent),\ 1771 .flags = (_flags),\ 1772 .clock_cfg = &(struct clk_stm32_composite_cfg) {\ 1773 .gate_id = (_gate_id),\ 1774 .div_id = (_div_id),\ 1775 },\ 1776 .ops = &clk_stm32_composite_ops,\ 1777 } 1778 1779 static const struct clk_stm32 stm32mp13_clk[CK_LAST] = { 1780 /* ROOT CLOCKS */ 1781 CLK_FIXED_RATE(_CK_OFF, _NO_ID, 0), 1782 CLK_OSC(_CK_HSE, CK_HSE, CLK_IS_ROOT, OSC_HSE), 1783 CLK_OSC(_CK_HSI, CK_HSI, CLK_IS_ROOT, OSC_HSI), 1784 CLK_OSC(_CK_CSI, CK_CSI, CLK_IS_ROOT, OSC_CSI), 1785 CLK_OSC(_CK_LSI, CK_LSI, CLK_IS_ROOT, OSC_LSI), 1786 CLK_OSC(_CK_LSE, CK_LSE, CLK_IS_ROOT, OSC_LSE), 1787 1788 CLK_OSC_FIXED(_I2SCKIN, _NO_ID, CLK_IS_ROOT, OSC_I2SCKIN), 1789 1790 CLK_FIXED_RATE(_USB_PHY_48, _NO_ID, USB_PHY_48_MHZ), 1791 1792 STM32_DIV(_HSE_DIV, _NO_ID, _CK_HSE, 0, DIV_RTC), 1793 1794 FIXED_FACTOR(_HSE_DIV2, CK_HSE_DIV2, _CK_HSE, 1, 2), 1795 FIXED_FACTOR(_CSI_DIV122, _NO_ID, _CK_CSI, 1, 122), 1796 1797 CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0), 1798 CLK_PLL(_CK_PLL2, PLL2, MUX(MUX_PLL12), GATE_PLL2, _PLL2, 0), 1799 CLK_PLL(_CK_PLL3, PLL3, MUX(MUX_PLL3), GATE_PLL3, _PLL3, 0), 1800 CLK_PLL(_CK_PLL4, PLL4, MUX(MUX_PLL4), GATE_PLL4, _PLL4, 0), 1801 1802 STM32_COMPOSITE(_PLL1P, PLL1_P, _CK_PLL1, CLK_IS_CRITICAL, GATE_PLL1_DIVP, DIV_PLL1DIVP), 1803 STM32_DIV(_PLL1P_DIV, _NO_ID, _CK_PLL1, 0, DIV_MPU), 1804 1805 STM32_COMPOSITE(_PLL2P, PLL2_P, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVP, DIV_PLL2DIVP), 1806 STM32_COMPOSITE(_PLL2Q, PLL2_Q, _CK_PLL2, 0, GATE_PLL2_DIVQ, DIV_PLL2DIVQ), 1807 STM32_COMPOSITE(_PLL2R, PLL2_R, _CK_PLL2, CLK_IS_CRITICAL, GATE_PLL2_DIVR, DIV_PLL2DIVR), 1808 1809 STM32_COMPOSITE(_PLL3P, PLL3_P, _CK_PLL3, 0, GATE_PLL3_DIVP, DIV_PLL3DIVP), 1810 STM32_COMPOSITE(_PLL3Q, PLL3_Q, _CK_PLL3, 0, GATE_PLL3_DIVQ, DIV_PLL3DIVQ), 1811 STM32_COMPOSITE(_PLL3R, PLL3_R, _CK_PLL3, 0, GATE_PLL3_DIVR, DIV_PLL3DIVR), 1812 1813 STM32_COMPOSITE(_PLL4P, PLL4_P, _CK_PLL4, 0, GATE_PLL4_DIVP, DIV_PLL4DIVP), 1814 STM32_COMPOSITE(_PLL4Q, PLL4_Q, _CK_PLL4, 0, GATE_PLL4_DIVQ, DIV_PLL4DIVQ), 1815 STM32_COMPOSITE(_PLL4R, PLL4_R, _CK_PLL4, 0, GATE_PLL4_DIVR, DIV_PLL4DIVR), 1816 1817 STM32_MUX(_CKMPU, CK_MPU, MUX_MPU, 0), 1818 STM32_DIV(_CKAXI, CK_AXI, MUX(MUX_AXI), 0, DIV_AXI), 1819 STM32_DIV(_CKMLAHB, CK_MLAHB, MUX(MUX_MLAHB), CLK_IS_CRITICAL, DIV_MLAHB), 1820 STM32_MUX(_CKPER, CK_PER, MUX(MUX_CKPER), 0), 1821 1822 STM32_DIV(_PCLK1, PCLK1, _CKMLAHB, 0, DIV_APB1), 1823 STM32_DIV(_PCLK2, PCLK2, _CKMLAHB, 0, DIV_APB2), 1824 STM32_DIV(_PCLK3, PCLK3, _CKMLAHB, 0, DIV_APB3), 1825 STM32_DIV(_PCLK4, PCLK4, _CKAXI, 0, DIV_APB4), 1826 STM32_DIV(_PCLK5, PCLK5, _CKAXI, 0, DIV_APB5), 1827 STM32_DIV(_PCLK6, PCLK6, _CKMLAHB, 0, DIV_APB6), 1828 1829 CK_TIMER(_CKTIMG1, CK_TIMG1, _PCLK1, 0, RCC_APB1DIVR, RCC_TIMG1PRER), 1830 CK_TIMER(_CKTIMG2, CK_TIMG2, _PCLK2, 0, RCC_APB2DIVR, RCC_TIMG2PRER), 1831 CK_TIMER(_CKTIMG3, CK_TIMG3, _PCLK6, 0, RCC_APB6DIVR, RCC_TIMG3PRER), 1832 1833 /* END ROOT CLOCKS */ 1834 1835 STM32_GATE(_DDRC1, DDRC1, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1), 1836 STM32_GATE(_DDRC1LP, DDRC1LP, _CKAXI, CLK_IS_CRITICAL, GATE_DDRC1LP), 1837 STM32_GATE(_DDRPHYC, DDRPHYC, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYC), 1838 STM32_GATE(_DDRPHYCLP, DDRPHYCLP, _PLL2R, CLK_IS_CRITICAL, GATE_DDRPHYCLP), 1839 STM32_GATE(_DDRCAPB, DDRCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPB), 1840 STM32_GATE(_DDRCAPBLP, DDRCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRCAPBLP), 1841 STM32_GATE(_AXIDCG, AXIDCG, _CKAXI, CLK_IS_CRITICAL, GATE_AXIDCG), 1842 STM32_GATE(_DDRPHYCAPB, DDRPHYCAPB, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPB), 1843 STM32_GATE(_DDRPHYCAPBLP, DDRPHYCAPBLP, _PCLK4, CLK_IS_CRITICAL, GATE_DDRPHYCAPBLP), 1844 1845 STM32_GATE(_SYSCFG, SYSCFG, _PCLK3, 0, GATE_SYSCFG), 1846 STM32_GATE(_DDRPERFM, DDRPERFM, _PCLK4, 0, GATE_DDRPERFM), 1847 STM32_GATE(_IWDG2APB, IWDG2, _PCLK4, 0, GATE_IWDG2APB), 1848 STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY), 1849 STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO), 1850 1851 STM32_GATE(_RTCAPB, RTCAPB, _PCLK5, CLK_IS_CRITICAL, GATE_RTCAPB), 1852 STM32_GATE(_TZC, TZC, _PCLK5, CLK_IS_CRITICAL, GATE_TZC), 1853 STM32_GATE(_ETZPC, TZPC, _PCLK5, CLK_IS_CRITICAL, GATE_ETZPC), 1854 STM32_GATE(_IWDG1APB, IWDG1, _PCLK5, 0, GATE_IWDG1APB), 1855 STM32_GATE(_BSEC, BSEC, _PCLK5, CLK_IS_CRITICAL, GATE_BSEC), 1856 STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC), 1857 1858 STM32_GATE(_USART1_K, USART1_K, MUX(MUX_UART1), 0, GATE_USART1), 1859 STM32_GATE(_USART2_K, USART2_K, MUX(MUX_UART2), 0, GATE_USART2), 1860 STM32_GATE(_I2C3_K, I2C3_K, MUX(MUX_I2C3), 0, GATE_I2C3), 1861 STM32_GATE(_I2C4_K, I2C4_K, MUX(MUX_I2C4), 0, GATE_I2C4), 1862 STM32_GATE(_I2C5_K, I2C5_K, MUX(MUX_I2C5), 0, GATE_I2C5), 1863 STM32_GATE(_TIM12, TIM12_K, _CKTIMG3, 0, GATE_TIM12), 1864 STM32_GATE(_TIM15, TIM15_K, _CKTIMG3, 0, GATE_TIM15), 1865 1866 STM32_GATE(_RTCCK, RTC, MUX(MUX_RTC), 0, GATE_RTCCK), 1867 1868 STM32_GATE(_GPIOA, GPIOA, _CKMLAHB, 0, GATE_GPIOA), 1869 STM32_GATE(_GPIOB, GPIOB, _CKMLAHB, 0, GATE_GPIOB), 1870 STM32_GATE(_GPIOC, GPIOC, _CKMLAHB, 0, GATE_GPIOC), 1871 STM32_GATE(_GPIOD, GPIOD, _CKMLAHB, 0, GATE_GPIOD), 1872 STM32_GATE(_GPIOE, GPIOE, _CKMLAHB, 0, GATE_GPIOE), 1873 STM32_GATE(_GPIOF, GPIOF, _CKMLAHB, 0, GATE_GPIOF), 1874 STM32_GATE(_GPIOG, GPIOG, _CKMLAHB, 0, GATE_GPIOG), 1875 STM32_GATE(_GPIOH, GPIOH, _CKMLAHB, 0, GATE_GPIOH), 1876 STM32_GATE(_GPIOI, GPIOI, _CKMLAHB, 0, GATE_GPIOI), 1877 1878 STM32_GATE(_PKA, PKA, _CKAXI, 0, GATE_PKA), 1879 STM32_GATE(_SAES_K, SAES_K, MUX(MUX_SAES), 0, GATE_SAES), 1880 STM32_GATE(_CRYP1, CRYP1, _PCLK5, 0, GATE_CRYP1), 1881 STM32_GATE(_HASH1, HASH1, _PCLK5, 0, GATE_HASH1), 1882 1883 STM32_GATE(_RNG1_K, RNG1_K, MUX(MUX_RNG1), 0, GATE_RNG1), 1884 STM32_GATE(_BKPSRAM, BKPSRAM, _PCLK5, CLK_IS_CRITICAL, GATE_BKPSRAM), 1885 1886 STM32_GATE(_SDMMC1_K, SDMMC1_K, MUX(MUX_SDMMC1), 0, GATE_SDMMC1), 1887 STM32_GATE(_SDMMC2_K, SDMMC2_K, MUX(MUX_SDMMC2), 0, GATE_SDMMC2), 1888 STM32_GATE(_DBGCK, CK_DBG, _CKAXI, 0, GATE_DBGCK), 1889 1890 /* TODO: CHECK CLOCK FOR BL2/BL32 AND IF ONLY FOR TEST OR NOT */ 1891 STM32_GATE(_USART3_K, USART3_K, MUX(MUX_UART35), 0, GATE_USART3), 1892 STM32_GATE(_UART4_K, UART4_K, MUX(MUX_UART4), 0, GATE_UART4), 1893 STM32_GATE(_UART5_K, UART5_K, MUX(MUX_UART35), 0, GATE_UART5), 1894 STM32_GATE(_UART7_K, UART7_K, MUX(MUX_UART78), 0, GATE_UART7), 1895 STM32_GATE(_UART8_K, UART8_K, MUX(MUX_UART78), 0, GATE_UART8), 1896 STM32_GATE(_USART6_K, USART6_K, MUX(MUX_UART6), 0, GATE_USART6), 1897 STM32_GATE(_MCE, MCE, _CKAXI, CLK_IS_CRITICAL, GATE_MCE), 1898 STM32_GATE(_FMC_K, FMC_K, MUX(MUX_FMC), 0, GATE_FMC), 1899 STM32_GATE(_QSPI_K, QSPI_K, MUX(MUX_QSPI), 0, GATE_QSPI), 1900 1901 STM32_COMPOSITE(_MCO1_K, CK_MCO1, MUX(MUX_MCO1), 0, GATE_MCO1, DIV_MCO1), 1902 STM32_COMPOSITE(_MCO2_K, CK_MCO2, MUX(MUX_MCO2), 0, GATE_MCO2, DIV_MCO2), 1903 STM32_COMPOSITE(_TRACECK, CK_TRACE, _CKAXI, 0, GATE_TRACECK, DIV_TRACE), 1904 1905 #if defined(IMAGE_BL32) 1906 STM32_GATE(_TIM2, TIM2_K, _CKTIMG1, 0, GATE_TIM2), 1907 STM32_GATE(_TIM3, TIM3_K, _CKTIMG1, 0, GATE_TIM3), 1908 STM32_GATE(_TIM4, TIM4_K, _CKTIMG1, 0, GATE_TIM4), 1909 STM32_GATE(_TIM5, TIM5_K, _CKTIMG1, 0, GATE_TIM5), 1910 STM32_GATE(_TIM6, TIM6_K, _CKTIMG1, 0, GATE_TIM6), 1911 STM32_GATE(_TIM7, TIM7_K, _CKTIMG1, 0, GATE_TIM7), 1912 STM32_GATE(_TIM13, TIM13_K, _CKTIMG3, 0, GATE_TIM13), 1913 STM32_GATE(_TIM14, TIM14_K, _CKTIMG3, 0, GATE_TIM14), 1914 STM32_GATE(_LPTIM1_K, LPTIM1_K, MUX(MUX_LPTIM1), 0, GATE_LPTIM1), 1915 STM32_GATE(_SPI2_K, SPI2_K, MUX(MUX_SPI23), 0, GATE_SPI2), 1916 STM32_GATE(_SPI3_K, SPI3_K, MUX(MUX_SPI23), 0, GATE_SPI3), 1917 STM32_GATE(_SPDIF_K, SPDIF_K, MUX(MUX_SPDIF), 0, GATE_SPDIF), 1918 STM32_GATE(_TIM1, TIM1_K, _CKTIMG2, 0, GATE_TIM1), 1919 STM32_GATE(_TIM8, TIM8_K, _CKTIMG2, 0, GATE_TIM8), 1920 STM32_GATE(_TIM16, TIM16_K, _CKTIMG3, 0, GATE_TIM16), 1921 STM32_GATE(_TIM17, TIM17_K, _CKTIMG3, 0, GATE_TIM17), 1922 STM32_GATE(_SPI1_K, SPI1_K, MUX(MUX_SPI1), 0, GATE_SPI1), 1923 STM32_GATE(_SPI4_K, SPI4_K, MUX(MUX_SPI4), 0, GATE_SPI4), 1924 STM32_GATE(_SPI5_K, SPI5_K, MUX(MUX_SPI5), 0, GATE_SPI5), 1925 STM32_GATE(_SAI1_K, SAI1_K, MUX(MUX_SAI1), 0, GATE_SAI1), 1926 STM32_GATE(_SAI2_K, SAI2_K, MUX(MUX_SAI2), 0, GATE_SAI2), 1927 STM32_GATE(_DFSDM, DFSDM_K, MUX(MUX_SAI1), 0, GATE_DFSDM), 1928 STM32_GATE(_FDCAN_K, FDCAN_K, MUX(MUX_FDCAN), 0, GATE_FDCAN), 1929 STM32_GATE(_USBH, USBH, _CKAXI, 0, GATE_USBH), 1930 STM32_GATE(_I2C1_K, I2C1_K, MUX(MUX_I2C12), 0, GATE_I2C1), 1931 STM32_GATE(_I2C2_K, I2C2_K, MUX(MUX_I2C12), 0, GATE_I2C2), 1932 STM32_GATE(_ADFSDM, ADFSDM_K, MUX(MUX_SAI1), 0, GATE_ADFSDM), 1933 STM32_GATE(_LPTIM2_K, LPTIM2_K, MUX(MUX_LPTIM2), 0, GATE_LPTIM2), 1934 STM32_GATE(_LPTIM3_K, LPTIM3_K, MUX(MUX_LPTIM3), 0, GATE_LPTIM3), 1935 STM32_GATE(_LPTIM4_K, LPTIM4_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM4), 1936 STM32_GATE(_LPTIM5_K, LPTIM5_K, MUX(MUX_LPTIM45), 0, GATE_LPTIM5), 1937 STM32_GATE(_VREF, VREF, _PCLK3, 0, GATE_VREF), 1938 STM32_GATE(_DTS, TMPSENS, _PCLK3, 0, GATE_DTS), 1939 STM32_GATE(_PMBCTRL, PMBCTRL, _PCLK3, 0, GATE_HDP), 1940 STM32_GATE(_HDP, HDP, _PCLK3, 0, GATE_PMBCTRL), 1941 STM32_GATE(_STGENRO, STGENRO, _PCLK4, 0, GATE_DCMIPP), 1942 STM32_GATE(_DCMIPP_K, DCMIPP_K, MUX(MUX_DCMIPP), 0, GATE_DCMIPP), 1943 STM32_GATE(_DMAMUX1, DMAMUX1, _CKAXI, 0, GATE_DMAMUX1), 1944 STM32_GATE(_DMAMUX2, DMAMUX2, _CKAXI, 0, GATE_DMAMUX2), 1945 STM32_GATE(_DMA3, DMA3, _CKAXI, 0, GATE_DMAMUX2), 1946 STM32_GATE(_ADC1_K, ADC1_K, MUX(MUX_ADC1), 0, GATE_ADC1), 1947 STM32_GATE(_ADC2_K, ADC2_K, MUX(MUX_ADC2), 0, GATE_ADC2), 1948 STM32_GATE(_TSC, TSC, _CKAXI, 0, GATE_TSC), 1949 STM32_GATE(_AXIMC, AXIMC, _CKAXI, 0, GATE_AXIMC), 1950 STM32_GATE(_CRC1, CRC1, _CKAXI, 0, GATE_ETH1TX), 1951 STM32_GATE(_ETH1CK, ETH1CK_K, MUX(MUX_ETH1), 0, GATE_ETH1CK), 1952 STM32_GATE(_ETH1TX, ETH1TX, _CKAXI, 0, GATE_ETH1TX), 1953 STM32_GATE(_ETH1RX, ETH1RX, _CKAXI, 0, GATE_ETH1RX), 1954 STM32_GATE(_ETH2CK, ETH2CK_K, MUX(MUX_ETH2), 0, GATE_ETH2CK), 1955 STM32_GATE(_ETH2TX, ETH2TX, _CKAXI, 0, GATE_ETH2TX), 1956 STM32_GATE(_ETH2RX, ETH2RX, _CKAXI, 0, GATE_ETH2RX), 1957 STM32_GATE(_ETH2MAC, ETH2MAC, _CKAXI, 0, GATE_ETH2MAC), 1958 #endif 1959 }; 1960 1961 static struct stm32_pll_dt_cfg mp13_pll[_PLL_NB]; 1962 1963 static struct stm32_osci_dt_cfg mp13_osci[NB_OSCILLATOR]; 1964 1965 static uint32_t mp13_clksrc[MUX_MAX]; 1966 1967 static uint32_t mp13_clkdiv[DIV_MAX]; 1968 1969 static struct stm32_clk_platdata stm32mp13_clock_pdata = { 1970 .osci = mp13_osci, 1971 .nosci = NB_OSCILLATOR, 1972 .pll = mp13_pll, 1973 .npll = _PLL_NB, 1974 .clksrc = mp13_clksrc, 1975 .nclksrc = MUX_MAX, 1976 .clkdiv = mp13_clkdiv, 1977 .nclkdiv = DIV_MAX, 1978 }; 1979 1980 static struct stm32_clk_priv stm32mp13_clock_data = { 1981 .base = RCC_BASE, 1982 .num = ARRAY_SIZE(stm32mp13_clk), 1983 .clks = stm32mp13_clk, 1984 .parents = parent_mp13, 1985 .nb_parents = ARRAY_SIZE(parent_mp13), 1986 .gates = gates_mp13, 1987 .nb_gates = ARRAY_SIZE(gates_mp13), 1988 .div = dividers_mp13, 1989 .nb_div = ARRAY_SIZE(dividers_mp13), 1990 .osci_data = stm32mp13_osc_data, 1991 .nb_osci_data = ARRAY_SIZE(stm32mp13_osc_data), 1992 .gate_refcounts = refcounts_mp13, 1993 .pdata = &stm32mp13_clock_pdata, 1994 }; 1995 1996 static int stm32mp1_init_clock_tree(void) 1997 { 1998 struct stm32_clk_priv *priv = clk_stm32_get_priv(); 1999 int ret; 2000 2001 #if STM32MP_USB_PROGRAMMER 2002 int usbphy_p = _clk_stm32_get_parent(priv, _USBPHY_K); 2003 int usbo_p = _clk_stm32_get_parent(priv, _USBO_K); 2004 2005 /* Don't initialize PLL4, when used by BOOTROM */ 2006 pll4_bootrom = stm32mp1_clk_is_pll4_used_by_bootrom(priv, usbphy_p); 2007 #endif 2008 2009 /* 2010 * Switch ON oscillators found in device-tree. 2011 * Note: HSI already ON after BootROM stage. 2012 */ 2013 stm32_clk_oscillators_enable(priv); 2014 2015 /* Come back to HSI */ 2016 ret = stm32mp1_come_back_to_hsi(); 2017 if (ret != 0) { 2018 return ret; 2019 } 2020 2021 ret = stm32_clk_hsidiv_configure(priv); 2022 if (ret != 0) { 2023 return ret; 2024 } 2025 2026 ret = stm32_clk_stgen_configure(priv, _STGENC); 2027 if (ret != 0) { 2028 panic(); 2029 } 2030 2031 ret = stm32_clk_dividers_configure(priv); 2032 if (ret != 0) { 2033 panic(); 2034 } 2035 2036 ret = stm32_clk_pll_configure(priv); 2037 if (ret != 0) { 2038 panic(); 2039 } 2040 2041 /* Wait LSE ready before to use it */ 2042 ret = stm32_clk_oscillators_wait_lse_ready(priv); 2043 if (ret != 0) { 2044 panic(); 2045 } 2046 2047 /* Configure with expected clock source */ 2048 ret = stm32_clk_source_configure(priv); 2049 if (ret != 0) { 2050 panic(); 2051 } 2052 2053 /* Configure LSE css after RTC source configuration */ 2054 ret = stm32_clk_oscillators_lse_set_css(priv); 2055 if (ret != 0) { 2056 panic(); 2057 } 2058 2059 #if STM32MP_USB_PROGRAMMER 2060 ret = stm32mp1_clk_check_usb_conflict(priv, usbphy_p, usbo_p); 2061 if (ret != 0) { 2062 return ret; 2063 } 2064 #endif 2065 /* reconfigure STGEN with DT config */ 2066 ret = stm32_clk_stgen_configure(priv, _STGENC); 2067 if (ret != 0) { 2068 panic(); 2069 } 2070 2071 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2072 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, 2073 RCC_DDRITFCR_DDRCKMOD_MASK, 2074 RCC_DDRITFCR_DDRCKMOD_SSR << 2075 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2076 2077 return 0; 2078 } 2079 2080 static int clk_stm32_parse_oscillator_fdt(void *fdt, int node, const char *name, 2081 struct stm32_osci_dt_cfg *osci) 2082 { 2083 int subnode = 0; 2084 2085 /* default value oscillator not found, freq=0 */ 2086 osci->freq = 0; 2087 2088 fdt_for_each_subnode(subnode, fdt, node) { 2089 const char *cchar = NULL; 2090 const fdt32_t *cuint = NULL; 2091 int ret = 0; 2092 2093 cchar = fdt_get_name(fdt, subnode, &ret); 2094 if (cchar == NULL) { 2095 return ret; 2096 } 2097 2098 if (strncmp(cchar, name, (size_t)ret) || 2099 fdt_get_status(subnode) == DT_DISABLED) { 2100 continue; 2101 } 2102 2103 cuint = fdt_getprop(fdt, subnode, "clock-frequency", &ret); 2104 if (cuint == NULL) { 2105 return ret; 2106 } 2107 2108 osci->freq = fdt32_to_cpu(*cuint); 2109 2110 if (fdt_getprop(fdt, subnode, "st,bypass", NULL) != NULL) { 2111 osci->bypass = true; 2112 } 2113 2114 if (fdt_getprop(fdt, subnode, "st,digbypass", NULL) != NULL) { 2115 osci->digbyp = true; 2116 } 2117 2118 if (fdt_getprop(fdt, subnode, "st,css", NULL) != NULL) { 2119 osci->css = true; 2120 } 2121 2122 osci->drive = fdt_read_uint32_default(fdt, subnode, "st,drive", LSEDRV_MEDIUM_HIGH); 2123 2124 return 0; 2125 } 2126 2127 return 0; 2128 } 2129 2130 static int stm32_clk_parse_fdt_all_oscillator(void *fdt, struct stm32_clk_platdata *pdata) 2131 { 2132 int fdt_err = 0; 2133 uint32_t i = 0; 2134 int node = 0; 2135 2136 node = fdt_path_offset(fdt, "/clocks"); 2137 if (node < 0) { 2138 return -FDT_ERR_NOTFOUND; 2139 } 2140 2141 for (i = 0; i < pdata->nosci; i++) { 2142 const char *name = NULL; 2143 2144 name = clk_stm32_get_oscillator_name((enum stm32_osc)i); 2145 if (name == NULL) { 2146 continue; 2147 } 2148 2149 fdt_err = clk_stm32_parse_oscillator_fdt(fdt, node, name, &pdata->osci[i]); 2150 if (fdt_err < 0) { 2151 panic(); 2152 } 2153 } 2154 2155 return 0; 2156 } 2157 2158 #define RCC_PLL_NAME_SIZE 12 2159 2160 static int clk_stm32_load_vco_config(void *fdt, int subnode, struct stm32_pll_vco *vco) 2161 { 2162 int err = 0; 2163 2164 err = fdt_read_uint32_array(fdt, subnode, "divmn", (int)PLL_DIV_MN_NB, vco->div_mn); 2165 if (err != 0) { 2166 return err; 2167 } 2168 2169 err = fdt_read_uint32_array(fdt, subnode, "csg", (int)PLL_CSG_NB, vco->csg); 2170 2171 vco->csg_enabled = (err == 0); 2172 2173 if (err == -FDT_ERR_NOTFOUND) { 2174 err = 0; 2175 } 2176 2177 if (err != 0) { 2178 return err; 2179 } 2180 2181 vco->status = RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | RCC_PLLNCR_DIVREN | RCC_PLLNCR_PLLON; 2182 2183 vco->frac = fdt_read_uint32_default(fdt, subnode, "frac", 0); 2184 2185 vco->src = fdt_read_uint32_default(fdt, subnode, "src", UINT32_MAX); 2186 2187 return 0; 2188 } 2189 2190 static int clk_stm32_load_output_config(void *fdt, int subnode, struct stm32_pll_output *output) 2191 { 2192 int err = 0; 2193 2194 err = fdt_read_uint32_array(fdt, subnode, "st,pll_div_pqr", (int)PLL_DIV_PQR_NB, 2195 output->output); 2196 if (err != 0) { 2197 return err; 2198 } 2199 2200 return 0; 2201 } 2202 2203 static int clk_stm32_parse_pll_fdt(void *fdt, int subnode, struct stm32_pll_dt_cfg *pll) 2204 { 2205 const fdt32_t *cuint = NULL; 2206 int subnode_pll = 0; 2207 int subnode_vco = 0; 2208 int err = 0; 2209 2210 cuint = fdt_getprop(fdt, subnode, "st,pll", NULL); 2211 if (!cuint) { 2212 return -FDT_ERR_NOTFOUND; 2213 } 2214 2215 subnode_pll = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2216 if (subnode_pll < 0) { 2217 return -FDT_ERR_NOTFOUND; 2218 } 2219 2220 cuint = fdt_getprop(fdt, subnode_pll, "st,pll_vco", NULL); 2221 if (!cuint) { 2222 return -FDT_ERR_NOTFOUND; 2223 } 2224 2225 subnode_vco = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*cuint)); 2226 if (subnode_vco < 0) { 2227 return -FDT_ERR_NOTFOUND; 2228 } 2229 2230 err = clk_stm32_load_vco_config(fdt, subnode_vco, &pll->vco); 2231 if (err != 0) { 2232 return err; 2233 } 2234 2235 err = clk_stm32_load_output_config(fdt, subnode_pll, &pll->output); 2236 if (err != 0) { 2237 return err; 2238 } 2239 2240 return 0; 2241 } 2242 2243 static int stm32_clk_parse_fdt_all_pll(void *fdt, int node, struct stm32_clk_platdata *pdata) 2244 { 2245 size_t i = 0U; 2246 2247 for (i = _PLL1; i < pdata->npll; i++) { 2248 struct stm32_pll_dt_cfg *pll = &pdata->pll[i]; 2249 char name[RCC_PLL_NAME_SIZE]; 2250 int subnode = 0; 2251 int err = 0; 2252 2253 snprintf(name, sizeof(name), "st,pll@%u", i); 2254 2255 subnode = fdt_subnode_offset(fdt, node, name); 2256 if (!fdt_check_node(subnode)) { 2257 continue; 2258 } 2259 2260 err = clk_stm32_parse_pll_fdt(fdt, subnode, pll); 2261 if (err != 0) { 2262 panic(); 2263 } 2264 } 2265 2266 return 0; 2267 } 2268 2269 static int stm32_clk_parse_fdt(struct stm32_clk_platdata *pdata) 2270 { 2271 void *fdt = NULL; 2272 int node; 2273 uint32_t err; 2274 2275 if (fdt_get_address(&fdt) == 0) { 2276 return -ENOENT; 2277 } 2278 2279 node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT); 2280 if (node < 0) { 2281 panic(); 2282 } 2283 2284 err = stm32_clk_parse_fdt_all_oscillator(fdt, pdata); 2285 if (err != 0) { 2286 return err; 2287 } 2288 2289 err = stm32_clk_parse_fdt_all_pll(fdt, node, pdata); 2290 if (err != 0) { 2291 return err; 2292 } 2293 2294 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clkdiv", pdata->clkdiv, &pdata->nclkdiv); 2295 if (err != 0) { 2296 return err; 2297 } 2298 2299 err = stm32_clk_parse_fdt_by_name(fdt, node, "st,clksrc", pdata->clksrc, &pdata->nclksrc); 2300 if (err != 0) { 2301 return err; 2302 } 2303 2304 return 0; 2305 } 2306 2307 int stm32mp1_clk_init(void) 2308 { 2309 return 0; 2310 } 2311 2312 int stm32mp1_clk_probe(void) 2313 { 2314 uintptr_t base = RCC_BASE; 2315 int ret; 2316 2317 ret = stm32_clk_parse_fdt(&stm32mp13_clock_pdata); 2318 if (ret != 0) { 2319 return ret; 2320 } 2321 2322 ret = clk_stm32_init(&stm32mp13_clock_data, base); 2323 if (ret != 0) { 2324 return ret; 2325 } 2326 2327 ret = stm32mp1_init_clock_tree(); 2328 if (ret != 0) { 2329 return ret; 2330 } 2331 2332 clk_stm32_enable_critical_clocks(); 2333 2334 return 0; 2335 } 2336