1 /* 2 * Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <stdint.h> 10 #include <stdio.h> 11 12 #include <arch.h> 13 #include <arch_helpers.h> 14 #include <common/debug.h> 15 #include <common/fdt_wrappers.h> 16 #include <drivers/clk.h> 17 #include <drivers/delay_timer.h> 18 #include <drivers/st/stm32mp_clkfunc.h> 19 #include <drivers/st/stm32mp1_clk.h> 20 #include <drivers/st/stm32mp1_rcc.h> 21 #include <dt-bindings/clock/stm32mp1-clksrc.h> 22 #include <lib/mmio.h> 23 #include <lib/spinlock.h> 24 #include <lib/utils_def.h> 25 #include <libfdt.h> 26 #include <plat/common/platform.h> 27 28 #include <platform_def.h> 29 30 #define MAX_HSI_HZ 64000000 31 #define USB_PHY_48_MHZ 48000000 32 33 #define TIMEOUT_US_200MS U(200000) 34 #define TIMEOUT_US_1S U(1000000) 35 36 #define PLLRDY_TIMEOUT TIMEOUT_US_200MS 37 #define CLKSRC_TIMEOUT TIMEOUT_US_200MS 38 #define CLKDIV_TIMEOUT TIMEOUT_US_200MS 39 #define HSIDIV_TIMEOUT TIMEOUT_US_200MS 40 #define OSCRDY_TIMEOUT TIMEOUT_US_1S 41 42 const char *stm32mp_osc_node_label[NB_OSC] = { 43 [_LSI] = "clk-lsi", 44 [_LSE] = "clk-lse", 45 [_HSI] = "clk-hsi", 46 [_HSE] = "clk-hse", 47 [_CSI] = "clk-csi", 48 [_I2S_CKIN] = "i2s_ckin", 49 }; 50 51 enum stm32mp1_parent_id { 52 /* Oscillators are defined in enum stm32mp_osc_id */ 53 54 /* Other parent source */ 55 _HSI_KER = NB_OSC, 56 _HSE_KER, 57 _HSE_KER_DIV2, 58 _HSE_RTC, 59 _CSI_KER, 60 _PLL1_P, 61 _PLL1_Q, 62 _PLL1_R, 63 _PLL2_P, 64 _PLL2_Q, 65 _PLL2_R, 66 _PLL3_P, 67 _PLL3_Q, 68 _PLL3_R, 69 _PLL4_P, 70 _PLL4_Q, 71 _PLL4_R, 72 _ACLK, 73 _PCLK1, 74 _PCLK2, 75 _PCLK3, 76 _PCLK4, 77 _PCLK5, 78 _HCLK6, 79 _HCLK2, 80 _CK_PER, 81 _CK_MPU, 82 _CK_MCU, 83 _USB_PHY_48, 84 _PARENT_NB, 85 _UNKNOWN_ID = 0xff, 86 }; 87 88 /* Lists only the parent clock we are interested in */ 89 enum stm32mp1_parent_sel { 90 _I2C12_SEL, 91 _I2C35_SEL, 92 _STGEN_SEL, 93 _I2C46_SEL, 94 _SPI6_SEL, 95 _UART1_SEL, 96 _RNG1_SEL, 97 _UART6_SEL, 98 _UART24_SEL, 99 _UART35_SEL, 100 _UART78_SEL, 101 _SDMMC12_SEL, 102 _SDMMC3_SEL, 103 _QSPI_SEL, 104 _FMC_SEL, 105 _AXIS_SEL, 106 _MCUS_SEL, 107 _USBPHY_SEL, 108 _USBO_SEL, 109 _MPU_SEL, 110 _CKPER_SEL, 111 _RTC_SEL, 112 _PARENT_SEL_NB, 113 _UNKNOWN_SEL = 0xff, 114 }; 115 116 /* State the parent clock ID straight related to a clock */ 117 static const uint8_t parent_id_clock_id[_PARENT_NB] = { 118 [_HSE] = CK_HSE, 119 [_HSI] = CK_HSI, 120 [_CSI] = CK_CSI, 121 [_LSE] = CK_LSE, 122 [_LSI] = CK_LSI, 123 [_I2S_CKIN] = _UNKNOWN_ID, 124 [_USB_PHY_48] = _UNKNOWN_ID, 125 [_HSI_KER] = CK_HSI, 126 [_HSE_KER] = CK_HSE, 127 [_HSE_KER_DIV2] = CK_HSE_DIV2, 128 [_HSE_RTC] = _UNKNOWN_ID, 129 [_CSI_KER] = CK_CSI, 130 [_PLL1_P] = PLL1_P, 131 [_PLL1_Q] = PLL1_Q, 132 [_PLL1_R] = PLL1_R, 133 [_PLL2_P] = PLL2_P, 134 [_PLL2_Q] = PLL2_Q, 135 [_PLL2_R] = PLL2_R, 136 [_PLL3_P] = PLL3_P, 137 [_PLL3_Q] = PLL3_Q, 138 [_PLL3_R] = PLL3_R, 139 [_PLL4_P] = PLL4_P, 140 [_PLL4_Q] = PLL4_Q, 141 [_PLL4_R] = PLL4_R, 142 [_ACLK] = CK_AXI, 143 [_PCLK1] = CK_AXI, 144 [_PCLK2] = CK_AXI, 145 [_PCLK3] = CK_AXI, 146 [_PCLK4] = CK_AXI, 147 [_PCLK5] = CK_AXI, 148 [_CK_PER] = CK_PER, 149 [_CK_MPU] = CK_MPU, 150 [_CK_MCU] = CK_MCU, 151 }; 152 153 static unsigned int clock_id2parent_id(unsigned long id) 154 { 155 unsigned int n; 156 157 for (n = 0U; n < ARRAY_SIZE(parent_id_clock_id); n++) { 158 if (parent_id_clock_id[n] == id) { 159 return n; 160 } 161 } 162 163 return _UNKNOWN_ID; 164 } 165 166 enum stm32mp1_pll_id { 167 _PLL1, 168 _PLL2, 169 _PLL3, 170 _PLL4, 171 _PLL_NB 172 }; 173 174 enum stm32mp1_div_id { 175 _DIV_P, 176 _DIV_Q, 177 _DIV_R, 178 _DIV_NB, 179 }; 180 181 enum stm32mp1_clksrc_id { 182 CLKSRC_MPU, 183 CLKSRC_AXI, 184 CLKSRC_MCU, 185 CLKSRC_PLL12, 186 CLKSRC_PLL3, 187 CLKSRC_PLL4, 188 CLKSRC_RTC, 189 CLKSRC_MCO1, 190 CLKSRC_MCO2, 191 CLKSRC_NB 192 }; 193 194 enum stm32mp1_clkdiv_id { 195 CLKDIV_MPU, 196 CLKDIV_AXI, 197 CLKDIV_MCU, 198 CLKDIV_APB1, 199 CLKDIV_APB2, 200 CLKDIV_APB3, 201 CLKDIV_APB4, 202 CLKDIV_APB5, 203 CLKDIV_RTC, 204 CLKDIV_MCO1, 205 CLKDIV_MCO2, 206 CLKDIV_NB 207 }; 208 209 enum stm32mp1_pllcfg { 210 PLLCFG_M, 211 PLLCFG_N, 212 PLLCFG_P, 213 PLLCFG_Q, 214 PLLCFG_R, 215 PLLCFG_O, 216 PLLCFG_NB 217 }; 218 219 enum stm32mp1_pllcsg { 220 PLLCSG_MOD_PER, 221 PLLCSG_INC_STEP, 222 PLLCSG_SSCG_MODE, 223 PLLCSG_NB 224 }; 225 226 enum stm32mp1_plltype { 227 PLL_800, 228 PLL_1600, 229 PLL_TYPE_NB 230 }; 231 232 struct stm32mp1_pll { 233 uint8_t refclk_min; 234 uint8_t refclk_max; 235 }; 236 237 struct stm32mp1_clk_gate { 238 uint16_t offset; 239 uint8_t bit; 240 uint8_t index; 241 uint8_t set_clr; 242 uint8_t secure; 243 uint8_t sel; /* Relates to enum stm32mp1_parent_sel */ 244 uint8_t fixed; /* Relates to enum stm32mp1_parent_id */ 245 }; 246 247 struct stm32mp1_clk_sel { 248 uint16_t offset; 249 uint8_t src; 250 uint8_t msk; 251 uint8_t nb_parent; 252 const uint8_t *parent; 253 }; 254 255 #define REFCLK_SIZE 4 256 struct stm32mp1_clk_pll { 257 enum stm32mp1_plltype plltype; 258 uint16_t rckxselr; 259 uint16_t pllxcfgr1; 260 uint16_t pllxcfgr2; 261 uint16_t pllxfracr; 262 uint16_t pllxcr; 263 uint16_t pllxcsgr; 264 enum stm32mp_osc_id refclk[REFCLK_SIZE]; 265 }; 266 267 /* Clocks with selectable source and non set/clr register access */ 268 #define _CLK_SELEC(sec, off, b, idx, s) \ 269 { \ 270 .offset = (off), \ 271 .bit = (b), \ 272 .index = (idx), \ 273 .set_clr = 0, \ 274 .secure = (sec), \ 275 .sel = (s), \ 276 .fixed = _UNKNOWN_ID, \ 277 } 278 279 /* Clocks with fixed source and non set/clr register access */ 280 #define _CLK_FIXED(sec, off, b, idx, f) \ 281 { \ 282 .offset = (off), \ 283 .bit = (b), \ 284 .index = (idx), \ 285 .set_clr = 0, \ 286 .secure = (sec), \ 287 .sel = _UNKNOWN_SEL, \ 288 .fixed = (f), \ 289 } 290 291 /* Clocks with selectable source and set/clr register access */ 292 #define _CLK_SC_SELEC(sec, off, b, idx, s) \ 293 { \ 294 .offset = (off), \ 295 .bit = (b), \ 296 .index = (idx), \ 297 .set_clr = 1, \ 298 .secure = (sec), \ 299 .sel = (s), \ 300 .fixed = _UNKNOWN_ID, \ 301 } 302 303 /* Clocks with fixed source and set/clr register access */ 304 #define _CLK_SC_FIXED(sec, off, b, idx, f) \ 305 { \ 306 .offset = (off), \ 307 .bit = (b), \ 308 .index = (idx), \ 309 .set_clr = 1, \ 310 .secure = (sec), \ 311 .sel = _UNKNOWN_SEL, \ 312 .fixed = (f), \ 313 } 314 315 #define _CLK_PARENT_SEL(_label, _rcc_selr, _parents) \ 316 [_ ## _label ## _SEL] = { \ 317 .offset = _rcc_selr, \ 318 .src = _rcc_selr ## _ ## _label ## SRC_SHIFT, \ 319 .msk = (_rcc_selr ## _ ## _label ## SRC_MASK) >> \ 320 (_rcc_selr ## _ ## _label ## SRC_SHIFT), \ 321 .parent = (_parents), \ 322 .nb_parent = ARRAY_SIZE(_parents) \ 323 } 324 325 #define _CLK_PLL(idx, type, off1, off2, off3, \ 326 off4, off5, off6, \ 327 p1, p2, p3, p4) \ 328 [(idx)] = { \ 329 .plltype = (type), \ 330 .rckxselr = (off1), \ 331 .pllxcfgr1 = (off2), \ 332 .pllxcfgr2 = (off3), \ 333 .pllxfracr = (off4), \ 334 .pllxcr = (off5), \ 335 .pllxcsgr = (off6), \ 336 .refclk[0] = (p1), \ 337 .refclk[1] = (p2), \ 338 .refclk[2] = (p3), \ 339 .refclk[3] = (p4), \ 340 } 341 342 #define NB_GATES ARRAY_SIZE(stm32mp1_clk_gate) 343 344 #define SEC 1 345 #define N_S 0 346 347 static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { 348 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK), 349 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK), 350 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK), 351 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK), 352 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R), 353 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R), 354 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4), 355 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4), 356 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK), 357 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4), 358 _CLK_FIXED(SEC, RCC_DDRITFCR, 10, DDRPHYCAPBLP, _PCLK4), 359 360 #if defined(IMAGE_BL32) 361 _CLK_SC_FIXED(N_S, RCC_MP_APB1ENSETR, 6, TIM12_K, _PCLK1), 362 #endif 363 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 14, USART2_K, _UART24_SEL), 364 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 15, USART3_K, _UART35_SEL), 365 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 16, UART4_K, _UART24_SEL), 366 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 17, UART5_K, _UART35_SEL), 367 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 18, UART7_K, _UART78_SEL), 368 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 19, UART8_K, _UART78_SEL), 369 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 21, I2C1_K, _I2C12_SEL), 370 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 22, I2C2_K, _I2C12_SEL), 371 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 23, I2C3_K, _I2C35_SEL), 372 _CLK_SC_SELEC(N_S, RCC_MP_APB1ENSETR, 24, I2C5_K, _I2C35_SEL), 373 374 #if defined(IMAGE_BL32) 375 _CLK_SC_FIXED(N_S, RCC_MP_APB2ENSETR, 2, TIM15_K, _PCLK2), 376 #endif 377 _CLK_SC_SELEC(N_S, RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL), 378 379 _CLK_SC_FIXED(N_S, RCC_MP_APB3ENSETR, 11, SYSCFG, _UNKNOWN_ID), 380 381 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL), 382 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL), 383 _CLK_SC_SELEC(N_S, RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL), 384 385 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 0, SPI6_K, _SPI6_SEL), 386 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 2, I2C4_K, _I2C46_SEL), 387 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 3, I2C6_K, _I2C46_SEL), 388 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 4, USART1_K, _UART1_SEL), 389 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 8, RTCAPB, _PCLK5), 390 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 11, TZC1, _PCLK5), 391 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 12, TZC2, _PCLK5), 392 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 13, TZPC, _PCLK5), 393 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 15, IWDG1, _PCLK5), 394 _CLK_SC_FIXED(SEC, RCC_MP_APB5ENSETR, 16, BSEC, _PCLK5), 395 _CLK_SC_SELEC(SEC, RCC_MP_APB5ENSETR, 20, STGEN_K, _STGEN_SEL), 396 397 #if defined(IMAGE_BL32) 398 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL), 399 _CLK_SC_SELEC(N_S, RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), 400 #endif 401 402 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), 403 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL), 404 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL), 405 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 3, GPIOD, _UNKNOWN_SEL), 406 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 4, GPIOE, _UNKNOWN_SEL), 407 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 5, GPIOF, _UNKNOWN_SEL), 408 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 6, GPIOG, _UNKNOWN_SEL), 409 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 7, GPIOH, _UNKNOWN_SEL), 410 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 8, GPIOI, _UNKNOWN_SEL), 411 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 9, GPIOJ, _UNKNOWN_SEL), 412 _CLK_SC_SELEC(N_S, RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL), 413 414 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 0, GPIOZ, _PCLK5), 415 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 4, CRYP1, _PCLK5), 416 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 5, HASH1, _PCLK5), 417 _CLK_SC_SELEC(SEC, RCC_MP_AHB5ENSETR, 6, RNG1_K, _RNG1_SEL), 418 _CLK_SC_FIXED(SEC, RCC_MP_AHB5ENSETR, 8, BKPSRAM, _PCLK5), 419 420 #if defined(IMAGE_BL2) 421 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 12, FMC_K, _FMC_SEL), 422 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 14, QSPI_K, _QSPI_SEL), 423 #endif 424 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 16, SDMMC1_K, _SDMMC12_SEL), 425 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 17, SDMMC2_K, _SDMMC12_SEL), 426 #if defined(IMAGE_BL32) 427 _CLK_SC_SELEC(N_S, RCC_MP_AHB6ENSETR, 24, USBH, _UNKNOWN_SEL), 428 #endif 429 430 _CLK_SELEC(SEC, RCC_BDCR, 20, RTC, _RTC_SEL), 431 _CLK_SELEC(N_S, RCC_DBGCFGR, 8, CK_DBG, _UNKNOWN_SEL), 432 }; 433 434 static const uint8_t i2c12_parents[] = { 435 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 436 }; 437 438 static const uint8_t i2c35_parents[] = { 439 _PCLK1, _PLL4_R, _HSI_KER, _CSI_KER 440 }; 441 442 static const uint8_t stgen_parents[] = { 443 _HSI_KER, _HSE_KER 444 }; 445 446 static const uint8_t i2c46_parents[] = { 447 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER 448 }; 449 450 static const uint8_t spi6_parents[] = { 451 _PCLK5, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER, _PLL3_Q 452 }; 453 454 static const uint8_t usart1_parents[] = { 455 _PCLK5, _PLL3_Q, _HSI_KER, _CSI_KER, _PLL4_Q, _HSE_KER 456 }; 457 458 static const uint8_t rng1_parents[] = { 459 _CSI, _PLL4_R, _LSE, _LSI 460 }; 461 462 static const uint8_t uart6_parents[] = { 463 _PCLK2, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 464 }; 465 466 static const uint8_t uart234578_parents[] = { 467 _PCLK1, _PLL4_Q, _HSI_KER, _CSI_KER, _HSE_KER 468 }; 469 470 static const uint8_t sdmmc12_parents[] = { 471 _HCLK6, _PLL3_R, _PLL4_P, _HSI_KER 472 }; 473 474 static const uint8_t sdmmc3_parents[] = { 475 _HCLK2, _PLL3_R, _PLL4_P, _HSI_KER 476 }; 477 478 static const uint8_t qspi_parents[] = { 479 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 480 }; 481 482 static const uint8_t fmc_parents[] = { 483 _ACLK, _PLL3_R, _PLL4_P, _CK_PER 484 }; 485 486 static const uint8_t axiss_parents[] = { 487 _HSI, _HSE, _PLL2_P 488 }; 489 490 static const uint8_t mcuss_parents[] = { 491 _HSI, _HSE, _CSI, _PLL3_P 492 }; 493 494 static const uint8_t usbphy_parents[] = { 495 _HSE_KER, _PLL4_R, _HSE_KER_DIV2 496 }; 497 498 static const uint8_t usbo_parents[] = { 499 _PLL4_R, _USB_PHY_48 500 }; 501 502 static const uint8_t mpu_parents[] = { 503 _HSI, _HSE, _PLL1_P, _PLL1_P /* specific div */ 504 }; 505 506 static const uint8_t per_parents[] = { 507 _HSI, _HSE, _CSI, 508 }; 509 510 static const uint8_t rtc_parents[] = { 511 _UNKNOWN_ID, _LSE, _LSI, _HSE_RTC 512 }; 513 514 static const struct stm32mp1_clk_sel stm32mp1_clk_sel[_PARENT_SEL_NB] = { 515 _CLK_PARENT_SEL(I2C12, RCC_I2C12CKSELR, i2c12_parents), 516 _CLK_PARENT_SEL(I2C35, RCC_I2C35CKSELR, i2c35_parents), 517 _CLK_PARENT_SEL(STGEN, RCC_STGENCKSELR, stgen_parents), 518 _CLK_PARENT_SEL(I2C46, RCC_I2C46CKSELR, i2c46_parents), 519 _CLK_PARENT_SEL(SPI6, RCC_SPI6CKSELR, spi6_parents), 520 _CLK_PARENT_SEL(UART1, RCC_UART1CKSELR, usart1_parents), 521 _CLK_PARENT_SEL(RNG1, RCC_RNG1CKSELR, rng1_parents), 522 _CLK_PARENT_SEL(MPU, RCC_MPCKSELR, mpu_parents), 523 _CLK_PARENT_SEL(CKPER, RCC_CPERCKSELR, per_parents), 524 _CLK_PARENT_SEL(RTC, RCC_BDCR, rtc_parents), 525 _CLK_PARENT_SEL(UART6, RCC_UART6CKSELR, uart6_parents), 526 _CLK_PARENT_SEL(UART24, RCC_UART24CKSELR, uart234578_parents), 527 _CLK_PARENT_SEL(UART35, RCC_UART35CKSELR, uart234578_parents), 528 _CLK_PARENT_SEL(UART78, RCC_UART78CKSELR, uart234578_parents), 529 _CLK_PARENT_SEL(SDMMC12, RCC_SDMMC12CKSELR, sdmmc12_parents), 530 _CLK_PARENT_SEL(SDMMC3, RCC_SDMMC3CKSELR, sdmmc3_parents), 531 _CLK_PARENT_SEL(QSPI, RCC_QSPICKSELR, qspi_parents), 532 _CLK_PARENT_SEL(FMC, RCC_FMCCKSELR, fmc_parents), 533 _CLK_PARENT_SEL(AXIS, RCC_ASSCKSELR, axiss_parents), 534 _CLK_PARENT_SEL(MCUS, RCC_MSSCKSELR, mcuss_parents), 535 _CLK_PARENT_SEL(USBPHY, RCC_USBCKSELR, usbphy_parents), 536 _CLK_PARENT_SEL(USBO, RCC_USBCKSELR, usbo_parents), 537 }; 538 539 /* Define characteristic of PLL according type */ 540 #define POST_DIVM_MIN 8000000U 541 #define POST_DIVM_MAX 16000000U 542 #define DIVM_MIN 0U 543 #define DIVM_MAX 63U 544 #define DIVN_MIN 24U 545 #define DIVN_MAX 99U 546 #define DIVP_MIN 0U 547 #define DIVP_MAX 127U 548 #define FRAC_MAX 8192U 549 #define VCO_MIN 800000000U 550 #define VCO_MAX 1600000000U 551 552 static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = { 553 [PLL_800] = { 554 .refclk_min = 4, 555 .refclk_max = 16, 556 }, 557 [PLL_1600] = { 558 .refclk_min = 8, 559 .refclk_max = 16, 560 }, 561 }; 562 563 /* PLLNCFGR2 register divider by output */ 564 static const uint8_t pllncfgr2[_DIV_NB] = { 565 [_DIV_P] = RCC_PLLNCFGR2_DIVP_SHIFT, 566 [_DIV_Q] = RCC_PLLNCFGR2_DIVQ_SHIFT, 567 [_DIV_R] = RCC_PLLNCFGR2_DIVR_SHIFT, 568 }; 569 570 static const struct stm32mp1_clk_pll stm32mp1_clk_pll[_PLL_NB] = { 571 _CLK_PLL(_PLL1, PLL_1600, 572 RCC_RCK12SELR, RCC_PLL1CFGR1, RCC_PLL1CFGR2, 573 RCC_PLL1FRACR, RCC_PLL1CR, RCC_PLL1CSGR, 574 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 575 _CLK_PLL(_PLL2, PLL_1600, 576 RCC_RCK12SELR, RCC_PLL2CFGR1, RCC_PLL2CFGR2, 577 RCC_PLL2FRACR, RCC_PLL2CR, RCC_PLL2CSGR, 578 _HSI, _HSE, _UNKNOWN_OSC_ID, _UNKNOWN_OSC_ID), 579 _CLK_PLL(_PLL3, PLL_800, 580 RCC_RCK3SELR, RCC_PLL3CFGR1, RCC_PLL3CFGR2, 581 RCC_PLL3FRACR, RCC_PLL3CR, RCC_PLL3CSGR, 582 _HSI, _HSE, _CSI, _UNKNOWN_OSC_ID), 583 _CLK_PLL(_PLL4, PLL_800, 584 RCC_RCK4SELR, RCC_PLL4CFGR1, RCC_PLL4CFGR2, 585 RCC_PLL4FRACR, RCC_PLL4CR, RCC_PLL4CSGR, 586 _HSI, _HSE, _CSI, _I2S_CKIN), 587 }; 588 589 /* Prescaler table lookups for clock computation */ 590 /* div = /1 /2 /4 /8 / 16 /64 /128 /512 */ 591 static const uint8_t stm32mp1_mcu_div[16] = { 592 0, 1, 2, 3, 4, 6, 7, 8, 9, 9, 9, 9, 9, 9, 9, 9 593 }; 594 595 /* div = /1 /2 /4 /8 /16 : same divider for PMU and APBX */ 596 #define stm32mp1_mpu_div stm32mp1_mpu_apbx_div 597 #define stm32mp1_apbx_div stm32mp1_mpu_apbx_div 598 static const uint8_t stm32mp1_mpu_apbx_div[8] = { 599 0, 1, 2, 3, 4, 4, 4, 4 600 }; 601 602 /* div = /1 /2 /3 /4 */ 603 static const uint8_t stm32mp1_axi_div[8] = { 604 1, 2, 3, 4, 4, 4, 4, 4 605 }; 606 607 static const char * const stm32mp1_clk_parent_name[_PARENT_NB] __unused = { 608 [_HSI] = "HSI", 609 [_HSE] = "HSE", 610 [_CSI] = "CSI", 611 [_LSI] = "LSI", 612 [_LSE] = "LSE", 613 [_I2S_CKIN] = "I2S_CKIN", 614 [_HSI_KER] = "HSI_KER", 615 [_HSE_KER] = "HSE_KER", 616 [_HSE_KER_DIV2] = "HSE_KER_DIV2", 617 [_HSE_RTC] = "HSE_RTC", 618 [_CSI_KER] = "CSI_KER", 619 [_PLL1_P] = "PLL1_P", 620 [_PLL1_Q] = "PLL1_Q", 621 [_PLL1_R] = "PLL1_R", 622 [_PLL2_P] = "PLL2_P", 623 [_PLL2_Q] = "PLL2_Q", 624 [_PLL2_R] = "PLL2_R", 625 [_PLL3_P] = "PLL3_P", 626 [_PLL3_Q] = "PLL3_Q", 627 [_PLL3_R] = "PLL3_R", 628 [_PLL4_P] = "PLL4_P", 629 [_PLL4_Q] = "PLL4_Q", 630 [_PLL4_R] = "PLL4_R", 631 [_ACLK] = "ACLK", 632 [_PCLK1] = "PCLK1", 633 [_PCLK2] = "PCLK2", 634 [_PCLK3] = "PCLK3", 635 [_PCLK4] = "PCLK4", 636 [_PCLK5] = "PCLK5", 637 [_HCLK6] = "KCLK6", 638 [_HCLK2] = "HCLK2", 639 [_CK_PER] = "CK_PER", 640 [_CK_MPU] = "CK_MPU", 641 [_CK_MCU] = "CK_MCU", 642 [_USB_PHY_48] = "USB_PHY_48", 643 }; 644 645 /* RCC clock device driver private */ 646 static unsigned long stm32mp1_osc[NB_OSC]; 647 static struct spinlock reg_lock; 648 static unsigned int gate_refcounts[NB_GATES]; 649 static struct spinlock refcount_lock; 650 651 static const struct stm32mp1_clk_gate *gate_ref(unsigned int idx) 652 { 653 return &stm32mp1_clk_gate[idx]; 654 } 655 656 #if defined(IMAGE_BL32) 657 static bool gate_is_non_secure(const struct stm32mp1_clk_gate *gate) 658 { 659 return gate->secure == N_S; 660 } 661 #endif 662 663 static const struct stm32mp1_clk_sel *clk_sel_ref(unsigned int idx) 664 { 665 return &stm32mp1_clk_sel[idx]; 666 } 667 668 static const struct stm32mp1_clk_pll *pll_ref(unsigned int idx) 669 { 670 return &stm32mp1_clk_pll[idx]; 671 } 672 673 static void stm32mp1_clk_lock(struct spinlock *lock) 674 { 675 if (stm32mp_lock_available()) { 676 /* Assume interrupts are masked */ 677 spin_lock(lock); 678 } 679 } 680 681 static void stm32mp1_clk_unlock(struct spinlock *lock) 682 { 683 if (stm32mp_lock_available()) { 684 spin_unlock(lock); 685 } 686 } 687 688 bool stm32mp1_rcc_is_secure(void) 689 { 690 uintptr_t rcc_base = stm32mp_rcc_base(); 691 uint32_t mask = RCC_TZCR_TZEN; 692 693 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 694 } 695 696 bool stm32mp1_rcc_is_mckprot(void) 697 { 698 uintptr_t rcc_base = stm32mp_rcc_base(); 699 uint32_t mask = RCC_TZCR_TZEN | RCC_TZCR_MCKPROT; 700 701 return (mmio_read_32(rcc_base + RCC_TZCR) & mask) == mask; 702 } 703 704 void stm32mp1_clk_rcc_regs_lock(void) 705 { 706 stm32mp1_clk_lock(®_lock); 707 } 708 709 void stm32mp1_clk_rcc_regs_unlock(void) 710 { 711 stm32mp1_clk_unlock(®_lock); 712 } 713 714 static unsigned long stm32mp1_clk_get_fixed(enum stm32mp_osc_id idx) 715 { 716 if (idx >= NB_OSC) { 717 return 0; 718 } 719 720 return stm32mp1_osc[idx]; 721 } 722 723 static int stm32mp1_clk_get_gated_id(unsigned long id) 724 { 725 unsigned int i; 726 727 for (i = 0U; i < NB_GATES; i++) { 728 if (gate_ref(i)->index == id) { 729 return i; 730 } 731 } 732 733 ERROR("%s: clk id %lu not found\n", __func__, id); 734 735 return -EINVAL; 736 } 737 738 static enum stm32mp1_parent_sel stm32mp1_clk_get_sel(int i) 739 { 740 return (enum stm32mp1_parent_sel)(gate_ref(i)->sel); 741 } 742 743 static enum stm32mp1_parent_id stm32mp1_clk_get_fixed_parent(int i) 744 { 745 return (enum stm32mp1_parent_id)(gate_ref(i)->fixed); 746 } 747 748 static int stm32mp1_clk_get_parent(unsigned long id) 749 { 750 const struct stm32mp1_clk_sel *sel; 751 uint32_t p_sel; 752 int i; 753 enum stm32mp1_parent_id p; 754 enum stm32mp1_parent_sel s; 755 uintptr_t rcc_base = stm32mp_rcc_base(); 756 757 /* Few non gateable clock have a static parent ID, find them */ 758 i = (int)clock_id2parent_id(id); 759 if (i != _UNKNOWN_ID) { 760 return i; 761 } 762 763 i = stm32mp1_clk_get_gated_id(id); 764 if (i < 0) { 765 panic(); 766 } 767 768 p = stm32mp1_clk_get_fixed_parent(i); 769 if (p < _PARENT_NB) { 770 return (int)p; 771 } 772 773 s = stm32mp1_clk_get_sel(i); 774 if (s == _UNKNOWN_SEL) { 775 return -EINVAL; 776 } 777 if (s >= _PARENT_SEL_NB) { 778 panic(); 779 } 780 781 sel = clk_sel_ref(s); 782 p_sel = (mmio_read_32(rcc_base + sel->offset) & 783 (sel->msk << sel->src)) >> sel->src; 784 if (p_sel < sel->nb_parent) { 785 return (int)sel->parent[p_sel]; 786 } 787 788 return -EINVAL; 789 } 790 791 static unsigned long stm32mp1_pll_get_fref(const struct stm32mp1_clk_pll *pll) 792 { 793 uint32_t selr = mmio_read_32(stm32mp_rcc_base() + pll->rckxselr); 794 uint32_t src = selr & RCC_SELR_REFCLK_SRC_MASK; 795 796 return stm32mp1_clk_get_fixed(pll->refclk[src]); 797 } 798 799 /* 800 * pll_get_fvco() : return the VCO or (VCO / 2) frequency for the requested PLL 801 * - PLL1 & PLL2 => return VCO / 2 with Fpll_y_ck = FVCO / 2 * (DIVy + 1) 802 * - PLL3 & PLL4 => return VCO with Fpll_y_ck = FVCO / (DIVy + 1) 803 * => in all cases Fpll_y_ck = pll_get_fvco() / (DIVy + 1) 804 */ 805 static unsigned long stm32mp1_pll_get_fvco(const struct stm32mp1_clk_pll *pll) 806 { 807 unsigned long refclk, fvco; 808 uint32_t cfgr1, fracr, divm, divn; 809 uintptr_t rcc_base = stm32mp_rcc_base(); 810 811 cfgr1 = mmio_read_32(rcc_base + pll->pllxcfgr1); 812 fracr = mmio_read_32(rcc_base + pll->pllxfracr); 813 814 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; 815 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; 816 817 refclk = stm32mp1_pll_get_fref(pll); 818 819 /* 820 * With FRACV : 821 * Fvco = Fck_ref * ((DIVN + 1) + FRACV / 2^13) / (DIVM + 1) 822 * Without FRACV 823 * Fvco = Fck_ref * ((DIVN + 1) / (DIVM + 1) 824 */ 825 if ((fracr & RCC_PLLNFRACR_FRACLE) != 0U) { 826 uint32_t fracv = (fracr & RCC_PLLNFRACR_FRACV_MASK) >> 827 RCC_PLLNFRACR_FRACV_SHIFT; 828 unsigned long long numerator, denominator; 829 830 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; 831 numerator = refclk * numerator; 832 denominator = ((unsigned long long)divm + 1U) << 13; 833 fvco = (unsigned long)(numerator / denominator); 834 } else { 835 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); 836 } 837 838 return fvco; 839 } 840 841 static unsigned long stm32mp1_read_pll_freq(enum stm32mp1_pll_id pll_id, 842 enum stm32mp1_div_id div_id) 843 { 844 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 845 unsigned long dfout; 846 uint32_t cfgr2, divy; 847 848 if (div_id >= _DIV_NB) { 849 return 0; 850 } 851 852 cfgr2 = mmio_read_32(stm32mp_rcc_base() + pll->pllxcfgr2); 853 divy = (cfgr2 >> pllncfgr2[div_id]) & RCC_PLLNCFGR2_DIVX_MASK; 854 855 dfout = stm32mp1_pll_get_fvco(pll) / (divy + 1U); 856 857 return dfout; 858 } 859 860 static unsigned long get_clock_rate(int p) 861 { 862 uint32_t reg, clkdiv; 863 unsigned long clock = 0; 864 uintptr_t rcc_base = stm32mp_rcc_base(); 865 866 switch (p) { 867 case _CK_MPU: 868 /* MPU sub system */ 869 reg = mmio_read_32(rcc_base + RCC_MPCKSELR); 870 switch (reg & RCC_SELR_SRC_MASK) { 871 case RCC_MPCKSELR_HSI: 872 clock = stm32mp1_clk_get_fixed(_HSI); 873 break; 874 case RCC_MPCKSELR_HSE: 875 clock = stm32mp1_clk_get_fixed(_HSE); 876 break; 877 case RCC_MPCKSELR_PLL: 878 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 879 break; 880 case RCC_MPCKSELR_PLL_MPUDIV: 881 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 882 883 reg = mmio_read_32(rcc_base + RCC_MPCKDIVR); 884 clkdiv = reg & RCC_MPUDIV_MASK; 885 clock >>= stm32mp1_mpu_div[clkdiv]; 886 break; 887 default: 888 break; 889 } 890 break; 891 /* AXI sub system */ 892 case _ACLK: 893 case _HCLK2: 894 case _HCLK6: 895 case _PCLK4: 896 case _PCLK5: 897 reg = mmio_read_32(rcc_base + RCC_ASSCKSELR); 898 switch (reg & RCC_SELR_SRC_MASK) { 899 case RCC_ASSCKSELR_HSI: 900 clock = stm32mp1_clk_get_fixed(_HSI); 901 break; 902 case RCC_ASSCKSELR_HSE: 903 clock = stm32mp1_clk_get_fixed(_HSE); 904 break; 905 case RCC_ASSCKSELR_PLL: 906 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 907 break; 908 default: 909 break; 910 } 911 912 /* System clock divider */ 913 reg = mmio_read_32(rcc_base + RCC_AXIDIVR); 914 clock /= stm32mp1_axi_div[reg & RCC_AXIDIV_MASK]; 915 916 switch (p) { 917 case _PCLK4: 918 reg = mmio_read_32(rcc_base + RCC_APB4DIVR); 919 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 920 break; 921 case _PCLK5: 922 reg = mmio_read_32(rcc_base + RCC_APB5DIVR); 923 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 924 break; 925 default: 926 break; 927 } 928 break; 929 /* MCU sub system */ 930 case _CK_MCU: 931 case _PCLK1: 932 case _PCLK2: 933 case _PCLK3: 934 reg = mmio_read_32(rcc_base + RCC_MSSCKSELR); 935 switch (reg & RCC_SELR_SRC_MASK) { 936 case RCC_MSSCKSELR_HSI: 937 clock = stm32mp1_clk_get_fixed(_HSI); 938 break; 939 case RCC_MSSCKSELR_HSE: 940 clock = stm32mp1_clk_get_fixed(_HSE); 941 break; 942 case RCC_MSSCKSELR_CSI: 943 clock = stm32mp1_clk_get_fixed(_CSI); 944 break; 945 case RCC_MSSCKSELR_PLL: 946 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 947 break; 948 default: 949 break; 950 } 951 952 /* MCU clock divider */ 953 reg = mmio_read_32(rcc_base + RCC_MCUDIVR); 954 clock >>= stm32mp1_mcu_div[reg & RCC_MCUDIV_MASK]; 955 956 switch (p) { 957 case _PCLK1: 958 reg = mmio_read_32(rcc_base + RCC_APB1DIVR); 959 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 960 break; 961 case _PCLK2: 962 reg = mmio_read_32(rcc_base + RCC_APB2DIVR); 963 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 964 break; 965 case _PCLK3: 966 reg = mmio_read_32(rcc_base + RCC_APB3DIVR); 967 clock >>= stm32mp1_apbx_div[reg & RCC_APBXDIV_MASK]; 968 break; 969 case _CK_MCU: 970 default: 971 break; 972 } 973 break; 974 case _CK_PER: 975 reg = mmio_read_32(rcc_base + RCC_CPERCKSELR); 976 switch (reg & RCC_SELR_SRC_MASK) { 977 case RCC_CPERCKSELR_HSI: 978 clock = stm32mp1_clk_get_fixed(_HSI); 979 break; 980 case RCC_CPERCKSELR_HSE: 981 clock = stm32mp1_clk_get_fixed(_HSE); 982 break; 983 case RCC_CPERCKSELR_CSI: 984 clock = stm32mp1_clk_get_fixed(_CSI); 985 break; 986 default: 987 break; 988 } 989 break; 990 case _HSI: 991 case _HSI_KER: 992 clock = stm32mp1_clk_get_fixed(_HSI); 993 break; 994 case _CSI: 995 case _CSI_KER: 996 clock = stm32mp1_clk_get_fixed(_CSI); 997 break; 998 case _HSE: 999 case _HSE_KER: 1000 clock = stm32mp1_clk_get_fixed(_HSE); 1001 break; 1002 case _HSE_KER_DIV2: 1003 clock = stm32mp1_clk_get_fixed(_HSE) >> 1; 1004 break; 1005 case _HSE_RTC: 1006 clock = stm32mp1_clk_get_fixed(_HSE); 1007 clock /= (mmio_read_32(rcc_base + RCC_RTCDIVR) & RCC_DIVR_DIV_MASK) + 1U; 1008 break; 1009 case _LSI: 1010 clock = stm32mp1_clk_get_fixed(_LSI); 1011 break; 1012 case _LSE: 1013 clock = stm32mp1_clk_get_fixed(_LSE); 1014 break; 1015 /* PLL */ 1016 case _PLL1_P: 1017 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_P); 1018 break; 1019 case _PLL1_Q: 1020 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_Q); 1021 break; 1022 case _PLL1_R: 1023 clock = stm32mp1_read_pll_freq(_PLL1, _DIV_R); 1024 break; 1025 case _PLL2_P: 1026 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_P); 1027 break; 1028 case _PLL2_Q: 1029 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_Q); 1030 break; 1031 case _PLL2_R: 1032 clock = stm32mp1_read_pll_freq(_PLL2, _DIV_R); 1033 break; 1034 case _PLL3_P: 1035 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_P); 1036 break; 1037 case _PLL3_Q: 1038 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_Q); 1039 break; 1040 case _PLL3_R: 1041 clock = stm32mp1_read_pll_freq(_PLL3, _DIV_R); 1042 break; 1043 case _PLL4_P: 1044 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_P); 1045 break; 1046 case _PLL4_Q: 1047 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_Q); 1048 break; 1049 case _PLL4_R: 1050 clock = stm32mp1_read_pll_freq(_PLL4, _DIV_R); 1051 break; 1052 /* Other */ 1053 case _USB_PHY_48: 1054 clock = USB_PHY_48_MHZ; 1055 break; 1056 default: 1057 break; 1058 } 1059 1060 return clock; 1061 } 1062 1063 static void __clk_enable(struct stm32mp1_clk_gate const *gate) 1064 { 1065 uintptr_t rcc_base = stm32mp_rcc_base(); 1066 1067 VERBOSE("Enable clock %u\n", gate->index); 1068 1069 if (gate->set_clr != 0U) { 1070 mmio_write_32(rcc_base + gate->offset, BIT(gate->bit)); 1071 } else { 1072 mmio_setbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1073 } 1074 } 1075 1076 static void __clk_disable(struct stm32mp1_clk_gate const *gate) 1077 { 1078 uintptr_t rcc_base = stm32mp_rcc_base(); 1079 1080 VERBOSE("Disable clock %u\n", gate->index); 1081 1082 if (gate->set_clr != 0U) { 1083 mmio_write_32(rcc_base + gate->offset + RCC_MP_ENCLRR_OFFSET, 1084 BIT(gate->bit)); 1085 } else { 1086 mmio_clrbits_32(rcc_base + gate->offset, BIT(gate->bit)); 1087 } 1088 } 1089 1090 static bool __clk_is_enabled(struct stm32mp1_clk_gate const *gate) 1091 { 1092 uintptr_t rcc_base = stm32mp_rcc_base(); 1093 1094 return mmio_read_32(rcc_base + gate->offset) & BIT(gate->bit); 1095 } 1096 1097 /* Oscillators and PLLs are not gated at runtime */ 1098 static bool clock_is_always_on(unsigned long id) 1099 { 1100 switch (id) { 1101 case CK_HSE: 1102 case CK_CSI: 1103 case CK_LSI: 1104 case CK_LSE: 1105 case CK_HSI: 1106 case CK_HSE_DIV2: 1107 case PLL1_Q: 1108 case PLL1_R: 1109 case PLL2_P: 1110 case PLL2_Q: 1111 case PLL2_R: 1112 case PLL3_P: 1113 case PLL3_Q: 1114 case PLL3_R: 1115 case CK_AXI: 1116 case CK_MPU: 1117 case CK_MCU: 1118 case RTC: 1119 return true; 1120 default: 1121 return false; 1122 } 1123 } 1124 1125 static void __stm32mp1_clk_enable(unsigned long id, bool with_refcnt) 1126 { 1127 const struct stm32mp1_clk_gate *gate; 1128 int i; 1129 1130 if (clock_is_always_on(id)) { 1131 return; 1132 } 1133 1134 i = stm32mp1_clk_get_gated_id(id); 1135 if (i < 0) { 1136 ERROR("Clock %lu can't be enabled\n", id); 1137 panic(); 1138 } 1139 1140 gate = gate_ref(i); 1141 1142 if (!with_refcnt) { 1143 __clk_enable(gate); 1144 return; 1145 } 1146 1147 #if defined(IMAGE_BL32) 1148 if (gate_is_non_secure(gate)) { 1149 /* Enable non-secure clock w/o any refcounting */ 1150 __clk_enable(gate); 1151 return; 1152 } 1153 #endif 1154 1155 stm32mp1_clk_lock(&refcount_lock); 1156 1157 if (gate_refcounts[i] == 0U) { 1158 __clk_enable(gate); 1159 } 1160 1161 gate_refcounts[i]++; 1162 if (gate_refcounts[i] == UINT_MAX) { 1163 ERROR("Clock %lu refcount reached max value\n", id); 1164 panic(); 1165 } 1166 1167 stm32mp1_clk_unlock(&refcount_lock); 1168 } 1169 1170 static void __stm32mp1_clk_disable(unsigned long id, bool with_refcnt) 1171 { 1172 const struct stm32mp1_clk_gate *gate; 1173 int i; 1174 1175 if (clock_is_always_on(id)) { 1176 return; 1177 } 1178 1179 i = stm32mp1_clk_get_gated_id(id); 1180 if (i < 0) { 1181 ERROR("Clock %lu can't be disabled\n", id); 1182 panic(); 1183 } 1184 1185 gate = gate_ref(i); 1186 1187 if (!with_refcnt) { 1188 __clk_disable(gate); 1189 return; 1190 } 1191 1192 #if defined(IMAGE_BL32) 1193 if (gate_is_non_secure(gate)) { 1194 /* Don't disable non-secure clocks */ 1195 return; 1196 } 1197 #endif 1198 1199 stm32mp1_clk_lock(&refcount_lock); 1200 1201 if (gate_refcounts[i] == 0U) { 1202 ERROR("Clock %lu refcount reached 0\n", id); 1203 panic(); 1204 } 1205 gate_refcounts[i]--; 1206 1207 if (gate_refcounts[i] == 0U) { 1208 __clk_disable(gate); 1209 } 1210 1211 stm32mp1_clk_unlock(&refcount_lock); 1212 } 1213 1214 static int stm32mp_clk_enable(unsigned long id) 1215 { 1216 __stm32mp1_clk_enable(id, true); 1217 1218 return 0; 1219 } 1220 1221 static void stm32mp_clk_disable(unsigned long id) 1222 { 1223 __stm32mp1_clk_disable(id, true); 1224 } 1225 1226 static bool stm32mp_clk_is_enabled(unsigned long id) 1227 { 1228 int i; 1229 1230 if (clock_is_always_on(id)) { 1231 return true; 1232 } 1233 1234 i = stm32mp1_clk_get_gated_id(id); 1235 if (i < 0) { 1236 panic(); 1237 } 1238 1239 return __clk_is_enabled(gate_ref(i)); 1240 } 1241 1242 static unsigned long stm32mp_clk_get_rate(unsigned long id) 1243 { 1244 uintptr_t rcc_base = stm32mp_rcc_base(); 1245 int p = stm32mp1_clk_get_parent(id); 1246 uint32_t prescaler, timpre; 1247 unsigned long parent_rate; 1248 1249 if (p < 0) { 1250 return 0; 1251 } 1252 1253 parent_rate = get_clock_rate(p); 1254 1255 switch (id) { 1256 case TIM2_K: 1257 case TIM3_K: 1258 case TIM4_K: 1259 case TIM5_K: 1260 case TIM6_K: 1261 case TIM7_K: 1262 case TIM12_K: 1263 case TIM13_K: 1264 case TIM14_K: 1265 prescaler = mmio_read_32(rcc_base + RCC_APB1DIVR) & 1266 RCC_APBXDIV_MASK; 1267 timpre = mmio_read_32(rcc_base + RCC_TIMG1PRER) & 1268 RCC_TIMGXPRER_TIMGXPRE; 1269 break; 1270 1271 case TIM1_K: 1272 case TIM8_K: 1273 case TIM15_K: 1274 case TIM16_K: 1275 case TIM17_K: 1276 prescaler = mmio_read_32(rcc_base + RCC_APB2DIVR) & 1277 RCC_APBXDIV_MASK; 1278 timpre = mmio_read_32(rcc_base + RCC_TIMG2PRER) & 1279 RCC_TIMGXPRER_TIMGXPRE; 1280 break; 1281 1282 default: 1283 return parent_rate; 1284 } 1285 1286 if (prescaler == 0U) { 1287 return parent_rate; 1288 } 1289 1290 return parent_rate * (timpre + 1U) * 2U; 1291 } 1292 1293 static void stm32mp1_ls_osc_set(bool enable, uint32_t offset, uint32_t mask_on) 1294 { 1295 uintptr_t address = stm32mp_rcc_base() + offset; 1296 1297 if (enable) { 1298 mmio_setbits_32(address, mask_on); 1299 } else { 1300 mmio_clrbits_32(address, mask_on); 1301 } 1302 } 1303 1304 static void stm32mp1_hs_ocs_set(bool enable, uint32_t mask_on) 1305 { 1306 uint32_t offset = enable ? RCC_OCENSETR : RCC_OCENCLRR; 1307 uintptr_t address = stm32mp_rcc_base() + offset; 1308 1309 mmio_write_32(address, mask_on); 1310 } 1311 1312 static int stm32mp1_osc_wait(bool enable, uint32_t offset, uint32_t mask_rdy) 1313 { 1314 uint64_t timeout; 1315 uint32_t mask_test; 1316 uintptr_t address = stm32mp_rcc_base() + offset; 1317 1318 if (enable) { 1319 mask_test = mask_rdy; 1320 } else { 1321 mask_test = 0; 1322 } 1323 1324 timeout = timeout_init_us(OSCRDY_TIMEOUT); 1325 while ((mmio_read_32(address) & mask_rdy) != mask_test) { 1326 if (timeout_elapsed(timeout)) { 1327 ERROR("OSC %x @ %lx timeout for enable=%d : 0x%x\n", 1328 mask_rdy, address, enable, mmio_read_32(address)); 1329 return -ETIMEDOUT; 1330 } 1331 } 1332 1333 return 0; 1334 } 1335 1336 static void stm32mp1_lse_enable(bool bypass, bool digbyp, uint32_t lsedrv) 1337 { 1338 uint32_t value; 1339 uintptr_t rcc_base = stm32mp_rcc_base(); 1340 1341 /* Do not reconfigure LSE if it is already ON */ 1342 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEON) == RCC_BDCR_LSEON) { 1343 return; 1344 } 1345 1346 if (digbyp) { 1347 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_DIGBYP); 1348 } 1349 1350 if (bypass || digbyp) { 1351 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_LSEBYP); 1352 } 1353 1354 /* 1355 * Warning: not recommended to switch directly from "high drive" 1356 * to "medium low drive", and vice-versa. 1357 */ 1358 value = (mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) >> 1359 RCC_BDCR_LSEDRV_SHIFT; 1360 1361 while (value != lsedrv) { 1362 if (value > lsedrv) { 1363 value--; 1364 } else { 1365 value++; 1366 } 1367 1368 mmio_clrsetbits_32(rcc_base + RCC_BDCR, 1369 RCC_BDCR_LSEDRV_MASK, 1370 value << RCC_BDCR_LSEDRV_SHIFT); 1371 } 1372 1373 stm32mp1_ls_osc_set(true, RCC_BDCR, RCC_BDCR_LSEON); 1374 } 1375 1376 static void stm32mp1_lse_wait(void) 1377 { 1378 if (stm32mp1_osc_wait(true, RCC_BDCR, RCC_BDCR_LSERDY) != 0) { 1379 VERBOSE("%s: failed\n", __func__); 1380 } 1381 } 1382 1383 static void stm32mp1_lsi_set(bool enable) 1384 { 1385 stm32mp1_ls_osc_set(enable, RCC_RDLSICR, RCC_RDLSICR_LSION); 1386 1387 if (stm32mp1_osc_wait(enable, RCC_RDLSICR, RCC_RDLSICR_LSIRDY) != 0) { 1388 VERBOSE("%s: failed\n", __func__); 1389 } 1390 } 1391 1392 static void stm32mp1_hse_enable(bool bypass, bool digbyp, bool css) 1393 { 1394 uintptr_t rcc_base = stm32mp_rcc_base(); 1395 1396 if (digbyp) { 1397 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_DIGBYP); 1398 } 1399 1400 if (bypass || digbyp) { 1401 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSEBYP); 1402 } 1403 1404 stm32mp1_hs_ocs_set(true, RCC_OCENR_HSEON); 1405 if (stm32mp1_osc_wait(true, RCC_OCRDYR, RCC_OCRDYR_HSERDY) != 0) { 1406 VERBOSE("%s: failed\n", __func__); 1407 } 1408 1409 if (css) { 1410 mmio_write_32(rcc_base + RCC_OCENSETR, RCC_OCENR_HSECSSON); 1411 } 1412 1413 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 1414 if ((mmio_read_32(rcc_base + RCC_OCENSETR) & RCC_OCENR_HSEBYP) && 1415 (!(digbyp || bypass))) { 1416 panic(); 1417 } 1418 #endif 1419 } 1420 1421 static void stm32mp1_csi_set(bool enable) 1422 { 1423 stm32mp1_hs_ocs_set(enable, RCC_OCENR_CSION); 1424 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_CSIRDY) != 0) { 1425 VERBOSE("%s: failed\n", __func__); 1426 } 1427 } 1428 1429 static void stm32mp1_hsi_set(bool enable) 1430 { 1431 stm32mp1_hs_ocs_set(enable, RCC_OCENR_HSION); 1432 if (stm32mp1_osc_wait(enable, RCC_OCRDYR, RCC_OCRDYR_HSIRDY) != 0) { 1433 VERBOSE("%s: failed\n", __func__); 1434 } 1435 } 1436 1437 static int stm32mp1_set_hsidiv(uint8_t hsidiv) 1438 { 1439 uint64_t timeout; 1440 uintptr_t rcc_base = stm32mp_rcc_base(); 1441 uintptr_t address = rcc_base + RCC_OCRDYR; 1442 1443 mmio_clrsetbits_32(rcc_base + RCC_HSICFGR, 1444 RCC_HSICFGR_HSIDIV_MASK, 1445 RCC_HSICFGR_HSIDIV_MASK & (uint32_t)hsidiv); 1446 1447 timeout = timeout_init_us(HSIDIV_TIMEOUT); 1448 while ((mmio_read_32(address) & RCC_OCRDYR_HSIDIVRDY) == 0U) { 1449 if (timeout_elapsed(timeout)) { 1450 ERROR("HSIDIV failed @ 0x%lx: 0x%x\n", 1451 address, mmio_read_32(address)); 1452 return -ETIMEDOUT; 1453 } 1454 } 1455 1456 return 0; 1457 } 1458 1459 static int stm32mp1_hsidiv(unsigned long hsifreq) 1460 { 1461 uint8_t hsidiv; 1462 uint32_t hsidivfreq = MAX_HSI_HZ; 1463 1464 for (hsidiv = 0; hsidiv < 4U; hsidiv++) { 1465 if (hsidivfreq == hsifreq) { 1466 break; 1467 } 1468 1469 hsidivfreq /= 2U; 1470 } 1471 1472 if (hsidiv == 4U) { 1473 ERROR("Invalid clk-hsi frequency\n"); 1474 return -1; 1475 } 1476 1477 if (hsidiv != 0U) { 1478 return stm32mp1_set_hsidiv(hsidiv); 1479 } 1480 1481 return 0; 1482 } 1483 1484 static bool stm32mp1_check_pll_conf(enum stm32mp1_pll_id pll_id, 1485 unsigned int clksrc, 1486 uint32_t *pllcfg, int plloff) 1487 { 1488 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1489 uintptr_t rcc_base = stm32mp_rcc_base(); 1490 uintptr_t pllxcr = rcc_base + pll->pllxcr; 1491 enum stm32mp1_plltype type = pll->plltype; 1492 uintptr_t clksrc_address = rcc_base + (clksrc >> 4); 1493 unsigned long refclk; 1494 uint32_t ifrge = 0U; 1495 uint32_t src, value, fracv = 0; 1496 void *fdt; 1497 1498 /* Check PLL output */ 1499 if (mmio_read_32(pllxcr) != RCC_PLLNCR_PLLON) { 1500 return false; 1501 } 1502 1503 /* Check current clksrc */ 1504 src = mmio_read_32(clksrc_address) & RCC_SELR_SRC_MASK; 1505 if (src != (clksrc & RCC_SELR_SRC_MASK)) { 1506 return false; 1507 } 1508 1509 /* Check Div */ 1510 src = mmio_read_32(rcc_base + pll->rckxselr) & RCC_SELR_REFCLK_SRC_MASK; 1511 1512 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1513 (pllcfg[PLLCFG_M] + 1U); 1514 1515 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1516 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1517 return false; 1518 } 1519 1520 if ((type == PLL_800) && (refclk >= 8000000U)) { 1521 ifrge = 1U; 1522 } 1523 1524 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1525 RCC_PLLNCFGR1_DIVN_MASK; 1526 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1527 RCC_PLLNCFGR1_DIVM_MASK; 1528 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1529 RCC_PLLNCFGR1_IFRGE_MASK; 1530 if (mmio_read_32(rcc_base + pll->pllxcfgr1) != value) { 1531 return false; 1532 } 1533 1534 /* Fractional configuration */ 1535 if (fdt_get_address(&fdt) == 1) { 1536 fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1537 } 1538 1539 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1540 value |= RCC_PLLNFRACR_FRACLE; 1541 if (mmio_read_32(rcc_base + pll->pllxfracr) != value) { 1542 return false; 1543 } 1544 1545 /* Output config */ 1546 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1547 RCC_PLLNCFGR2_DIVP_MASK; 1548 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1549 RCC_PLLNCFGR2_DIVQ_MASK; 1550 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1551 RCC_PLLNCFGR2_DIVR_MASK; 1552 if (mmio_read_32(rcc_base + pll->pllxcfgr2) != value) { 1553 return false; 1554 } 1555 1556 return true; 1557 } 1558 1559 static void stm32mp1_pll_start(enum stm32mp1_pll_id pll_id) 1560 { 1561 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1562 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1563 1564 /* Preserve RCC_PLLNCR_SSCG_CTRL value */ 1565 mmio_clrsetbits_32(pllxcr, 1566 RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1567 RCC_PLLNCR_DIVREN, 1568 RCC_PLLNCR_PLLON); 1569 } 1570 1571 static int stm32mp1_pll_output(enum stm32mp1_pll_id pll_id, uint32_t output) 1572 { 1573 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1574 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1575 uint64_t timeout = timeout_init_us(PLLRDY_TIMEOUT); 1576 1577 /* Wait PLL lock */ 1578 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) == 0U) { 1579 if (timeout_elapsed(timeout)) { 1580 ERROR("PLL%u start failed @ 0x%lx: 0x%x\n", 1581 pll_id, pllxcr, mmio_read_32(pllxcr)); 1582 return -ETIMEDOUT; 1583 } 1584 } 1585 1586 /* Start the requested output */ 1587 mmio_setbits_32(pllxcr, output << RCC_PLLNCR_DIVEN_SHIFT); 1588 1589 return 0; 1590 } 1591 1592 static int stm32mp1_pll_stop(enum stm32mp1_pll_id pll_id) 1593 { 1594 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1595 uintptr_t pllxcr = stm32mp_rcc_base() + pll->pllxcr; 1596 uint64_t timeout; 1597 1598 /* Stop all output */ 1599 mmio_clrbits_32(pllxcr, RCC_PLLNCR_DIVPEN | RCC_PLLNCR_DIVQEN | 1600 RCC_PLLNCR_DIVREN); 1601 1602 /* Stop PLL */ 1603 mmio_clrbits_32(pllxcr, RCC_PLLNCR_PLLON); 1604 1605 timeout = timeout_init_us(PLLRDY_TIMEOUT); 1606 /* Wait PLL stopped */ 1607 while ((mmio_read_32(pllxcr) & RCC_PLLNCR_PLLRDY) != 0U) { 1608 if (timeout_elapsed(timeout)) { 1609 ERROR("PLL%u stop failed @ 0x%lx: 0x%x\n", 1610 pll_id, pllxcr, mmio_read_32(pllxcr)); 1611 return -ETIMEDOUT; 1612 } 1613 } 1614 1615 return 0; 1616 } 1617 1618 static void stm32mp1_pll_config_output(enum stm32mp1_pll_id pll_id, 1619 uint32_t *pllcfg) 1620 { 1621 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1622 uintptr_t rcc_base = stm32mp_rcc_base(); 1623 uint32_t value; 1624 1625 value = (pllcfg[PLLCFG_P] << RCC_PLLNCFGR2_DIVP_SHIFT) & 1626 RCC_PLLNCFGR2_DIVP_MASK; 1627 value |= (pllcfg[PLLCFG_Q] << RCC_PLLNCFGR2_DIVQ_SHIFT) & 1628 RCC_PLLNCFGR2_DIVQ_MASK; 1629 value |= (pllcfg[PLLCFG_R] << RCC_PLLNCFGR2_DIVR_SHIFT) & 1630 RCC_PLLNCFGR2_DIVR_MASK; 1631 mmio_write_32(rcc_base + pll->pllxcfgr2, value); 1632 } 1633 1634 static int stm32mp1_pll_config(enum stm32mp1_pll_id pll_id, 1635 uint32_t *pllcfg, uint32_t fracv) 1636 { 1637 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1638 uintptr_t rcc_base = stm32mp_rcc_base(); 1639 enum stm32mp1_plltype type = pll->plltype; 1640 unsigned long refclk; 1641 uint32_t ifrge = 0; 1642 uint32_t src, value; 1643 1644 src = mmio_read_32(rcc_base + pll->rckxselr) & 1645 RCC_SELR_REFCLK_SRC_MASK; 1646 1647 refclk = stm32mp1_clk_get_fixed(pll->refclk[src]) / 1648 (pllcfg[PLLCFG_M] + 1U); 1649 1650 if ((refclk < (stm32mp1_pll[type].refclk_min * 1000000U)) || 1651 (refclk > (stm32mp1_pll[type].refclk_max * 1000000U))) { 1652 return -EINVAL; 1653 } 1654 1655 if ((type == PLL_800) && (refclk >= 8000000U)) { 1656 ifrge = 1U; 1657 } 1658 1659 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & 1660 RCC_PLLNCFGR1_DIVN_MASK; 1661 value |= (pllcfg[PLLCFG_M] << RCC_PLLNCFGR1_DIVM_SHIFT) & 1662 RCC_PLLNCFGR1_DIVM_MASK; 1663 value |= (ifrge << RCC_PLLNCFGR1_IFRGE_SHIFT) & 1664 RCC_PLLNCFGR1_IFRGE_MASK; 1665 mmio_write_32(rcc_base + pll->pllxcfgr1, value); 1666 1667 /* Fractional configuration */ 1668 value = 0; 1669 mmio_write_32(rcc_base + pll->pllxfracr, value); 1670 1671 value = fracv << RCC_PLLNFRACR_FRACV_SHIFT; 1672 mmio_write_32(rcc_base + pll->pllxfracr, value); 1673 1674 value |= RCC_PLLNFRACR_FRACLE; 1675 mmio_write_32(rcc_base + pll->pllxfracr, value); 1676 1677 stm32mp1_pll_config_output(pll_id, pllcfg); 1678 1679 return 0; 1680 } 1681 1682 static void stm32mp1_pll_csg(enum stm32mp1_pll_id pll_id, uint32_t *csg) 1683 { 1684 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 1685 uint32_t pllxcsg = 0; 1686 1687 pllxcsg |= (csg[PLLCSG_MOD_PER] << RCC_PLLNCSGR_MOD_PER_SHIFT) & 1688 RCC_PLLNCSGR_MOD_PER_MASK; 1689 1690 pllxcsg |= (csg[PLLCSG_INC_STEP] << RCC_PLLNCSGR_INC_STEP_SHIFT) & 1691 RCC_PLLNCSGR_INC_STEP_MASK; 1692 1693 pllxcsg |= (csg[PLLCSG_SSCG_MODE] << RCC_PLLNCSGR_SSCG_MODE_SHIFT) & 1694 RCC_PLLNCSGR_SSCG_MODE_MASK; 1695 1696 mmio_write_32(stm32mp_rcc_base() + pll->pllxcsgr, pllxcsg); 1697 1698 mmio_setbits_32(stm32mp_rcc_base() + pll->pllxcr, 1699 RCC_PLLNCR_SSCG_CTRL); 1700 } 1701 1702 static int stm32mp1_set_clksrc(unsigned int clksrc) 1703 { 1704 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1705 uint64_t timeout; 1706 1707 mmio_clrsetbits_32(clksrc_address, RCC_SELR_SRC_MASK, 1708 clksrc & RCC_SELR_SRC_MASK); 1709 1710 timeout = timeout_init_us(CLKSRC_TIMEOUT); 1711 while ((mmio_read_32(clksrc_address) & RCC_SELR_SRCRDY) == 0U) { 1712 if (timeout_elapsed(timeout)) { 1713 ERROR("CLKSRC %x start failed @ 0x%lx: 0x%x\n", clksrc, 1714 clksrc_address, mmio_read_32(clksrc_address)); 1715 return -ETIMEDOUT; 1716 } 1717 } 1718 1719 return 0; 1720 } 1721 1722 static int stm32mp1_set_clkdiv(unsigned int clkdiv, uintptr_t address) 1723 { 1724 uint64_t timeout; 1725 1726 mmio_clrsetbits_32(address, RCC_DIVR_DIV_MASK, 1727 clkdiv & RCC_DIVR_DIV_MASK); 1728 1729 timeout = timeout_init_us(CLKDIV_TIMEOUT); 1730 while ((mmio_read_32(address) & RCC_DIVR_DIVRDY) == 0U) { 1731 if (timeout_elapsed(timeout)) { 1732 ERROR("CLKDIV %x start failed @ 0x%lx: 0x%x\n", 1733 clkdiv, address, mmio_read_32(address)); 1734 return -ETIMEDOUT; 1735 } 1736 } 1737 1738 return 0; 1739 } 1740 1741 static void stm32mp1_mco_csg(uint32_t clksrc, uint32_t clkdiv) 1742 { 1743 uintptr_t clksrc_address = stm32mp_rcc_base() + (clksrc >> 4); 1744 1745 /* 1746 * Binding clksrc : 1747 * bit15-4 offset 1748 * bit3: disable 1749 * bit2-0: MCOSEL[2:0] 1750 */ 1751 if ((clksrc & 0x8U) != 0U) { 1752 mmio_clrbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1753 } else { 1754 mmio_clrsetbits_32(clksrc_address, 1755 RCC_MCOCFG_MCOSRC_MASK, 1756 clksrc & RCC_MCOCFG_MCOSRC_MASK); 1757 mmio_clrsetbits_32(clksrc_address, 1758 RCC_MCOCFG_MCODIV_MASK, 1759 clkdiv << RCC_MCOCFG_MCODIV_SHIFT); 1760 mmio_setbits_32(clksrc_address, RCC_MCOCFG_MCOON); 1761 } 1762 } 1763 1764 static void stm32mp1_set_rtcsrc(unsigned int clksrc, bool lse_css) 1765 { 1766 uintptr_t address = stm32mp_rcc_base() + RCC_BDCR; 1767 1768 if (((mmio_read_32(address) & RCC_BDCR_RTCCKEN) == 0U) || 1769 (clksrc != (uint32_t)CLK_RTC_DISABLED)) { 1770 mmio_clrsetbits_32(address, 1771 RCC_BDCR_RTCSRC_MASK, 1772 (clksrc & RCC_SELR_SRC_MASK) << RCC_BDCR_RTCSRC_SHIFT); 1773 1774 mmio_setbits_32(address, RCC_BDCR_RTCCKEN); 1775 } 1776 1777 if (lse_css) { 1778 mmio_setbits_32(address, RCC_BDCR_LSECSSON); 1779 } 1780 } 1781 1782 static void stm32mp1_pkcs_config(uint32_t pkcs) 1783 { 1784 uintptr_t address = stm32mp_rcc_base() + ((pkcs >> 4) & 0xFFFU); 1785 uint32_t value = pkcs & 0xFU; 1786 uint32_t mask = 0xFU; 1787 1788 if ((pkcs & BIT(31)) != 0U) { 1789 mask <<= 4; 1790 value <<= 4; 1791 } 1792 1793 mmio_clrsetbits_32(address, mask, value); 1794 } 1795 1796 static int clk_get_pll_settings_from_dt(int plloff, unsigned int *pllcfg, 1797 uint32_t *fracv, uint32_t *csg, 1798 bool *csg_set) 1799 { 1800 void *fdt; 1801 int ret; 1802 1803 if (fdt_get_address(&fdt) == 0) { 1804 return -FDT_ERR_NOTFOUND; 1805 } 1806 1807 ret = fdt_read_uint32_array(fdt, plloff, "cfg", (uint32_t)PLLCFG_NB, 1808 pllcfg); 1809 if (ret < 0) { 1810 return -FDT_ERR_NOTFOUND; 1811 } 1812 1813 *fracv = fdt_read_uint32_default(fdt, plloff, "frac", 0); 1814 1815 ret = fdt_read_uint32_array(fdt, plloff, "csg", (uint32_t)PLLCSG_NB, 1816 csg); 1817 1818 *csg_set = (ret == 0); 1819 1820 if (ret == -FDT_ERR_NOTFOUND) { 1821 ret = 0; 1822 } 1823 1824 return ret; 1825 } 1826 1827 static int clk_compute_pll1_settings(unsigned long input_freq, 1828 uint32_t freq_khz, 1829 uint32_t *pllcfg, uint32_t *fracv) 1830 { 1831 unsigned long long best_diff = ULLONG_MAX; 1832 unsigned int divm; 1833 1834 /* Following parameters have always the same value */ 1835 pllcfg[PLLCFG_Q] = 0U; 1836 pllcfg[PLLCFG_R] = 0U; 1837 pllcfg[PLLCFG_O] = PQR(1, 0, 0); 1838 1839 for (divm = (DIVM_MAX + 1U); divm != DIVM_MIN; divm--) { 1840 unsigned long post_divm = input_freq / divm; 1841 unsigned int divp; 1842 1843 if ((post_divm < POST_DIVM_MIN) || (post_divm > POST_DIVM_MAX)) { 1844 continue; 1845 } 1846 1847 for (divp = DIVP_MIN; divp <= DIVP_MAX; divp++) { 1848 unsigned long long output_freq = freq_khz * 1000ULL; 1849 unsigned long long freq; 1850 unsigned long long divn; 1851 unsigned long long frac; 1852 unsigned int i; 1853 1854 freq = output_freq * divm * (divp + 1U); 1855 1856 divn = (freq / input_freq) - 1U; 1857 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { 1858 continue; 1859 } 1860 1861 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); 1862 1863 /* 2 loops to refine the fractional part */ 1864 for (i = 2U; i != 0U; i--) { 1865 unsigned long long diff; 1866 unsigned long long vco; 1867 1868 if (frac > FRAC_MAX) { 1869 break; 1870 } 1871 1872 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); 1873 1874 if ((vco < (VCO_MIN / 2U)) || (vco > (VCO_MAX / 2U))) { 1875 frac++; 1876 continue; 1877 } 1878 1879 freq = vco / (divp + 1U); 1880 if (output_freq < freq) { 1881 diff = freq - output_freq; 1882 } else { 1883 diff = output_freq - freq; 1884 } 1885 1886 if (diff < best_diff) { 1887 pllcfg[PLLCFG_M] = divm - 1U; 1888 pllcfg[PLLCFG_N] = (uint32_t)divn; 1889 pllcfg[PLLCFG_P] = divp; 1890 *fracv = (uint32_t)frac; 1891 1892 if (diff == 0U) { 1893 return 0; 1894 } 1895 1896 best_diff = diff; 1897 } 1898 1899 frac++; 1900 } 1901 } 1902 } 1903 1904 if (best_diff == ULLONG_MAX) { 1905 return -EINVAL; 1906 } 1907 1908 return 0; 1909 } 1910 1911 static int clk_get_pll1_settings(uint32_t clksrc, uint32_t freq_khz, 1912 uint32_t *pllcfg, uint32_t *fracv) 1913 { 1914 unsigned long input_freq = 0UL; 1915 1916 assert(pllcfg != NULL); 1917 assert(fracv != NULL); 1918 1919 switch (clksrc) { 1920 case CLK_PLL12_HSI: 1921 input_freq = stm32mp_clk_get_rate(CK_HSI); 1922 break; 1923 case CLK_PLL12_HSE: 1924 input_freq = stm32mp_clk_get_rate(CK_HSE); 1925 break; 1926 default: 1927 break; 1928 } 1929 1930 if (input_freq == 0UL) { 1931 panic(); 1932 } 1933 1934 return clk_compute_pll1_settings(input_freq, freq_khz, pllcfg, fracv); 1935 } 1936 1937 int stm32mp1_clk_init(void) 1938 { 1939 uintptr_t rcc_base = stm32mp_rcc_base(); 1940 uint32_t pllfracv[_PLL_NB]; 1941 uint32_t pllcsg[_PLL_NB][PLLCSG_NB]; 1942 unsigned int clksrc[CLKSRC_NB]; 1943 unsigned int clkdiv[CLKDIV_NB]; 1944 unsigned int pllcfg[_PLL_NB][PLLCFG_NB]; 1945 int plloff[_PLL_NB]; 1946 int ret, len; 1947 enum stm32mp1_pll_id i; 1948 bool pllcsg_set[_PLL_NB]; 1949 bool pllcfg_valid[_PLL_NB]; 1950 bool lse_css = false; 1951 bool pll3_preserve = false; 1952 bool pll4_preserve = false; 1953 bool pll4_bootrom = false; 1954 const fdt32_t *pkcs_cell; 1955 void *fdt; 1956 int stgen_p = stm32mp1_clk_get_parent(STGEN_K); 1957 int usbphy_p = stm32mp1_clk_get_parent(USBPHY_K); 1958 1959 if (fdt_get_address(&fdt) == 0) { 1960 return -FDT_ERR_NOTFOUND; 1961 } 1962 1963 ret = fdt_rcc_read_uint32_array("st,clksrc", (uint32_t)CLKSRC_NB, 1964 clksrc); 1965 if (ret < 0) { 1966 return -FDT_ERR_NOTFOUND; 1967 } 1968 1969 ret = fdt_rcc_read_uint32_array("st,clkdiv", (uint32_t)CLKDIV_NB, 1970 clkdiv); 1971 if (ret < 0) { 1972 return -FDT_ERR_NOTFOUND; 1973 } 1974 1975 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 1976 char name[12]; 1977 1978 snprintf(name, sizeof(name), "st,pll@%u", i); 1979 plloff[i] = fdt_rcc_subnode_offset(name); 1980 1981 pllcfg_valid[i] = fdt_check_node(plloff[i]); 1982 if (pllcfg_valid[i]) { 1983 ret = clk_get_pll_settings_from_dt(plloff[i], pllcfg[i], 1984 &pllfracv[i], 1985 pllcsg[i], 1986 &pllcsg_set[i]); 1987 if (ret != 0) { 1988 return ret; 1989 } 1990 1991 continue; 1992 } 1993 1994 if (i == _PLL1) { 1995 ret = clk_get_pll1_settings(clksrc[CLKSRC_PLL12], 1996 PLL1_NOMINAL_FREQ_IN_KHZ, 1997 pllcfg[i], &pllfracv[i]); 1998 if (ret != 0) { 1999 return ret; 2000 } 2001 2002 pllcfg_valid[i] = true; 2003 } 2004 } 2005 2006 stm32mp1_mco_csg(clksrc[CLKSRC_MCO1], clkdiv[CLKDIV_MCO1]); 2007 stm32mp1_mco_csg(clksrc[CLKSRC_MCO2], clkdiv[CLKDIV_MCO2]); 2008 2009 /* 2010 * Switch ON oscillator found in device-tree. 2011 * Note: HSI already ON after BootROM stage. 2012 */ 2013 if (stm32mp1_osc[_LSI] != 0U) { 2014 stm32mp1_lsi_set(true); 2015 } 2016 if (stm32mp1_osc[_LSE] != 0U) { 2017 const char *name = stm32mp_osc_node_label[_LSE]; 2018 bool bypass, digbyp; 2019 uint32_t lsedrv; 2020 2021 bypass = fdt_clk_read_bool(name, "st,bypass"); 2022 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 2023 lse_css = fdt_clk_read_bool(name, "st,css"); 2024 lsedrv = fdt_clk_read_uint32_default(name, "st,drive", 2025 LSEDRV_MEDIUM_HIGH); 2026 stm32mp1_lse_enable(bypass, digbyp, lsedrv); 2027 } 2028 if (stm32mp1_osc[_HSE] != 0U) { 2029 const char *name = stm32mp_osc_node_label[_HSE]; 2030 bool bypass, digbyp, css; 2031 2032 bypass = fdt_clk_read_bool(name, "st,bypass"); 2033 digbyp = fdt_clk_read_bool(name, "st,digbypass"); 2034 css = fdt_clk_read_bool(name, "st,css"); 2035 stm32mp1_hse_enable(bypass, digbyp, css); 2036 } 2037 /* 2038 * CSI is mandatory for automatic I/O compensation (SYSCFG_CMPCR) 2039 * => switch on CSI even if node is not present in device tree 2040 */ 2041 stm32mp1_csi_set(true); 2042 2043 /* Come back to HSI */ 2044 ret = stm32mp1_set_clksrc(CLK_MPU_HSI); 2045 if (ret != 0) { 2046 return ret; 2047 } 2048 ret = stm32mp1_set_clksrc(CLK_AXI_HSI); 2049 if (ret != 0) { 2050 return ret; 2051 } 2052 ret = stm32mp1_set_clksrc(CLK_MCU_HSI); 2053 if (ret != 0) { 2054 return ret; 2055 } 2056 2057 if ((mmio_read_32(rcc_base + RCC_MP_RSTSCLRR) & 2058 RCC_MP_RSTSCLRR_MPUP0RSTF) != 0) { 2059 if (pllcfg_valid[_PLL3]) { 2060 pll3_preserve = 2061 stm32mp1_check_pll_conf(_PLL3, 2062 clksrc[CLKSRC_PLL3], 2063 pllcfg[_PLL3], 2064 plloff[_PLL3]); 2065 } 2066 2067 if (pllcfg_valid[_PLL4]) { 2068 pll4_preserve = 2069 stm32mp1_check_pll_conf(_PLL4, 2070 clksrc[CLKSRC_PLL4], 2071 pllcfg[_PLL4], 2072 plloff[_PLL4]); 2073 } 2074 } 2075 /* Don't initialize PLL4, when used by BOOTROM */ 2076 if ((stm32mp_get_boot_itf_selected() == 2077 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB) && 2078 ((stgen_p == (int)_PLL4_R) || (usbphy_p == (int)_PLL4_R))) { 2079 pll4_bootrom = true; 2080 pll4_preserve = true; 2081 } 2082 2083 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2084 if (((i == _PLL3) && pll3_preserve) || 2085 ((i == _PLL4) && pll4_preserve)) { 2086 continue; 2087 } 2088 2089 ret = stm32mp1_pll_stop(i); 2090 if (ret != 0) { 2091 return ret; 2092 } 2093 } 2094 2095 /* Configure HSIDIV */ 2096 if (stm32mp1_osc[_HSI] != 0U) { 2097 ret = stm32mp1_hsidiv(stm32mp1_osc[_HSI]); 2098 if (ret != 0) { 2099 return ret; 2100 } 2101 2102 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2103 } 2104 2105 /* Select DIV */ 2106 /* No ready bit when MPUSRC != CLK_MPU_PLL1P_DIV, MPUDIV is disabled */ 2107 mmio_write_32(rcc_base + RCC_MPCKDIVR, 2108 clkdiv[CLKDIV_MPU] & RCC_DIVR_DIV_MASK); 2109 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_AXI], rcc_base + RCC_AXIDIVR); 2110 if (ret != 0) { 2111 return ret; 2112 } 2113 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB4], rcc_base + RCC_APB4DIVR); 2114 if (ret != 0) { 2115 return ret; 2116 } 2117 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB5], rcc_base + RCC_APB5DIVR); 2118 if (ret != 0) { 2119 return ret; 2120 } 2121 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_MCU], rcc_base + RCC_MCUDIVR); 2122 if (ret != 0) { 2123 return ret; 2124 } 2125 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB1], rcc_base + RCC_APB1DIVR); 2126 if (ret != 0) { 2127 return ret; 2128 } 2129 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB2], rcc_base + RCC_APB2DIVR); 2130 if (ret != 0) { 2131 return ret; 2132 } 2133 ret = stm32mp1_set_clkdiv(clkdiv[CLKDIV_APB3], rcc_base + RCC_APB3DIVR); 2134 if (ret != 0) { 2135 return ret; 2136 } 2137 2138 /* No ready bit for RTC */ 2139 mmio_write_32(rcc_base + RCC_RTCDIVR, 2140 clkdiv[CLKDIV_RTC] & RCC_DIVR_DIV_MASK); 2141 2142 /* Configure PLLs source */ 2143 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL12]); 2144 if (ret != 0) { 2145 return ret; 2146 } 2147 2148 if (!pll3_preserve) { 2149 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL3]); 2150 if (ret != 0) { 2151 return ret; 2152 } 2153 } 2154 2155 if (!pll4_preserve) { 2156 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_PLL4]); 2157 if (ret != 0) { 2158 return ret; 2159 } 2160 } 2161 2162 /* Configure and start PLLs */ 2163 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2164 if (((i == _PLL3) && pll3_preserve) || 2165 ((i == _PLL4) && pll4_preserve && !pll4_bootrom)) { 2166 continue; 2167 } 2168 2169 if (!pllcfg_valid[i]) { 2170 continue; 2171 } 2172 2173 if ((i == _PLL4) && pll4_bootrom) { 2174 /* Set output divider if not done by the Bootrom */ 2175 stm32mp1_pll_config_output(i, pllcfg[i]); 2176 continue; 2177 } 2178 2179 ret = stm32mp1_pll_config(i, pllcfg[i], pllfracv[i]); 2180 if (ret != 0) { 2181 return ret; 2182 } 2183 2184 if (pllcsg_set[i]) { 2185 stm32mp1_pll_csg(i, pllcsg[i]); 2186 } 2187 2188 stm32mp1_pll_start(i); 2189 } 2190 /* Wait and start PLLs output when ready */ 2191 for (i = (enum stm32mp1_pll_id)0; i < _PLL_NB; i++) { 2192 if (!pllcfg_valid[i]) { 2193 continue; 2194 } 2195 2196 ret = stm32mp1_pll_output(i, pllcfg[i][PLLCFG_O]); 2197 if (ret != 0) { 2198 return ret; 2199 } 2200 } 2201 /* Wait LSE ready before to use it */ 2202 if (stm32mp1_osc[_LSE] != 0U) { 2203 stm32mp1_lse_wait(); 2204 } 2205 2206 /* Configure with expected clock source */ 2207 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MPU]); 2208 if (ret != 0) { 2209 return ret; 2210 } 2211 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_AXI]); 2212 if (ret != 0) { 2213 return ret; 2214 } 2215 ret = stm32mp1_set_clksrc(clksrc[CLKSRC_MCU]); 2216 if (ret != 0) { 2217 return ret; 2218 } 2219 stm32mp1_set_rtcsrc(clksrc[CLKSRC_RTC], lse_css); 2220 2221 /* Configure PKCK */ 2222 pkcs_cell = fdt_rcc_read_prop("st,pkcs", &len); 2223 if (pkcs_cell != NULL) { 2224 bool ckper_disabled = false; 2225 uint32_t j; 2226 uint32_t usbreg_bootrom = 0U; 2227 2228 if (pll4_bootrom) { 2229 usbreg_bootrom = mmio_read_32(rcc_base + RCC_USBCKSELR); 2230 } 2231 2232 for (j = 0; j < ((uint32_t)len / sizeof(uint32_t)); j++) { 2233 uint32_t pkcs = fdt32_to_cpu(pkcs_cell[j]); 2234 2235 if (pkcs == (uint32_t)CLK_CKPER_DISABLED) { 2236 ckper_disabled = true; 2237 continue; 2238 } 2239 stm32mp1_pkcs_config(pkcs); 2240 } 2241 2242 /* 2243 * CKPER is source for some peripheral clocks 2244 * (FMC-NAND / QPSI-NOR) and switching source is allowed 2245 * only if previous clock is still ON 2246 * => deactivated CKPER only after switching clock 2247 */ 2248 if (ckper_disabled) { 2249 stm32mp1_pkcs_config(CLK_CKPER_DISABLED); 2250 } 2251 2252 if (pll4_bootrom) { 2253 uint32_t usbreg_value, usbreg_mask; 2254 const struct stm32mp1_clk_sel *sel; 2255 2256 sel = clk_sel_ref(_USBPHY_SEL); 2257 usbreg_mask = (uint32_t)sel->msk << sel->src; 2258 sel = clk_sel_ref(_USBO_SEL); 2259 usbreg_mask |= (uint32_t)sel->msk << sel->src; 2260 2261 usbreg_value = mmio_read_32(rcc_base + RCC_USBCKSELR) & 2262 usbreg_mask; 2263 usbreg_bootrom &= usbreg_mask; 2264 if (usbreg_bootrom != usbreg_value) { 2265 VERBOSE("forbidden new USB clk path\n"); 2266 VERBOSE("vs bootrom on USB boot\n"); 2267 return -FDT_ERR_BADVALUE; 2268 } 2269 } 2270 } 2271 2272 /* Switch OFF HSI if not found in device-tree */ 2273 if (stm32mp1_osc[_HSI] == 0U) { 2274 stm32mp1_hsi_set(false); 2275 } 2276 2277 stm32mp_stgen_config(stm32mp_clk_get_rate(STGEN_K)); 2278 2279 /* Software Self-Refresh mode (SSR) during DDR initilialization */ 2280 mmio_clrsetbits_32(rcc_base + RCC_DDRITFCR, 2281 RCC_DDRITFCR_DDRCKMOD_MASK, 2282 RCC_DDRITFCR_DDRCKMOD_SSR << 2283 RCC_DDRITFCR_DDRCKMOD_SHIFT); 2284 2285 return 0; 2286 } 2287 2288 static void stm32mp1_osc_clk_init(const char *name, 2289 enum stm32mp_osc_id index) 2290 { 2291 uint32_t frequency; 2292 2293 if (fdt_osc_read_freq(name, &frequency) == 0) { 2294 stm32mp1_osc[index] = frequency; 2295 } 2296 } 2297 2298 static void stm32mp1_osc_init(void) 2299 { 2300 enum stm32mp_osc_id i; 2301 2302 for (i = (enum stm32mp_osc_id)0 ; i < NB_OSC; i++) { 2303 stm32mp1_osc_clk_init(stm32mp_osc_node_label[i], i); 2304 } 2305 } 2306 2307 #ifdef STM32MP_SHARED_RESOURCES 2308 /* 2309 * Get the parent ID of the target parent clock, for tagging as secure 2310 * shared clock dependencies. 2311 */ 2312 static int get_parent_id_parent(unsigned int parent_id) 2313 { 2314 enum stm32mp1_parent_sel s = _UNKNOWN_SEL; 2315 enum stm32mp1_pll_id pll_id; 2316 uint32_t p_sel; 2317 uintptr_t rcc_base = stm32mp_rcc_base(); 2318 2319 switch (parent_id) { 2320 case _ACLK: 2321 case _PCLK4: 2322 case _PCLK5: 2323 s = _AXIS_SEL; 2324 break; 2325 case _PLL1_P: 2326 case _PLL1_Q: 2327 case _PLL1_R: 2328 pll_id = _PLL1; 2329 break; 2330 case _PLL2_P: 2331 case _PLL2_Q: 2332 case _PLL2_R: 2333 pll_id = _PLL2; 2334 break; 2335 case _PLL3_P: 2336 case _PLL3_Q: 2337 case _PLL3_R: 2338 pll_id = _PLL3; 2339 break; 2340 case _PLL4_P: 2341 case _PLL4_Q: 2342 case _PLL4_R: 2343 pll_id = _PLL4; 2344 break; 2345 case _PCLK1: 2346 case _PCLK2: 2347 case _HCLK2: 2348 case _HCLK6: 2349 case _CK_PER: 2350 case _CK_MPU: 2351 case _CK_MCU: 2352 case _USB_PHY_48: 2353 /* We do not expect to access these */ 2354 panic(); 2355 break; 2356 default: 2357 /* Other parents have no parent */ 2358 return -1; 2359 } 2360 2361 if (s != _UNKNOWN_SEL) { 2362 const struct stm32mp1_clk_sel *sel = clk_sel_ref(s); 2363 2364 p_sel = (mmio_read_32(rcc_base + sel->offset) >> sel->src) & 2365 sel->msk; 2366 2367 if (p_sel < sel->nb_parent) { 2368 return (int)sel->parent[p_sel]; 2369 } 2370 } else { 2371 const struct stm32mp1_clk_pll *pll = pll_ref(pll_id); 2372 2373 p_sel = mmio_read_32(rcc_base + pll->rckxselr) & 2374 RCC_SELR_REFCLK_SRC_MASK; 2375 2376 if (pll->refclk[p_sel] != _UNKNOWN_OSC_ID) { 2377 return (int)pll->refclk[p_sel]; 2378 } 2379 } 2380 2381 VERBOSE("No parent selected for %s\n", 2382 stm32mp1_clk_parent_name[parent_id]); 2383 2384 return -1; 2385 } 2386 2387 static void secure_parent_clocks(unsigned long parent_id) 2388 { 2389 int grandparent_id; 2390 2391 switch (parent_id) { 2392 case _PLL3_P: 2393 case _PLL3_Q: 2394 case _PLL3_R: 2395 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2396 break; 2397 2398 /* These clocks are always secure when RCC is secure */ 2399 case _ACLK: 2400 case _HCLK2: 2401 case _HCLK6: 2402 case _PCLK4: 2403 case _PCLK5: 2404 case _PLL1_P: 2405 case _PLL1_Q: 2406 case _PLL1_R: 2407 case _PLL2_P: 2408 case _PLL2_Q: 2409 case _PLL2_R: 2410 case _HSI: 2411 case _HSI_KER: 2412 case _LSI: 2413 case _CSI: 2414 case _CSI_KER: 2415 case _HSE: 2416 case _HSE_KER: 2417 case _HSE_KER_DIV2: 2418 case _HSE_RTC: 2419 case _LSE: 2420 break; 2421 2422 default: 2423 VERBOSE("Cannot secure parent clock %s\n", 2424 stm32mp1_clk_parent_name[parent_id]); 2425 panic(); 2426 } 2427 2428 grandparent_id = get_parent_id_parent(parent_id); 2429 if (grandparent_id >= 0) { 2430 secure_parent_clocks(grandparent_id); 2431 } 2432 } 2433 2434 void stm32mp1_register_clock_parents_secure(unsigned long clock_id) 2435 { 2436 int parent_id; 2437 2438 if (!stm32mp1_rcc_is_secure()) { 2439 return; 2440 } 2441 2442 switch (clock_id) { 2443 case PLL1: 2444 case PLL2: 2445 /* PLL1/PLL2 are always secure: nothing to do */ 2446 break; 2447 case PLL3: 2448 stm32mp_register_secure_periph(STM32MP1_SHRES_PLL3); 2449 break; 2450 case PLL4: 2451 ERROR("PLL4 cannot be secured\n"); 2452 panic(); 2453 break; 2454 default: 2455 /* Others are expected gateable clock */ 2456 parent_id = stm32mp1_clk_get_parent(clock_id); 2457 if (parent_id < 0) { 2458 INFO("No parent found for clock %lu\n", clock_id); 2459 } else { 2460 secure_parent_clocks(parent_id); 2461 } 2462 break; 2463 } 2464 } 2465 #endif /* STM32MP_SHARED_RESOURCES */ 2466 2467 void stm32mp1_clk_mcuss_protect(bool enable) 2468 { 2469 uintptr_t rcc_base = stm32mp_rcc_base(); 2470 2471 if (enable) { 2472 mmio_setbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2473 } else { 2474 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 2475 } 2476 } 2477 2478 static void sync_earlyboot_clocks_state(void) 2479 { 2480 unsigned int idx; 2481 const unsigned long secure_enable[] = { 2482 AXIDCG, 2483 BSEC, 2484 DDRC1, DDRC1LP, 2485 DDRC2, DDRC2LP, 2486 DDRCAPB, DDRPHYCAPB, DDRPHYCAPBLP, 2487 DDRPHYC, DDRPHYCLP, 2488 RTCAPB, 2489 TZC1, TZC2, 2490 TZPC, 2491 STGEN_K, 2492 }; 2493 2494 for (idx = 0U; idx < ARRAY_SIZE(secure_enable); idx++) { 2495 stm32mp_clk_enable(secure_enable[idx]); 2496 } 2497 } 2498 2499 static const struct clk_ops stm32mp_clk_ops = { 2500 .enable = stm32mp_clk_enable, 2501 .disable = stm32mp_clk_disable, 2502 .is_enabled = stm32mp_clk_is_enabled, 2503 .get_rate = stm32mp_clk_get_rate, 2504 .get_parent = stm32mp1_clk_get_parent, 2505 }; 2506 2507 int stm32mp1_clk_probe(void) 2508 { 2509 #if defined(IMAGE_BL32) 2510 if (!fdt_get_rcc_secure_state()) { 2511 mmio_write_32(stm32mp_rcc_base() + RCC_TZCR, 0U); 2512 } 2513 #endif 2514 2515 stm32mp1_osc_init(); 2516 2517 sync_earlyboot_clocks_state(); 2518 2519 clk_register(&stm32mp_clk_ops); 2520 2521 return 0; 2522 } 2523