1 /* 2 * Copyright (C) 2022-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 5 */ 6 7 #ifndef CLK_STM32_CORE_H 8 #define CLK_STM32_CORE_H 9 10 struct mux_cfg { 11 uint16_t offset; 12 uint8_t shift; 13 uint8_t width; 14 uint8_t bitrdy; 15 }; 16 17 struct gate_cfg { 18 uint16_t offset; 19 uint8_t bit_idx; 20 uint8_t set_clr; 21 }; 22 23 struct clk_div_table { 24 uint16_t val; 25 uint16_t div; 26 }; 27 28 struct div_cfg { 29 const struct clk_div_table *table; 30 uint16_t offset; 31 uint8_t shift; 32 uint8_t width; 33 uint8_t flags; 34 uint8_t bitrdy; 35 }; 36 37 struct parent_cfg { 38 const uint16_t *id_parents; 39 struct mux_cfg *mux; 40 uint8_t num_parents; 41 }; 42 43 struct stm32_clk_priv; 44 45 struct stm32_clk_ops { 46 unsigned long (*recalc_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate); 47 int (*get_parent)(struct stm32_clk_priv *priv, int id); 48 int (*set_rate)(struct stm32_clk_priv *priv, int id, unsigned long rate, 49 unsigned long prate); 50 int (*enable)(struct stm32_clk_priv *priv, int id); 51 void (*disable)(struct stm32_clk_priv *priv, int id); 52 bool (*is_enabled)(struct stm32_clk_priv *priv, int id); 53 void (*init)(struct stm32_clk_priv *priv, int id); 54 }; 55 56 struct clk_stm32 { 57 uint16_t binding; 58 uint16_t parent; 59 uint8_t ops; 60 uint8_t flags; 61 void *clock_cfg; 62 }; 63 64 struct stm32_clk_priv { 65 uintptr_t base; 66 const uint32_t num; 67 const struct clk_stm32 *clks; 68 const struct parent_cfg *parents; 69 const uint32_t nb_parents; 70 const struct gate_cfg *gates; 71 const uint32_t nb_gates; 72 const struct div_cfg *div; 73 const uint32_t nb_div; 74 struct clk_oscillator_data *osci_data; 75 const uint32_t nb_osci_data; 76 uint8_t *gate_refcounts; 77 void *pdata; 78 const struct stm32_clk_ops **ops_array; 79 }; 80 81 struct stm32_clk_bypass { 82 uint16_t offset; 83 uint8_t bit_byp; 84 uint8_t bit_digbyp; 85 }; 86 87 struct stm32_clk_css { 88 uint16_t offset; 89 uint8_t bit_css; 90 }; 91 92 struct stm32_clk_drive { 93 uint16_t offset; 94 uint8_t drv_shift; 95 uint8_t drv_width; 96 uint8_t drv_default; 97 }; 98 99 struct clk_oscillator_data { 100 const char *name; 101 struct stm32_clk_bypass *bypass; 102 struct stm32_clk_css *css; 103 struct stm32_clk_drive *drive; 104 unsigned long frequency; 105 uint16_t id_clk; 106 uint16_t gate_id; 107 uint16_t gate_rdy_id; 108 109 }; 110 111 struct clk_fixed_rate { 112 const char *name; 113 unsigned long fixed_rate; 114 }; 115 116 struct clk_gate_cfg { 117 uint32_t offset; 118 uint8_t bit_idx; 119 }; 120 121 /* CLOCK FLAGS */ 122 #define CLK_IS_CRITICAL BIT(0) 123 #define CLK_IGNORE_UNUSED BIT(1) 124 #define CLK_SET_RATE_PARENT BIT(2) 125 126 #define CLK_DIVIDER_ONE_BASED BIT(0) 127 #define CLK_DIVIDER_POWER_OF_TWO BIT(1) 128 #define CLK_DIVIDER_ALLOW_ZERO BIT(2) 129 #define CLK_DIVIDER_HIWORD_MASK BIT(3) 130 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4) 131 #define CLK_DIVIDER_READ_ONLY BIT(5) 132 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6) 133 #define CLK_DIVIDER_BIG_ENDIAN BIT(7) 134 135 #define MUX_MAX_PARENTS U(0x8000) 136 #define MUX_PARENT_MASK GENMASK(14, 0) 137 #define MUX_FLAG U(0x8000) 138 #define MUX(mux) ((mux) | MUX_FLAG) 139 140 #define NO_GATE 0 141 #define _NO_ID UINT16_MAX 142 #define CLK_IS_ROOT UINT16_MAX 143 #define MUX_NO_BIT_RDY UINT8_MAX 144 #define DIV_NO_BIT_RDY UINT8_MAX 145 146 #define MASK_WIDTH_SHIFT(_width, _shift) \ 147 GENMASK(((_width) + (_shift) - 1U), (_shift)) 148 149 int clk_stm32_init(struct stm32_clk_priv *priv, uintptr_t base); 150 void clk_stm32_enable_critical_clocks(void); 151 152 struct stm32_clk_priv *clk_stm32_get_priv(void); 153 154 int clk_get_index(struct stm32_clk_priv *priv, unsigned long binding_id); 155 const struct clk_stm32 *_clk_get(struct stm32_clk_priv *priv, int id); 156 157 void clk_oscillator_set_bypass(struct stm32_clk_priv *priv, int id, bool digbyp, bool bypass); 158 void clk_oscillator_set_drive(struct stm32_clk_priv *priv, int id, uint8_t lsedrv); 159 void clk_oscillator_set_css(struct stm32_clk_priv *priv, int id, bool css); 160 161 int _clk_stm32_gate_wait_ready(struct stm32_clk_priv *priv, uint16_t gate_id, bool ready_on); 162 163 int clk_oscillator_wait_ready(struct stm32_clk_priv *priv, int id, bool ready_on); 164 int clk_oscillator_wait_ready_on(struct stm32_clk_priv *priv, int id); 165 int clk_oscillator_wait_ready_off(struct stm32_clk_priv *priv, int id); 166 167 int clk_stm32_get_counter(unsigned long binding_id); 168 169 void _clk_stm32_gate_disable(struct stm32_clk_priv *priv, uint16_t gate_id); 170 int _clk_stm32_gate_enable(struct stm32_clk_priv *priv, uint16_t gate_id); 171 172 int _clk_stm32_set_parent(struct stm32_clk_priv *priv, int id, int src_id); 173 int _clk_stm32_set_parent_by_index(struct stm32_clk_priv *priv, int clk, int sel); 174 175 int _clk_stm32_get_parent(struct stm32_clk_priv *priv, int id); 176 int _clk_stm32_get_parent_by_index(struct stm32_clk_priv *priv, int clk_id, int idx); 177 int _clk_stm32_get_parent_index(struct stm32_clk_priv *priv, int clk_id); 178 179 unsigned long _clk_stm32_get_rate(struct stm32_clk_priv *priv, int id); 180 unsigned long _clk_stm32_get_parent_rate(struct stm32_clk_priv *priv, int id); 181 182 bool _stm32_clk_is_flags(struct stm32_clk_priv *priv, int id, uint8_t flag); 183 184 int _clk_stm32_enable(struct stm32_clk_priv *priv, int id); 185 void _clk_stm32_disable(struct stm32_clk_priv *priv, int id); 186 187 int clk_stm32_enable_call_ops(struct stm32_clk_priv *priv, uint16_t id); 188 void clk_stm32_disable_call_ops(struct stm32_clk_priv *priv, uint16_t id); 189 190 bool _clk_stm32_is_enabled(struct stm32_clk_priv *priv, int id); 191 192 int _clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int div_id, 193 unsigned long rate, unsigned long parent_rate); 194 195 int clk_stm32_divider_set_rate(struct stm32_clk_priv *priv, int id, unsigned long rate, 196 unsigned long prate); 197 198 unsigned long _clk_stm32_divider_recalc(struct stm32_clk_priv *priv, 199 int div_id, 200 unsigned long prate); 201 202 unsigned long clk_stm32_divider_recalc(struct stm32_clk_priv *priv, int idx, 203 unsigned long prate); 204 205 int clk_stm32_gate_enable(struct stm32_clk_priv *priv, int idx); 206 void clk_stm32_gate_disable(struct stm32_clk_priv *priv, int idx); 207 208 bool _clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int gate_id); 209 bool clk_stm32_gate_is_enabled(struct stm32_clk_priv *priv, int idx); 210 211 uint32_t clk_stm32_div_get_value(struct stm32_clk_priv *priv, int div_id); 212 int clk_stm32_set_div(struct stm32_clk_priv *priv, uint32_t div_id, uint32_t value); 213 int clk_mux_set_parent(struct stm32_clk_priv *priv, uint16_t pid, uint8_t sel); 214 int clk_mux_get_parent(struct stm32_clk_priv *priv, uint32_t mux_id); 215 216 int stm32_clk_parse_fdt_by_name(void *fdt, int node, const char *name, uint32_t *tab, uint32_t *nb); 217 218 #ifdef CFG_STM32_CLK_DEBUG 219 void clk_stm32_display_clock_info(void); 220 #endif 221 222 struct clk_stm32_div_cfg { 223 uint8_t id; 224 }; 225 226 #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ 227 [(idx)] = (struct clk_stm32){ \ 228 .binding = (_binding),\ 229 .parent = (_parent),\ 230 .flags = (_flags),\ 231 .clock_cfg = &(struct clk_stm32_div_cfg){\ 232 .id = (_div_id),\ 233 },\ 234 .ops = STM32_DIVIDER_OPS,\ 235 } 236 237 struct clk_stm32_gate_cfg { 238 uint8_t id; 239 }; 240 241 #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ 242 [(idx)] = (struct clk_stm32){ \ 243 .binding = (_binding),\ 244 .parent = (_parent),\ 245 .flags = (_flags),\ 246 .clock_cfg = &(struct clk_stm32_gate_cfg){\ 247 .id = (_gate_id),\ 248 },\ 249 .ops = STM32_GATE_OPS,\ 250 } 251 252 struct fixed_factor_cfg { 253 uint8_t mult; 254 uint8_t div; 255 }; 256 257 unsigned long fixed_factor_recalc_rate(struct stm32_clk_priv *priv, 258 int _idx, unsigned long prate); 259 260 #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ 261 [(idx)] = (struct clk_stm32){ \ 262 .binding = (_idx),\ 263 .parent = (_parent),\ 264 .clock_cfg = &(struct fixed_factor_cfg){\ 265 .mult = (_mult),\ 266 .div = (_div),\ 267 },\ 268 .ops = FIXED_FACTOR_OPS,\ 269 } 270 271 #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ 272 [(idx)] = (struct clk_stm32){ \ 273 .binding = (_binding),\ 274 .parent = (_parent),\ 275 .flags = (_flags),\ 276 .clock_cfg = &(struct clk_gate_cfg){\ 277 .offset = (_offset),\ 278 .bit_idx = (_bit_idx),\ 279 },\ 280 .ops = GATE_OPS,\ 281 } 282 283 #define STM32_MUX(idx, _binding, _mux_id, _flags) \ 284 [(idx)] = (struct clk_stm32){ \ 285 .binding = (_binding),\ 286 .parent = (MUX(_mux_id)),\ 287 .flags = (_flags),\ 288 .clock_cfg = NULL,\ 289 .ops = STM32_MUX_OPS\ 290 } 291 292 struct clk_timer_cfg { 293 uint32_t apbdiv; 294 uint32_t timpre; 295 }; 296 297 #define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ 298 [(idx)] = (struct clk_stm32){ \ 299 .binding = (_idx),\ 300 .parent = (_parent),\ 301 .flags = (CLK_SET_RATE_PARENT | (_flags)),\ 302 .clock_cfg = &(struct clk_timer_cfg){\ 303 .apbdiv = (_apbdiv),\ 304 .timpre = (_timpre),\ 305 },\ 306 .ops = STM32_TIMER_OPS,\ 307 } 308 309 struct clk_stm32_fixed_rate_cfg { 310 unsigned long rate; 311 }; 312 313 #define CLK_FIXED_RATE(idx, _binding, _rate) \ 314 [(idx)] = (struct clk_stm32){ \ 315 .binding = (_binding),\ 316 .parent = (CLK_IS_ROOT),\ 317 .clock_cfg = &(struct clk_stm32_fixed_rate_cfg){\ 318 .rate = (_rate),\ 319 },\ 320 .ops = STM32_FIXED_RATE_OPS,\ 321 } 322 323 #define BYPASS(_offset, _bit_byp, _bit_digbyp) &(struct stm32_clk_bypass){\ 324 .offset = (_offset),\ 325 .bit_byp = (_bit_byp),\ 326 .bit_digbyp = (_bit_digbyp),\ 327 } 328 329 #define CSS(_offset, _bit_css) &(struct stm32_clk_css){\ 330 .offset = (_offset),\ 331 .bit_css = (_bit_css),\ 332 } 333 334 #define DRIVE(_offset, _shift, _width, _default) &(struct stm32_clk_drive){\ 335 .offset = (_offset),\ 336 .drv_shift = (_shift),\ 337 .drv_width = (_width),\ 338 .drv_default = (_default),\ 339 } 340 341 #define OSCILLATOR(idx_osc, _id, _name, _gate_id, _gate_rdy_id, _bypass, _css, _drive) \ 342 [(idx_osc)] = (struct clk_oscillator_data){\ 343 .name = (_name),\ 344 .id_clk = (_id),\ 345 .gate_id = (_gate_id),\ 346 .gate_rdy_id = (_gate_rdy_id),\ 347 .bypass = (_bypass),\ 348 .css = (_css),\ 349 .drive = (_drive),\ 350 } 351 352 struct clk_oscillator_data *clk_oscillator_get_data(struct stm32_clk_priv *priv, int id); 353 354 void clk_stm32_osc_init(struct stm32_clk_priv *priv, int id); 355 bool clk_stm32_osc_gate_is_enabled(struct stm32_clk_priv *priv, int id); 356 int clk_stm32_osc_gate_enable(struct stm32_clk_priv *priv, int id); 357 void clk_stm32_osc_gate_disable(struct stm32_clk_priv *priv, int id); 358 359 struct stm32_osc_cfg { 360 uint8_t osc_id; 361 }; 362 363 #define CLK_OSC(idx, _idx, _parent, _osc_id) \ 364 [(idx)] = (struct clk_stm32){ \ 365 .binding = (_idx),\ 366 .parent = (_parent),\ 367 .flags = CLK_IS_CRITICAL,\ 368 .clock_cfg = &(struct stm32_osc_cfg){\ 369 .osc_id = (_osc_id),\ 370 },\ 371 .ops = STM32_OSC_OPS,\ 372 } 373 374 #define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ 375 [(idx)] = (struct clk_stm32){ \ 376 .binding = (_idx),\ 377 .parent = (_parent),\ 378 .flags = CLK_IS_CRITICAL,\ 379 .clock_cfg = &(struct stm32_osc_cfg){\ 380 .osc_id = (_osc_id),\ 381 },\ 382 .ops = STM32_OSC_NOGATE_OPS,\ 383 } 384 385 extern const struct stm32_clk_ops clk_mux_ops; 386 extern const struct stm32_clk_ops clk_stm32_divider_ops; 387 extern const struct stm32_clk_ops clk_stm32_gate_ops; 388 extern const struct stm32_clk_ops clk_fixed_factor_ops; 389 extern const struct stm32_clk_ops clk_gate_ops; 390 extern const struct stm32_clk_ops clk_timer_ops; 391 extern const struct stm32_clk_ops clk_stm32_fixed_rate_ops; 392 extern const struct stm32_clk_ops clk_stm32_osc_ops; 393 extern const struct stm32_clk_ops clk_stm32_osc_nogate_ops; 394 395 enum { 396 NO_OPS, 397 FIXED_FACTOR_OPS, 398 GATE_OPS, 399 STM32_MUX_OPS, 400 STM32_DIVIDER_OPS, 401 STM32_GATE_OPS, 402 STM32_TIMER_OPS, 403 STM32_FIXED_RATE_OPS, 404 STM32_OSC_OPS, 405 STM32_OSC_NOGATE_OPS, 406 407 STM32_LAST_OPS 408 }; 409 410 #endif /* CLK_STM32_CORE_H */ 411