fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Ch

fix(intel): update the size with addition 0x8000 0000 base

The FPGA_CONFIG_SIZE is actually the end address of FPGA_CONFIG_ADDR
Thus, we need to add in the DDR base address which is 0x8000 0000.

Change-Id: I177596243e0616c6eadc2fa388e85e28692dc8f7
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4

fix(intel): fix bridge enable and disable function

1. hps reset and reboot spec is missing ack clear status step
2. software workaround for bridge timeout
3. f2sdram bridge quick write thru failed
4. bridge timeout workaround for F2SOC and F2SDRAM


Change-Id: Ide4210ff862531f82e083633af385b559ffbe16b
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df

fix(intel): update outdated code for Linux direct boot

1. Update emif rsthdshk macro
2. Update mailbox return status
3. Update bridge return status

Change-Id: I33905508aceb258ac8759c10079b2af977df0e0a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

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Merge "feat(sctlr2): add support for FEAT_SCTLR2" into integration

Merge "feat(the): add support for FEAT_THE" into integration

Merge "fix(versal2): correct the UFS clock rates" into integration

Merge changes from topic "xlnx_fix_plat_console_changes" into integration

* changes:
feat(xilinx): add none console
feat(versal2): add dtb & runtime console
feat(versal-net): add DTB console t

Merge changes from topic "xlnx_fix_plat_console_changes" into integration

* changes:
feat(xilinx): add none console
feat(versal2): add dtb & runtime console
feat(versal-net): add DTB console to platform.mk
feat(versal-net): dedicate console for boot and runtime
feat(versal): add DTB console to platform.mk
feat(versal): dedicate console for boot and runtime
refactor(xilinx): register runtime console directly
refactor(xilinx): console registration through console holder structure
feat(zynqmp): add DTB console to platform.mk
feat(zynqmp): dedicate console for boot and runtime
fix(xilinx): dcc to support runtime console scope
refactor(xilinx): create generic function for DT console
refactor(xilinx): rename setup_runtime_console to generic
chore(xilinx): rename console variables
chore(xilinx): rename runtime console to DT console

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chore(cpus): optimise runtime errata applications

The errata framework has a helper to invoke workarounds, complete with a
cpu rev_var check. We can use that directly instead of the
apply_cpu_pwr_dw

chore(cpus): optimise runtime errata applications

The errata framework has a helper to invoke workarounds, complete with a
cpu rev_var check. We can use that directly instead of the
apply_cpu_pwr_dwn_errata to save on some code, as well as an extra
branch. It's also more readable.

Also, apply_erratum invocation in cpu files don't need to check the
rev_var as that was already done by the cpu_ops dispatcher for us to end
up in the file.

Finally, X2 erratum 2768515 only applies in the powerdown sequence, i.e.
at runtime. It doesn't achieve anything at reset, so we can label it
accordingly.

Change-Id: I02f9dd7d0619feb54c870938ea186be5e3a6ca7b
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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chore(commitlint): tell editors commit line lengths are 72 characters

The repository obeys an 100 character soft limit for source lines.
However, commit messages generally have lines shorter than 72

chore(commitlint): tell editors commit line lengths are 72 characters

The repository obeys an 100 character soft limit for source lines.
However, commit messages generally have lines shorter than 72 characters
to make gerrit print them without wrapping.

Annoyingly, the editorconfig can't express this and the 100 character
limit applies to commit messages, requiring manual formatting. Luckily,
when writing commit messages the file `.git/COMMIT_EDITMSG` is open. So
we can set its line length to be 72 characters.

Change-Id: Id96dcab8ce500ee965e53dd53a51c6761811440e
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

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refactor(delay-timer): add timer callback functions

In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header

refactor(delay-timer): add timer callback functions

In order to avoid separate platform definitions when not using the
default timer functions, it is better to move these functions out of the
header file and into the source files, so that they can be built if
needed.

Move timer functions from delay_timer.h into generic_delay_timer.c. Add
them as callback functions which are then called in delay_timer.c.

Change-Id: I96a1eac8948b1a7b1e481899b67a083db4c9b97d
Signed-off-by: Abhi Singh <abhi.singh@arm.com>

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Merge "feat(rmmd): el3 token sign during attestation" into integration

Merge "docs: update TF-A May'25 release dates" into integration

docs: update TF-A May'25 release dates

Tentatively updating the plan for TF-A v2.13 release in May'25.

Change-Id: I98abe5f72901b71179a1efe3762046756d5ab6ac
Signed-off-by: Govindraj Raja <govindraj.

docs: update TF-A May'25 release dates

Tentatively updating the plan for TF-A v2.13 release in May'25.

Change-Id: I98abe5f72901b71179a1efe3762046756d5ab6ac
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

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feat(rmmd): el3 token sign during attestation

Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable

feat(rmmd): el3 token sign during attestation

Add required SMCs by RMM to push attestation signing requests to EL3
and get responses. EL3 may then choose to push these requests to a HES
as suitable for a platform. This patch also supports the new
RMM_EL3_FEATURES interface, that RMM can use to query for support for
HES based signing. The new interface exposes a feature register with
different bits defining different discoverable features. This new
interface is available starting the 0.4 version of the RMM-EL3
interface, causing the version to bump up. This patch also adds a
platform port for FVP that implements the platform hooks required to
enable the new SMCs, but it does not push to a HES and instead copies a
zeroed buffer in EL3.

Change-Id: I69c110252835122a9533e71bdcce10b5f2a686b2
Signed-off-by: Raghu Krishnamurthy <raghupathyk@nvidia.com>

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feat(context-mgmt): introduce EL3/root context

* This patch adds root context procedure to restore/configure
the registers, which are of importance during EL3 execution.

* EL3/Root context is a s

feat(context-mgmt): introduce EL3/root context

* This patch adds root context procedure to restore/configure
the registers, which are of importance during EL3 execution.

* EL3/Root context is a simple restore operation that overwrites
the following bits: (MDCR_EL3.SDD, SCR_EL3.{EA, SIF}, PMCR_EL0.DP
PSTATE.DIT) while the execution is in EL3.

* It ensures EL3 world maintains its own settings distinct
from other worlds (NS/Realm/SWd). With this in place, the EL3
system register settings is no longer influenced by settings of
incoming worlds. This allows the EL3/Root world to access features
for its own execution at EL3 (eg: Pauth).

* It should be invoked at cold and warm boot entry paths and also
at all the possible exception handlers routing to EL3 at runtime.
Cold and warm boot paths are handled by including setup_el3_context
function in "el3_entrypoint_common" macro, which gets invoked in
both the entry paths.

* At runtime, el3_context is setup at the stage, while we get prepared
to enter into EL3 via "prepare_el3_entry" routine.

Change-Id: I5c090978c54a53bc1c119d1bc5fa77cd8813cdc2
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(el3-runtime): correct CASSERT for cpu data size

Build breaks when EL3_EXCEPTION_HANDLING option is enabled. The
CPU_DATA_SIZE macro does not consider the size required to save the
ehf_data field

fix(el3-runtime): correct CASSERT for cpu data size

Build breaks when EL3_EXCEPTION_HANDLING option is enabled. The
CPU_DATA_SIZE macro does not consider the size required to save the
ehf_data field of cpu_data structure.

include/lib/el3_runtime/cpu_data.h:163:17: error: size of array
'assert_cpu_data_size_mismatch' is negative
assert_cpu_data_size_mismatch);

This patch adds support to consider ehf_data field to calculate the
CPU_DATA_SIZE macro. Also adds relevant checks and asserts if the
ehf_data field is not considered.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@arm.com>
Change-Id: I3c11b2982f4a612ce28e46848b5c5035a8f8efc2

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refactor(bl): remove un-necessary variable

Remove un-necessary variable 'is_parent_image'
used in the 'load_auth_image_recursive' function.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com

refactor(bl): remove un-necessary variable

Remove un-necessary variable 'is_parent_image'
used in the 'load_auth_image_recursive' function.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Ie66f7e3cc82dd443da0b75d55adf3ae7e15b5f99

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Merge changes from topic "add-qcbor-dependency" into integration

* changes:
chore(tc): increase stack size with 0x100 bytes
chore(tc): link QCBOR library to the platform test

Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

* changes:
feat(tc): move flash device to own node
feat(tc): remove static memory used for fwu
fix(tc): correct NS timer frame ID f

Merge changes I19503ac3,I0fb128a4,I287ab9c3 into integration

* changes:
feat(tc): move flash device to own node
feat(tc): remove static memory used for fwu
fix(tc): correct NS timer frame ID for TC

show more ...

Merge changes Ic79429c3,Ie2d5272e,Iec73f9c5,Ie63f48dc,I951da75a, ... into integration

* changes:
feat(stm32mp2): load FW binaries to DDR
feat(stm32mp2-fdts): update STM32MP257F-EV1 DT
feat(fdt

Merge changes Ic79429c3,Ie2d5272e,Iec73f9c5,Ie63f48dc,I951da75a, ... into integration

* changes:
feat(stm32mp2): load FW binaries to DDR
feat(stm32mp2-fdts): update STM32MP257F-EV1 DT
feat(fdts): add DDR4 files for STM32MP2
feat(stm32mp25-fdts): add DDRCTRL and DDRPHY settings in DDR node
feat(stm32mp25-fdts): add DDR power supplies
feat(stm32mp2-fdts): add memory node
feat(stm32mp2): enable DDR driver

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feat(xilinx): add none console

None console does not register boot and runtime console.
User will not observe any console logs.

Change-Id: I39877c900f399ae7cffc1bb599b30c7a23888fc8
Signed-off-by: M

feat(xilinx): add none console

None console does not register boot and runtime console.
User will not observe any console logs.

Change-Id: I39877c900f399ae7cffc1bb599b30c7a23888fc8
Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(versal2): add dtb & runtime console

Modified platform.mk and bl31_setup to
invoke setup_console and runtime_console
to support dtb console parsing and runtime.

Change-Id: I68c2fffd90e38274cfa

feat(versal2): add dtb & runtime console

Modified platform.mk and bl31_setup to
invoke setup_console and runtime_console
to support dtb console parsing and runtime.

Change-Id: I68c2fffd90e38274cfad4f85dd51c722fae0ee89
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(versal-net): add DTB console to platform.mk

In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_NET_CONSOLE_ID_dtb, will
be introduced to check DT console.Use

feat(versal-net): add DTB console to platform.mk

In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_NET_CONSOLE_ID_dtb, will
be introduced to check DT console.Users will have the
option to select VERSAL_NET_CONSOLE to dtb, which will run
from the DDR address and OCM. The address XILINX_OF_BOARD_DTB_ADDR
needs to be provided. This configuration will register the
DT console in TF-A

Change-Id: I530492c3f48705387e50895aef4bf229a82d350d
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(versal-net): dedicate console for boot and runtime

Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag

feat(versal-net): dedicate console for boot and runtime

Introduce a build-time parameter (CONSOLE_RUNTIME) to select
separate runtime console options. For boot-time console, remove
the runtime flag and add a boot/crash flag. Additionally,
introduce an RT_CONSOLE_IS macro to check different UART types.

Implement a common function, console_runtime_init(), to initialize
the runtime console. Ensure that all platforms have access to
this feature.

The current implementation utilizes a single console for boot,
crash, and runtime. Make sure that the dedicated console integrates
into runtime and crash scenarios

Change-Id: I49b8554c0f067c85eb693e039a0cf17c5e6794ce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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feat(versal): add DTB console to platform.mk

In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_CONSOLE_ID_dtb, will
be introduced to check DT console.Users will

feat(versal): add DTB console to platform.mk

In the platform.mk file, new console types named dtb
are to be created a macro, VERSAL_CONSOLE_ID_dtb, will
be introduced to check DT console.Users will have the
option to select VERSAL_CONSOLE to dtb, which will run
from the DDR address and OCM. The address XILINX_OF_BOARD_DTB_ADDR
needs to be provided. This configuration will register the
DT console in TF-A.

Change-Id: Iee0ed2d5bb73c833f34809699203622b912cdbd7
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
Signed-off-by: Maheedhar Bollapalli <MaheedharSai.Bollapalli@amd.com>

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