1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <drivers/arm/pl061_gpio.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <lib/transfer_list.h> 13 #include <plat/common/platform.h> 14 #if ENABLE_RME 15 #include <qemu_pas_def.h> 16 #endif 17 18 #include "qemu_private.h" 19 20 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 21 BL31_BASE, \ 22 BL31_END - BL31_BASE, \ 23 MT_MEMORY | MT_RW | EL3_PAS) 24 #define MAP_BL31_RO MAP_REGION_FLAT( \ 25 BL_CODE_BASE, \ 26 BL_CODE_END - BL_CODE_BASE, \ 27 MT_CODE | EL3_PAS), \ 28 MAP_REGION_FLAT( \ 29 BL_RO_DATA_BASE, \ 30 BL_RO_DATA_END \ 31 - BL_RO_DATA_BASE, \ 32 MT_RO_DATA | EL3_PAS) 33 34 #if USE_COHERENT_MEM 35 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 36 BL_COHERENT_RAM_BASE, \ 37 BL_COHERENT_RAM_END \ 38 - BL_COHERENT_RAM_BASE, \ 39 MT_DEVICE | MT_RW | EL3_PAS) 40 #endif 41 42 /* 43 * Placeholder variables for copying the arguments that have been passed to 44 * BL3-1 from BL2. 45 */ 46 static entry_point_info_t bl32_image_ep_info; 47 static entry_point_info_t bl33_image_ep_info; 48 #if ENABLE_RME 49 static entry_point_info_t rmm_image_ep_info; 50 #endif 51 static struct transfer_list_header *bl31_tl; 52 53 /******************************************************************************* 54 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 55 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 56 * they are lost (potentially). This needs to be done before the MMU is 57 * initialized so that the memory layout can be used while creating page 58 * tables. BL2 has flushed this information to memory, so we are guaranteed 59 * to pick up good data. 60 ******************************************************************************/ 61 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 62 u_register_t arg2, u_register_t arg3) 63 { 64 /* Initialize the console to provide early debug support */ 65 qemu_console_init(); 66 67 /* Platform names have to be lowercase. */ 68 #ifdef PLAT_qemu_sbsa 69 sip_svc_init(); 70 #endif 71 72 /* 73 * Check params passed from BL2 74 */ 75 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 76 77 assert(params_from_bl2); 78 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 79 assert(params_from_bl2->h.version >= VERSION_2); 80 81 bl_params_node_t *bl_params = params_from_bl2->head; 82 83 /* 84 * Copy BL33, BL32 and RMM (if present), entry point information. 85 * They are stored in Secure RAM, in BL2's address space. 86 */ 87 while (bl_params) { 88 if (bl_params->image_id == BL32_IMAGE_ID) 89 bl32_image_ep_info = *bl_params->ep_info; 90 91 #if ENABLE_RME 92 if (bl_params->image_id == RMM_IMAGE_ID) 93 rmm_image_ep_info = *bl_params->ep_info; 94 #endif 95 96 if (bl_params->image_id == BL33_IMAGE_ID) 97 bl33_image_ep_info = *bl_params->ep_info; 98 99 bl_params = bl_params->next_params_info; 100 } 101 102 if (!bl33_image_ep_info.pc) 103 panic(); 104 #if ENABLE_RME 105 if (!rmm_image_ep_info.pc) 106 panic(); 107 #endif 108 109 if (TRANSFER_LIST && arg1 == (TRANSFER_LIST_SIGNATURE | 110 REGISTER_CONVENTION_VERSION_MASK) && 111 transfer_list_check_header((void *)arg3) != TL_OPS_NON) { 112 bl31_tl = (void *)arg3; /* saved TL address from BL2 */ 113 } 114 } 115 116 #if ENABLE_RME 117 static void bl31_plat_gpt_setup(void) 118 { 119 /* 120 * The GPT library might modify the gpt regions structure to optimize 121 * the layout, so the array cannot be constant. 122 */ 123 pas_region_t pas_regions[] = { 124 QEMU_PAS_ROOT, 125 QEMU_PAS_SECURE, 126 QEMU_PAS_GPTS, 127 QEMU_PAS_NS0, 128 QEMU_PAS_REALM, 129 QEMU_PAS_NS1, 130 }; 131 132 /* 133 * Initialize entire protected space to GPT_GPI_ANY. With each L0 entry 134 * covering 1GB (currently the only supported option), then covering 135 * 256TB of RAM (48-bit PA) would require a 2MB L0 region. At the 136 * moment we use a 8KB table, which covers 1TB of RAM (40-bit PA). 137 */ 138 if (gpt_init_l0_tables(PLATFORM_GPCCR_PPS, PLAT_QEMU_L0_GPT_BASE, 139 PLAT_QEMU_L0_GPT_SIZE + 140 PLAT_QEMU_GPT_BITLOCK_SIZE) < 0) { 141 ERROR("gpt_init_l0_tables() failed!\n"); 142 panic(); 143 } 144 145 /* Carve out defined PAS ranges. */ 146 if (gpt_init_pas_l1_tables(GPCCR_PGS_4K, 147 PLAT_QEMU_L1_GPT_BASE, 148 PLAT_QEMU_L1_GPT_SIZE, 149 pas_regions, 150 (unsigned int)(sizeof(pas_regions) / 151 sizeof(pas_region_t))) < 0) { 152 ERROR("gpt_init_pas_l1_tables() failed!\n"); 153 panic(); 154 } 155 156 INFO("Enabling Granule Protection Checks\n"); 157 if (gpt_enable() < 0) { 158 ERROR("gpt_enable() failed!\n"); 159 panic(); 160 } 161 } 162 #endif 163 164 void bl31_plat_arch_setup(void) 165 { 166 const mmap_region_t bl_regions[] = { 167 MAP_BL31_TOTAL, 168 MAP_BL31_RO, 169 #if USE_COHERENT_MEM 170 MAP_BL_COHERENT_RAM, 171 #endif 172 #if ENABLE_RME 173 MAP_GPT_L0_REGION, 174 MAP_GPT_L1_REGION, 175 MAP_RMM_SHARED_MEM, 176 #endif 177 {0} 178 }; 179 180 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 181 182 enable_mmu_el3(0); 183 184 #if ENABLE_RME 185 /* Initialise and enable granule protection after MMU. */ 186 bl31_plat_gpt_setup(); 187 188 /* 189 * Initialise Granule Protection library and enable GPC for the primary 190 * processor. The tables have already been initialized by a previous BL 191 * stage, so there is no need to provide any PAS here. This function 192 * sets up pointers to those tables. 193 */ 194 if (gpt_runtime_init() < 0) { 195 ERROR("gpt_runtime_init() failed!\n"); 196 panic(); 197 } 198 #endif /* ENABLE_RME */ 199 200 } 201 202 static void qemu_gpio_init(void) 203 { 204 #ifdef SECURE_GPIO_BASE 205 pl061_gpio_init(); 206 pl061_gpio_register(SECURE_GPIO_BASE, 0); 207 #endif 208 } 209 210 void bl31_platform_setup(void) 211 { 212 plat_qemu_gic_init(); 213 qemu_gpio_init(); 214 } 215 216 unsigned int plat_get_syscnt_freq2(void) 217 { 218 return read_cntfrq_el0(); 219 } 220 221 /******************************************************************************* 222 * Return a pointer to the 'entry_point_info' structure of the next image 223 * for the security state specified. BL3-3 corresponds to the non-secure 224 * image type while BL3-2 corresponds to the secure image type. A NULL 225 * pointer is returned if the image does not exist. 226 ******************************************************************************/ 227 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 228 { 229 entry_point_info_t *next_image_info; 230 231 assert(sec_state_is_valid(type)); 232 if (type == NON_SECURE) { 233 next_image_info = &bl33_image_ep_info; 234 } 235 #if ENABLE_RME 236 else if (type == REALM) { 237 next_image_info = &rmm_image_ep_info; 238 } 239 #endif 240 else { 241 next_image_info = &bl32_image_ep_info; 242 } 243 244 /* 245 * None of the images on the ARM development platforms can have 0x0 246 * as the entrypoint 247 */ 248 if (next_image_info->pc) 249 return next_image_info; 250 else 251 return NULL; 252 } 253 254 void bl31_plat_runtime_setup(void) 255 { 256 #if TRANSFER_LIST 257 if (bl31_tl) { 258 /* 259 * update the TL from S to NS memory before jump to BL33 260 * to reflect all changes in TL done by BL32 261 */ 262 memcpy((void *)FW_NS_HANDOFF_BASE, bl31_tl, bl31_tl->max_size); 263 } 264 #endif 265 266 console_flush(); 267 console_switch_state(CONSOLE_FLAG_RUNTIME); 268 } 269