1 /* 2 * Copyright (c) 2023, Linaro Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/fdt_wrappers.h> 10 #include <common/runtime_svc.h> 11 #include <libfdt.h> 12 #include <smccc_helpers.h> 13 14 /* default platform version is 0.0 */ 15 static int platform_version_major; 16 static int platform_version_minor; 17 18 #define SMC_FASTCALL 0x80000000 19 #define SMC64_FUNCTION (SMC_FASTCALL | 0x40000000) 20 #define SIP_FUNCTION (SMC64_FUNCTION | 0x02000000) 21 #define SIP_FUNCTION_ID(n) (SIP_FUNCTION | (n)) 22 23 /* 24 * We do not use SMCCC_ARCH_SOC_ID here because qemu_sbsa is virtual platform 25 * which uses SoC present in QEMU. And they can change on their own while we 26 * need version of whole 'virtual hardware platform'. 27 */ 28 #define SIP_SVC_VERSION SIP_FUNCTION_ID(1) 29 #define SIP_SVC_GET_GIC SIP_FUNCTION_ID(100) 30 #define SIP_SVC_GET_GIC_ITS SIP_FUNCTION_ID(101) 31 #define SIP_SVC_GET_CPU_COUNT SIP_FUNCTION_ID(200) 32 #define SIP_SVC_GET_CPU_NODE SIP_FUNCTION_ID(201) 33 #define SIP_SVC_GET_CPU_TOPOLOGY SIP_FUNCTION_ID(202) 34 #define SIP_SVC_GET_MEMORY_NODE_COUNT SIP_FUNCTION_ID(300) 35 #define SIP_SVC_GET_MEMORY_NODE SIP_FUNCTION_ID(301) 36 37 static uint64_t gic_its_addr; 38 39 typedef struct { 40 uint32_t nodeid; 41 uint32_t mpidr; 42 } cpu_data; 43 44 typedef struct{ 45 uint32_t nodeid; 46 uint64_t addr_base; 47 uint64_t addr_size; 48 } memory_data; 49 50 /* 51 * sockets: the number of sockets on sbsa-ref platform. 52 * clusters: the number of clusters in one socket. 53 * cores: the number of cores in one cluster. 54 * threads: the number of threads in one core. 55 */ 56 typedef struct { 57 uint32_t sockets; 58 uint32_t clusters; 59 uint32_t cores; 60 uint32_t threads; 61 } cpu_topology; 62 63 struct qemu_platform_info { 64 uint32_t num_cpus; 65 uint32_t num_memnodes; 66 cpu_data cpu[PLATFORM_CORE_COUNT]; 67 cpu_topology cpu_topo; 68 memory_data memory[PLAT_MAX_MEM_NODES]; 69 }; 70 71 static struct qemu_platform_info dynamic_platform_info; 72 73 void sbsa_set_gic_bases(const uintptr_t gicd_base, const uintptr_t gicr_base); 74 uintptr_t sbsa_get_gicd(void); 75 uintptr_t sbsa_get_gicr(void); 76 77 /* 78 * QEMU provides us with minimal information about hardware platform using 79 * minimalistic DeviceTree. This is not a Linux DeviceTree. It is not even 80 * a firmware DeviceTree. 81 * 82 * It is information passed from QEMU to describe the information a hardware 83 * platform would have other mechanisms to discover at runtime, that are 84 * affected by the QEMU command line. 85 * 86 * Ultimately this device tree will be replaced by IPC calls to an emulated SCP. 87 * And when we do that, we won't then have to rewrite Normal world firmware to 88 * cope. 89 */ 90 91 static void read_cpu_topology_from_dt(void *dtb) 92 { 93 int node; 94 95 /* 96 * QEMU gives us this DeviceTree node when we config: 97 * -smp 16,sockets=2,clusters=2,cores=2,threads=2 98 * 99 * topology { 100 * threads = <0x02>; 101 * cores = <0x02>; 102 * clusters = <0x02>; 103 * sockets = <0x02>; 104 * }; 105 */ 106 107 node = fdt_path_offset(dtb, "/cpus/topology"); 108 if (node > 0) { 109 dynamic_platform_info.cpu_topo.sockets = 110 fdt_read_uint32_default(dtb, node, "sockets", 0); 111 dynamic_platform_info.cpu_topo.clusters = 112 fdt_read_uint32_default(dtb, node, "clusters", 0); 113 dynamic_platform_info.cpu_topo.cores = 114 fdt_read_uint32_default(dtb, node, "cores", 0); 115 dynamic_platform_info.cpu_topo.threads = 116 fdt_read_uint32_default(dtb, node, "threads", 0); 117 } 118 119 INFO("Cpu topology: sockets: %d, clusters: %d, cores: %d, threads: %d\n", 120 dynamic_platform_info.cpu_topo.sockets, 121 dynamic_platform_info.cpu_topo.clusters, 122 dynamic_platform_info.cpu_topo.cores, 123 dynamic_platform_info.cpu_topo.threads); 124 } 125 126 void read_cpuinfo_from_dt(void *dtb) 127 { 128 int node; 129 int prev; 130 int cpu = 0; 131 uintptr_t mpidr; 132 133 /* 134 * QEMU gives us this DeviceTree node: 135 * numa-node-id entries are only when NUMA config is used 136 * 137 * cpus { 138 * #size-cells = <0x00>; 139 * #address-cells = <0x02>; 140 * 141 * cpu@0 { 142 * numa-node-id = <0x00>; 143 * reg = <0x00 0x00>; 144 * }; 145 * 146 * cpu@1 { 147 * numa-node-id = <0x03>; 148 * reg = <0x00 0x01>; 149 * }; 150 * }; 151 */ 152 node = fdt_path_offset(dtb, "/cpus"); 153 if (node < 0) { 154 ERROR("No information about cpus in DeviceTree.\n"); 155 panic(); 156 } 157 158 /* 159 * QEMU numbers cpus from 0 and there can be /cpus/cpu-map present so we 160 * cannot use fdt_first_subnode() here 161 */ 162 node = fdt_path_offset(dtb, "/cpus/cpu@0"); 163 164 while (node > 0) { 165 if (fdt_getprop(dtb, node, "reg", NULL)) { 166 fdt_get_reg_props_by_index(dtb, node, 0, &mpidr, NULL); 167 } else { 168 ERROR("Incomplete information for cpu %d in DeviceTree.\n", cpu); 169 panic(); 170 } 171 172 dynamic_platform_info.cpu[cpu].mpidr = mpidr; 173 dynamic_platform_info.cpu[cpu].nodeid = 174 fdt_read_uint32_default(dtb, node, "numa-node-id", 0); 175 176 INFO("CPU %d: node-id: %d, mpidr: %ld\n", cpu, 177 dynamic_platform_info.cpu[cpu].nodeid, mpidr); 178 179 cpu++; 180 181 prev = node; 182 node = fdt_next_subnode(dtb, prev); 183 } 184 185 dynamic_platform_info.num_cpus = cpu; 186 INFO("Found %d cpus\n", dynamic_platform_info.num_cpus); 187 188 read_cpu_topology_from_dt(dtb); 189 } 190 191 void read_meminfo_from_dt(void *dtb) 192 { 193 const fdt32_t *prop; 194 const char *type; 195 int prev, node; 196 int len; 197 uint32_t memnode = 0; 198 uint32_t higher_value, lower_value; 199 uint64_t cur_base, cur_size; 200 201 /* 202 * QEMU gives us this DeviceTree node: 203 * 204 * memory@100c0000000 { 205 * numa-node-id = <0x01>; 206 * reg = <0x100 0xc0000000 0x00 0x40000000>; 207 * device_type = "memory"; 208 * }; 209 * 210 * memory@10000000000 { 211 * numa-node-id = <0x00>; 212 * reg = <0x100 0x00 0x00 0xc0000000>; 213 * device_type = "memory"; 214 * } 215 */ 216 217 for (prev = 0;; prev = node) { 218 node = fdt_next_node(dtb, prev, NULL); 219 if (node < 0) { 220 break; 221 } 222 223 type = fdt_getprop(dtb, node, "device_type", &len); 224 if (type && strncmp(type, "memory", len) == 0) { 225 dynamic_platform_info.memory[memnode].nodeid = 226 fdt_read_uint32_default(dtb, node, "numa-node-id", 0); 227 228 /* 229 * Get the 'reg' property of this node and 230 * assume two 8 bytes for base and size. 231 */ 232 prop = fdt_getprop(dtb, node, "reg", &len); 233 if (prop != 0 && len == (2 * sizeof(int64_t))) { 234 higher_value = fdt32_to_cpu(*prop); 235 lower_value = fdt32_to_cpu(*(prop + 1)); 236 cur_base = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32); 237 238 higher_value = fdt32_to_cpu(*(prop + 2)); 239 lower_value = fdt32_to_cpu(*(prop + 3)); 240 cur_size = (uint64_t)(lower_value | ((uint64_t)higher_value) << 32); 241 242 dynamic_platform_info.memory[memnode].addr_base = cur_base; 243 dynamic_platform_info.memory[memnode].addr_size = cur_size; 244 245 INFO("RAM %d: node-id: %d, address: 0x%lx - 0x%lx\n", 246 memnode, 247 dynamic_platform_info.memory[memnode].nodeid, 248 dynamic_platform_info.memory[memnode].addr_base, 249 dynamic_platform_info.memory[memnode].addr_base + 250 dynamic_platform_info.memory[memnode].addr_size - 1); 251 } 252 253 memnode++; 254 } 255 } 256 257 dynamic_platform_info.num_memnodes = memnode; 258 } 259 260 void read_platform_config_from_dt(void *dtb) 261 { 262 int node; 263 const fdt64_t *data; 264 int err; 265 uintptr_t gicd_base; 266 uintptr_t gicr_base; 267 268 /* 269 * QEMU gives us this DeviceTree node: 270 * 271 * intc { 272 * reg = < 0x00 0x40060000 0x00 0x10000 273 * 0x00 0x40080000 0x00 0x4000000>; 274 * its { 275 * reg = <0x00 0x44081000 0x00 0x20000>; 276 * }; 277 * }; 278 */ 279 node = fdt_path_offset(dtb, "/intc"); 280 if (node < 0) { 281 return; 282 } 283 284 data = fdt_getprop(dtb, node, "reg", NULL); 285 if (data == NULL) { 286 return; 287 } 288 289 err = fdt_get_reg_props_by_index(dtb, node, 0, &gicd_base, NULL); 290 if (err < 0) { 291 ERROR("Failed to read GICD reg property of GIC node\n"); 292 return; 293 } 294 INFO("GICD base = 0x%lx\n", gicd_base); 295 296 err = fdt_get_reg_props_by_index(dtb, node, 1, &gicr_base, NULL); 297 if (err < 0) { 298 ERROR("Failed to read GICR reg property of GIC node\n"); 299 return; 300 } 301 INFO("GICR base = 0x%lx\n", gicr_base); 302 303 sbsa_set_gic_bases(gicd_base, gicr_base); 304 305 node = fdt_path_offset(dtb, "/intc/its"); 306 if (node < 0) { 307 return; 308 } 309 310 err = fdt_get_reg_props_by_index(dtb, node, 0, &gic_its_addr, NULL); 311 if (err < 0) { 312 ERROR("Failed to read GICI reg property of GIC node\n"); 313 return; 314 } 315 INFO("GICI base = 0x%lx\n", gic_its_addr); 316 } 317 318 void read_platform_version(void *dtb) 319 { 320 int node; 321 322 node = fdt_path_offset(dtb, "/"); 323 if (node >= 0) { 324 platform_version_major = 325 fdt_read_uint32_default(dtb, node, "machine-version-major", 0); 326 platform_version_minor = 327 fdt_read_uint32_default(dtb, node, "machine-version-minor", 0); 328 } 329 } 330 331 void sip_svc_init(void) 332 { 333 /* Read DeviceTree data before MMU is enabled */ 334 335 void *dtb = (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; 336 int err; 337 338 err = fdt_open_into(dtb, dtb, PLAT_QEMU_DT_MAX_SIZE); 339 if (err < 0) { 340 ERROR("Invalid Device Tree at %p: error %d\n", dtb, err); 341 return; 342 } 343 344 err = fdt_check_header(dtb); 345 if (err < 0) { 346 ERROR("Invalid DTB file passed\n"); 347 return; 348 } 349 350 read_platform_version(dtb); 351 INFO("Platform version: %d.%d\n", platform_version_major, platform_version_minor); 352 353 read_platform_config_from_dt(dtb); 354 read_cpuinfo_from_dt(dtb); 355 read_meminfo_from_dt(dtb); 356 } 357 358 /* 359 * This function is responsible for handling all SiP calls from the NS world 360 */ 361 uintptr_t sbsa_sip_smc_handler(uint32_t smc_fid, 362 u_register_t x1, 363 u_register_t x2, 364 u_register_t x3, 365 u_register_t x4, 366 void *cookie, 367 void *handle, 368 u_register_t flags) 369 { 370 uint32_t ns; 371 uint64_t index; 372 373 /* Determine which security state this SMC originated from */ 374 ns = is_caller_non_secure(flags); 375 if (!ns) { 376 ERROR("%s: wrong world SMC (0x%x)\n", __func__, smc_fid); 377 SMC_RET1(handle, SMC_UNK); 378 } 379 380 switch (smc_fid) { 381 case SIP_SVC_VERSION: 382 INFO("Platform version requested\n"); 383 SMC_RET3(handle, NULL, platform_version_major, platform_version_minor); 384 385 case SIP_SVC_GET_GIC: 386 SMC_RET3(handle, NULL, sbsa_get_gicd(), sbsa_get_gicr()); 387 388 case SIP_SVC_GET_GIC_ITS: 389 SMC_RET2(handle, NULL, gic_its_addr); 390 391 case SIP_SVC_GET_CPU_COUNT: 392 SMC_RET2(handle, NULL, dynamic_platform_info.num_cpus); 393 394 case SIP_SVC_GET_CPU_NODE: 395 index = x1; 396 if (index < PLATFORM_CORE_COUNT) { 397 SMC_RET3(handle, NULL, 398 dynamic_platform_info.cpu[index].nodeid, 399 dynamic_platform_info.cpu[index].mpidr); 400 } else { 401 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM); 402 } 403 404 case SIP_SVC_GET_CPU_TOPOLOGY: 405 if (dynamic_platform_info.cpu_topo.cores > 0) { 406 SMC_RET5(handle, NULL, 407 dynamic_platform_info.cpu_topo.sockets, 408 dynamic_platform_info.cpu_topo.clusters, 409 dynamic_platform_info.cpu_topo.cores, 410 dynamic_platform_info.cpu_topo.threads); 411 } else { 412 /* we do not know topology so we report SMC as unknown */ 413 SMC_RET1(handle, SMC_UNK); 414 } 415 416 case SIP_SVC_GET_MEMORY_NODE_COUNT: 417 SMC_RET2(handle, NULL, dynamic_platform_info.num_memnodes); 418 419 case SIP_SVC_GET_MEMORY_NODE: 420 index = x1; 421 if (index < PLAT_MAX_MEM_NODES) { 422 SMC_RET4(handle, NULL, 423 dynamic_platform_info.memory[index].nodeid, 424 dynamic_platform_info.memory[index].addr_base, 425 dynamic_platform_info.memory[index].addr_size); 426 } else { 427 SMC_RET1(handle, SMC_ARCH_CALL_INVAL_PARAM); 428 } 429 430 default: 431 ERROR("%s: unhandled SMC (0x%x) (function id: %d)\n", __func__, smc_fid, 432 smc_fid - SIP_FUNCTION); 433 SMC_RET1(handle, SMC_UNK); 434 } 435 } 436 437 int sbsa_sip_smc_setup(void) 438 { 439 return 0; 440 } 441 442 /* Define a runtime service descriptor for fast SMC calls */ 443 DECLARE_RT_SVC( 444 sbsa_sip_svc, 445 OEN_SIP_START, 446 OEN_SIP_END, 447 SMC_TYPE_FAST, 448 sbsa_sip_smc_setup, 449 sbsa_sip_smc_handler 450 ); 451