1 2 /* 3 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #include <string.h> 9 10 #include <platform_def.h> 11 12 #include <arch_helpers.h> 13 #include <common/bl_common.h> 14 #include <lib/xlat_tables/xlat_tables_v2.h> 15 #include <services/el3_spmc_ffa_memory.h> 16 #if ENABLE_RME 17 #include <services/rmm_core_manifest.h> 18 #endif 19 20 #include <plat/common/platform.h> 21 #include "qemu_private.h" 22 23 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 24 DEVICE0_SIZE, \ 25 MT_DEVICE | MT_RW | EL3_PAS) 26 27 #ifdef DEVICE1_BASE 28 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 29 DEVICE1_SIZE, \ 30 MT_DEVICE | MT_RW | EL3_PAS) 31 #endif 32 33 #ifdef DEVICE2_BASE 34 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 35 DEVICE2_SIZE, \ 36 MT_DEVICE | MT_RW | EL3_PAS) 37 #endif 38 39 #define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \ 40 SHARED_RAM_SIZE, \ 41 MT_DEVICE | MT_RW | EL3_PAS) 42 43 #define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \ 44 MT_MEMORY | MT_RW | EL3_PAS) 45 46 #define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \ 47 MT_MEMORY | MT_RW | MT_NS) 48 49 #define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \ 50 MT_MEMORY | MT_RO | EL3_PAS) 51 52 #define MAP_FLASH1 MAP_REGION_FLAT(QEMU_FLASH1_BASE, QEMU_FLASH1_SIZE, \ 53 MT_MEMORY | MT_RO | EL3_PAS) 54 55 #ifdef FW_HANDOFF_BASE 56 #define MAP_FW_HANDOFF MAP_REGION_FLAT(FW_HANDOFF_BASE, FW_HANDOFF_SIZE, \ 57 MT_MEMORY | MT_RW | EL3_PAS) 58 #endif 59 #ifdef FW_NS_HANDOFF_BASE 60 #define MAP_FW_NS_HANDOFF MAP_REGION_FLAT(FW_NS_HANDOFF_BASE, FW_HANDOFF_SIZE, \ 61 MT_MEMORY | MT_RW | MT_NS) 62 #endif 63 /* 64 * Table of regions for various BL stages to map using the MMU. 65 * This doesn't include TZRAM as the 'mem_layout' argument passed to 66 * arm_configure_mmu_elx() will give the available subset of that, 67 */ 68 #ifdef IMAGE_BL1 69 static const mmap_region_t plat_qemu_mmap[] = { 70 MAP_FLASH0, 71 MAP_FLASH1, 72 MAP_SHARED_RAM, 73 MAP_DEVICE0, 74 #ifdef MAP_DEVICE1 75 MAP_DEVICE1, 76 #endif 77 #ifdef MAP_DEVICE2 78 MAP_DEVICE2, 79 #endif 80 {0} 81 }; 82 #endif 83 #ifdef IMAGE_BL2 84 static const mmap_region_t plat_qemu_mmap[] = { 85 MAP_FLASH0, 86 MAP_FLASH1, 87 MAP_SHARED_RAM, 88 MAP_DEVICE0, 89 #ifdef MAP_DEVICE1 90 MAP_DEVICE1, 91 #endif 92 #ifdef MAP_DEVICE2 93 MAP_DEVICE2, 94 #endif 95 MAP_NS_DRAM0, 96 #if SPM_MM 97 QEMU_SP_IMAGE_MMAP, 98 #else 99 MAP_BL32_MEM, 100 #endif 101 #ifdef MAP_FW_HANDOFF 102 MAP_FW_HANDOFF, 103 #endif 104 {0} 105 }; 106 #endif 107 #ifdef IMAGE_BL31 108 static const mmap_region_t plat_qemu_mmap[] = { 109 MAP_SHARED_RAM, 110 MAP_DEVICE0, 111 #ifdef MAP_DEVICE1 112 MAP_DEVICE1, 113 #endif 114 #ifdef MAP_DEVICE2 115 MAP_DEVICE2, 116 #endif 117 #ifdef MAP_FW_HANDOFF 118 MAP_FW_HANDOFF, 119 #endif 120 #ifdef MAP_FW_NS_HANDOFF 121 MAP_FW_NS_HANDOFF, 122 #endif 123 #if SPM_MM 124 MAP_NS_DRAM0, 125 QEMU_SPM_BUF_EL3_MMAP, 126 #elif !SPMC_AT_EL3 127 MAP_BL32_MEM, 128 #endif 129 {0} 130 }; 131 #endif 132 #ifdef IMAGE_BL32 133 static const mmap_region_t plat_qemu_mmap[] = { 134 MAP_SHARED_RAM, 135 MAP_DEVICE0, 136 #ifdef MAP_DEVICE1 137 MAP_DEVICE1, 138 #endif 139 #ifdef MAP_DEVICE2 140 MAP_DEVICE2, 141 #endif 142 {0} 143 }; 144 #endif 145 146 #ifdef IMAGE_RMM 147 const mmap_region_t plat_qemu_mmap[] = { 148 MAP_DEVICE0, 149 #ifdef MAP_DEVICE1 150 MAP_DEVICE1, 151 #endif 152 #ifdef MAP_DEVICE2 153 MAP_DEVICE2, 154 #endif 155 {0} 156 }; 157 #endif 158 159 /******************************************************************************* 160 * Returns QEMU platform specific memory map regions. 161 ******************************************************************************/ 162 const mmap_region_t *plat_qemu_get_mmap(void) 163 { 164 return plat_qemu_mmap; 165 } 166 167 #if MEASURED_BOOT || TRUSTED_BOARD_BOOT 168 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 169 { 170 return get_mbedtls_heap_helper(heap_addr, heap_size); 171 } 172 #endif 173 174 #if SPMC_AT_EL3 175 /* 176 * When using the EL3 SPMC implementation allocate the datastore 177 * for tracking shared memory descriptors in normal memory. 178 */ 179 #define PLAT_SPMC_SHMEM_DATASTORE_SIZE 64 * 1024 180 181 uint8_t plat_spmc_shmem_datastore[PLAT_SPMC_SHMEM_DATASTORE_SIZE] __aligned(2 * sizeof(long)); 182 183 int plat_spmc_shmem_datastore_get(uint8_t **datastore, size_t *size) 184 { 185 *datastore = plat_spmc_shmem_datastore; 186 *size = PLAT_SPMC_SHMEM_DATASTORE_SIZE; 187 return 0; 188 } 189 190 int plat_spmc_shmem_begin(struct ffa_mtd *desc) 191 { 192 return 0; 193 } 194 195 int plat_spmc_shmem_reclaim(struct ffa_mtd *desc) 196 { 197 return 0; 198 } 199 #endif 200 201 #if defined(SPD_spmd) 202 int plat_spmd_handle_group0_interrupt(uint32_t intid) 203 { 204 /* 205 * Currently, there are no sources of Group0 secure interrupt 206 * enabled for QEMU. 207 */ 208 (void)intid; 209 return -1; 210 } 211 #endif /*defined(SPD_spmd)*/ 212 213 #if ENABLE_RME 214 /* 215 * Get a pointer to the RMM-EL3 Shared buffer and return it 216 * through the pointer passed as parameter. 217 * 218 * This function returns the size of the shared buffer. 219 */ 220 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) 221 { 222 *shared = (uintptr_t)RMM_SHARED_BASE; 223 224 return (size_t)RMM_SHARED_SIZE; 225 } 226 227 int plat_rmmd_load_manifest(struct rmm_manifest *manifest) 228 { 229 uint64_t checksum; 230 uintptr_t base; 231 uint64_t size; 232 size_t num_banks = 1; 233 size_t num_consoles = 1; 234 struct ns_dram_bank *bank_ptr; 235 struct console_info *console_ptr; 236 237 assert(manifest != NULL); 238 239 manifest->version = RMMD_MANIFEST_VERSION; 240 manifest->padding = 0U; /* RES0 */ 241 manifest->plat_data = (uintptr_t)NULL; 242 manifest->plat_dram.num_banks = num_banks; 243 manifest->plat_console.num_consoles = num_consoles; 244 245 /* 246 * Boot manifest structure illustration: 247 * 248 * +----------------------------------------+ 249 * | offset | field | comment | 250 * +----------+--------------+--------------+ 251 * | 0 | version | 0x00000003 | 252 * +----------+--------------+--------------+ 253 * | 4 | padding | 0x00000000 | 254 * +----------+--------------+--------------+ 255 * | 8 | plat_data | NULL | 256 * +----------+--------------+--------------+ 257 * | 16 | num_banks | | 258 * +----------+--------------+ | 259 * | 24 | banks | plat_dram | 260 * +----------+--------------+ | 261 * | 32 | checksum | | 262 * +----------+--------------+--------------+ 263 * | 40 | num_consoles | | 264 * +----------+--------------+ | 265 * | 48 | consoles | plat_console | 266 * +----------+--------------+ | 267 * | 56 | checksum | | 268 * +----------+--------------+--------------+ 269 * | 64 | base 0 | | 270 * +----------+--------------+ bank[0] | 271 * | 72 | size 0 | | 272 * +----------+--------------+--------------+ 273 * | 80 | base | | 274 * +----------+--------------+ | 275 * | 88 | map_pages | | 276 * +----------+--------------+ | 277 * | 96 | name | | 278 * +----------+--------------+ consoles[0] | 279 * | 104 | clk_in_hz | | 280 * +----------+--------------+ | 281 * | 112 | baud_rate | | 282 * +----------+--------------+ | 283 * | 120 | flags | | 284 * +----------+--------------+--------------+ 285 */ 286 bank_ptr = (struct ns_dram_bank *) 287 (((uintptr_t)manifest) + sizeof(*manifest)); 288 289 console_ptr = (struct console_info *) 290 ((uintptr_t)bank_ptr + (num_banks * sizeof(*bank_ptr))); 291 292 manifest->plat_dram.banks = bank_ptr; 293 manifest->plat_console.consoles = console_ptr; 294 295 /* Ensure the manifest is not larger than the shared buffer */ 296 assert((sizeof(struct rmm_manifest) + 297 (sizeof(struct console_info) * num_consoles) + 298 (sizeof(struct ns_dram_bank) * num_banks)) <= RMM_SHARED_SIZE); 299 300 /* Calculate checksum of plat_dram structure */ 301 checksum = num_banks + (uint64_t)bank_ptr; 302 303 base = NS_DRAM0_BASE; 304 size = NS_DRAM0_SIZE; 305 bank_ptr[0].base = base; 306 bank_ptr[0].size = size; 307 checksum += base + size; 308 309 /* Checksum must be 0 */ 310 manifest->plat_dram.checksum = ~checksum + 1UL; 311 312 /* Calculate the checksum of the plat_consoles structure */ 313 checksum = num_consoles + (uint64_t)console_ptr; 314 315 /* Zero out the console info struct */ 316 memset((void *)console_ptr, 0, sizeof(struct console_info) * num_consoles); 317 318 console_ptr[0].map_pages = 1; 319 console_ptr[0].base = PLAT_QEMU_BOOT_UART_BASE; 320 console_ptr[0].clk_in_hz = PLAT_QEMU_BOOT_UART_CLK_IN_HZ; 321 console_ptr[0].baud_rate = PLAT_QEMU_CONSOLE_BAUDRATE; 322 323 strlcpy(console_ptr[0].name, "pl011", sizeof(console_ptr[0].name)); 324 325 /* Update checksum */ 326 checksum += console_ptr[0].base + console_ptr[0].map_pages + 327 console_ptr[0].clk_in_hz + console_ptr[0].baud_rate; 328 329 /* Checksum must be 0 */ 330 manifest->plat_console.checksum = ~checksum + 1UL; 331 332 return 0; 333 } 334 #endif /* ENABLE_RME */ 335 336 /** 337 * plat_qemu_dt_runtime_address() - Get the final DT location in RAM 338 * 339 * When support is enabled on SBSA, the device tree is relocated from its 340 * original place at the beginning of the NS RAM to after the RMM. This 341 * function returns the address of the final location in RAM of the device 342 * tree. See function update_dt() in qemu_bl2_setup.c 343 * 344 * Return: The address of the final location in RAM of the device tree 345 */ 346 #if (ENABLE_RME && PLAT_qemu_sbsa) 347 void *plat_qemu_dt_runtime_address(void) 348 { 349 return (void *)(uintptr_t)PLAT_QEMU_DT_BASE; 350 } 351 #else 352 void *plat_qemu_dt_runtime_address(void) 353 { 354 return (void *)(uintptr_t)ARM_PRELOADED_DTB_BASE; 355 } 356 #endif /* (ENABLE_RME && PLAT_qemu_sbsa) */ 357