Merge pull request #513 from pgeorgi/configurable-timestamp

build system: allow overriding the build's timestamp

Move private APIs in gic_common.h to a private header

This patch moves the private GIC common accessors from `gic_common.h` to
a new private header file `gic_common_private.h`. This patch also adds

Move private APIs in gic_common.h to a private header

This patch moves the private GIC common accessors from `gic_common.h` to
a new private header file `gic_common_private.h`. This patch also adds
additional comments to GIC register accessors to highlight the fact
that some of them access register values that correspond to multiple
interrupt IDs. The convention used is that the `set`, `get` and `clr`
accessors access and modify the values corresponding to a single interrupt
ID whereas the `read` and `write` GIC register accessors access the raw
GIC registers and it could correspond to multiple interrupt IDs depending
on the register accessed.

Change-Id: I2643ecb2533f01e3d3219fcedfb5f80c120622f9

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Fix GIC_IPRIORITYR setting in new drivers

The code to set the interrupt priority for secure interrupts in the
new GICv2 and GICv3 drivers is incorrect. The setup code to configure
interrupt prioriti

Fix GIC_IPRIORITYR setting in new drivers

The code to set the interrupt priority for secure interrupts in the
new GICv2 and GICv3 drivers is incorrect. The setup code to configure
interrupt priorities of secure interrupts, one interrupt at a time, used
gicd_write_ipriorityr()/gicr_write_ipriority() function affecting
4 interrupts at a time. This bug did not manifest itself because all the
secure interrupts were configured to the highest secure priority(0) during
cold boot and the adjacent non secure interrupt priority would be configured
later by the normal world. This patch introduces new accessors,
gicd_set_ipriorityr() and gicr_set_ipriorityr(), for configuring priority
one interrupt at a time and fixes the the setup code to use the new
accessors.

Fixes ARM-software/tf-issues#344

Change-Id: I470fd74d2b7fce7058b55d83f604be05a27e1341

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Fix race in GIC IPRIORITY and ITARGET accessors

GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
so that individual interrupt priorities can be atomically updated by
issuing a

Fix race in GIC IPRIORITY and ITARGET accessors

GICD_IPRIORITYR and GICD_ITARGETSR specifically support byte addressing
so that individual interrupt priorities can be atomically updated by
issuing a single byte write. The previous implementation of
gicd_set_ipriority() and gicd_set_itargetsr() used 32-bit register
accesses, modifying values for 4 interrupts at a time, using a
read-modify-write approach. This potentially may cause concurrent changes
by other CPUs to the adjacent interrupts to be corrupted. This patch fixes
the issue by modifying these accessors to use byte addressing.

Fixes ARM-software/tf-issues#343

Change-Id: Iec28b5f5074045b00dfb8d5f5339b685f9425915

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Merge pull request #516 from vikramkanigiri/vk/ccn-fix-dvm-entry

Bug fix: Rectify logic to enter or exit from DVM domain

Merge pull request #515 from soby-mathew/sm/gcc_false_positive

PSCI: Resolve GCC static analysis false positive

Merge pull request #514 from sandrine-bailleux/sb/a53-a57-disable-non-temporal-hint

Disable non-temporal hint on Cortex-A53/57

Bug fix: Rectify logic to enter or exit from DVM domain

Currently, `ccn_snoop_dvm_domain_common()` is responsible for providing
a bitmap of HN-F and HN-I nodes in the interconnect. There is a reques

Bug fix: Rectify logic to enter or exit from DVM domain

Currently, `ccn_snoop_dvm_domain_common()` is responsible for providing
a bitmap of HN-F and HN-I nodes in the interconnect. There is a request
node (RN) corresponding to the master interface (e.g. cluster) that needs
to be added or removed from the snoop/DVM domain. This request node is
removed from or added to each HN-F or HN-I node present in the bitmap
depending upon the type of domain.

The above logic is incorrect when participation of a master interface in
the DVM domain has to be managed. The request node should be removed
from or added to the single Miscellaneous Node (MN) in the system
instead of each HN-I node.

This patch fixes this by removing the intermediate
`ccn_snoop_dvm_domain_common()` and instead reads the MN registers to
get the needed node Id bitmap for snoop(HN-F bitmap) and DVM(MN bitmap)
domains.

Additionally, it renames `MN_DDC_SET_OFF` to `MN_DDC_SET_OFFSET` to
be inline with other macros.

Change-Id: Id896046dd0ccc5092419e74f8ac85e31b104f7a4

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PSCI: Resolve GCC static analysis false positive

When BL31 is compiled at `-O3` optimization level using Linaro GCC 4.9
AArch64 toolchain, it reports the following error:

```
services/std_svc/psci/

PSCI: Resolve GCC static analysis false positive

When BL31 is compiled at `-O3` optimization level using Linaro GCC 4.9
AArch64 toolchain, it reports the following error:

```
services/std_svc/psci/psci_common.c: In function 'psci_do_state_coordination':
services/std_svc/psci/psci_common.c:220:27: error: array subscript is above
array bounds [-Werror=array-bounds]
psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state;
^
```

This error is a false positive and this patch resolves the error by asserting
the array bounds in `psci_do_state_coordination()`.

Fixes ARM-software/tf-issues#347

Change-Id: I3584ed7b2e28faf455b082cb3281d6e1d11d6495

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Cortex-Axx: Unconditionally apply CPU reset operations

In the Cortex-A35/A53/A57 CPUs library code, some of the CPU specific
reset operations are skipped if they have already been applied in a
previ

Cortex-Axx: Unconditionally apply CPU reset operations

In the Cortex-A35/A53/A57 CPUs library code, some of the CPU specific
reset operations are skipped if they have already been applied in a
previous invocation of the reset handler. This precaution is not
required, as all these operations can be reapplied safely.

This patch removes the unneeded test-before-set instructions in
the reset handler for these CPUs.

Change-Id: Ib175952c814dc51f1b5125f76ed6c06a22b95167

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Disable non-temporal hint on Cortex-A53/57

The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a s

Disable non-temporal hint on Cortex-A53/57

The LDNP/STNP instructions as implemented on Cortex-A53 and
Cortex-A57 do not behave in a way most programmers expect, and will
most probably result in a significant speed degradation to any code
that employs them. The ARMv8-A architecture (see Document ARM DDI
0487A.h, section D3.4.3) allows cores to ignore the non-temporal hint
and treat LDNP/STNP as LDP/STP instead.

This patch introduces 2 new build flags:
A53_DISABLE_NON_TEMPORAL_HINT and A57_DISABLE_NON_TEMPORAL_HINT
to enforce this behaviour on Cortex-A53 and Cortex-A57. They are
enabled by default.

The string printed in debug builds when a specific CPU errata
workaround is compiled in but skipped at runtime has been
generalised, so that it can be reused for the non-temporal hint use
case as well.

Change-Id: I3e354f4797fd5d3959872a678e160322b13867a1

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build system: allow overriding the build's timestamp

This allows reproducible builds (same source and same compiler produce
bit-identical results) and also allows coordinating the timestamp across
m

build system: allow overriding the build's timestamp

This allows reproducible builds (same source and same compiler produce
bit-identical results) and also allows coordinating the timestamp across
multiple projects, eg. with another firmware.

Signed-off-by: Patrick Georgi <pgeorgi@google.com>

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Move up FVP versions in the user guide

Move up to Base FVP version 7.2 (build 0.8/7202) and Foundation FVP version
9.5 (build 9.5.41) in the user guide.

Change-Id: Ie9900596216808cadf45f042eec639d9

Move up FVP versions in the user guide

Move up to Base FVP version 7.2 (build 0.8/7202) and Foundation FVP version
9.5 (build 9.5.41) in the user guide.

Change-Id: Ie9900596216808cadf45f042eec639d906e497b2

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Remove non-ASCII character from comment

Replaced a long dash in a comment by the ASCII character '-'. Support
for multibyte character in the source character set is not enforced by
the C99 standard.

Remove non-ASCII character from comment

Replaced a long dash in a comment by the ASCII character '-'. Support
for multibyte character in the source character set is not enforced by
the C99 standard. To maximize compatibility with C processing tools
(e.g. compilers or static code analysis tools), they should be removed.

Change-Id: Ie318e380d3b44755109f042a76ebfd2229f42ae3

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Merge pull request #511 from soby-mathew/sm/psci_on_race_v2

Fix PSCI CPU ON race when setting state to ON_PENDING

Merge pull request #508 from soby-mathew/sm/debug_xlat

Use tf_printf() for debug logs from xlat_tables.c

Merge pull request #504 from sandrine-bailleux/sb/fix-doc-mmap

Porting Guide: Clarify identity-mapping requirement

Merge pull request #503 from sandrine-bailleux/sb/clarify-doc-el3-payloads

Clarify EL3 payload documentation

Merge pull request #501 from jcastillo-arm/jc/tf-issues/300

Disable PL011 UART before configuring it

Fix PSCI CPU ON race when setting state to ON_PENDING

When a CPU is powered down using PSCI CPU OFF API, it disables its caches
and updates its `aff_info_state` to OFF. The corresponding cache line

Fix PSCI CPU ON race when setting state to ON_PENDING

When a CPU is powered down using PSCI CPU OFF API, it disables its caches
and updates its `aff_info_state` to OFF. The corresponding cache line is
invalidated by the CPU so that the update will be observed by other CPUs
running with caches enabled. There is a possibility that another CPU
which has been trying to turn ON this CPU via PSCI CPU ON API,
has already seen the update to `aff_info_state` and proceeds to update
the state to ON_PENDING prior to the cache invalidation. This may result
in the update of the state to ON_PENDING being discarded.

This patch fixes this issue by making sure that the update of `aff_info_state`
to ON_PENDING sticks by reading back the value after the cache flush and
retrying it if not updated. The patch also adds a dsbish() to
`psci_do_cpu_off()` to ensure ordering of the update to `aff_info_state`
prior to cache line invalidation.

Fixes ARM-software/tf-issues#349

Change-Id: I225de99957fe89871f8c57bcfc243956e805dcca

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Merge pull request #497 from mtk09422/spm-v3

update SPM/DCM/MTCMOS related code for power control logic

Improve memory layout documentation

This patch adds a brief explanation of the top/bottom load approach
to the Firmware Design guide and how Trusted Firmware keeps track of
the free memory at boot t

Improve memory layout documentation

This patch adds a brief explanation of the top/bottom load approach
to the Firmware Design guide and how Trusted Firmware keeps track of
the free memory at boot time. This will help platform developers to
avoid unexpected results in the memory layout.

Fixes ARM-software/tf-issues#319

Change-Id: I04be7e24c1f3b54d28cac29701c24bf51a5c00ad

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Use tf_printf() for debug logs from xlat_tables.c

The debug prints used to debug translation table setup in xlat_tables.c
used the `printf()` standard library function instead of the stack
optimized

Use tf_printf() for debug logs from xlat_tables.c

The debug prints used to debug translation table setup in xlat_tables.c
used the `printf()` standard library function instead of the stack
optimized `tf_printf()` API. DEBUG_XLAT_TABLE option was used to enable
debug logs within xlat_tables.c and it configured a much larger stack
size for the platform in case it was enabled. This patch modifies these
debug prints within xlat_tables.c to use tf_printf() and modifies the format
specifiers to be compatible with tf_printf(). The debug prints are now enabled
if the VERBOSE prints are enabled in Trusted Firmware via LOG_LEVEL build
option.

The much larger stack size definition when DEBUG_XLAT_TABLE is defined
is no longer required and the platform ports are modified to remove this
stack size definition.

Change-Id: I2f7d77ea12a04b827fa15e2adc3125b1175e4c23

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Porting Guide: Clarify identity-mapping requirement

The memory translation library in Trusted Firmware supports
non-identity mappings for Physical to Virtual addresses since commit
f984ce84ba. Howev

Porting Guide: Clarify identity-mapping requirement

The memory translation library in Trusted Firmware supports
non-identity mappings for Physical to Virtual addresses since commit
f984ce84ba. However, the porting guide hasn't been updated
accordingly and still mandates the platform ports to use
identity-mapped page tables for all addresses.

This patch removes this out-dated information from the Porting Guide
and clarifies in which circumstances non-identity mapping may safely
be used.

Fixes ARM-software/tf-issues#258

Change-Id: I84dab9f3cabfc43794951b1828bfecb13049f706

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Clarify EL3 payload documentation

This patch reworks the section about booting an EL3 payload in the
User Guide:

- Centralize all EL3 payload related information in the same
section.

- Mentio

Clarify EL3 payload documentation

This patch reworks the section about booting an EL3 payload in the
User Guide:

- Centralize all EL3 payload related information in the same
section.

- Mention the possibility to program the EL3 payload in flash memory
and execute it in place.

- Provide model parameters for both the Base and Foundation FVPs.

- Provide some guidance to boot an EL3 payload on Juno.

Change-Id: I975c8de6b9b54ff4de01a1154cba63271d709912

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