1/* 2 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <platform_def.h> 32 33OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) 34OUTPUT_ARCH(PLATFORM_LINKER_ARCH) 35ENTRY(bl31_entrypoint) 36 37 38MEMORY { 39 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE 40} 41 42 43SECTIONS 44{ 45 . = BL31_BASE; 46 ASSERT(. == ALIGN(4096), 47 "BL31_BASE address is not aligned on a page boundary.") 48 49 ro . : { 50 __RO_START__ = .; 51 *bl31_entrypoint.o(.text*) 52 *(.text*) 53 *(.rodata*) 54 55 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 56 . = ALIGN(8); 57 __RT_SVC_DESCS_START__ = .; 58 KEEP(*(rt_svc_descs)) 59 __RT_SVC_DESCS_END__ = .; 60 61#if ENABLE_PMF 62 /* Ensure 8-byte alignment for descriptors and ensure inclusion */ 63 . = ALIGN(8); 64 __PMF_SVC_DESCS_START__ = .; 65 KEEP(*(pmf_svc_descs)) 66 __PMF_SVC_DESCS_END__ = .; 67#endif /* ENABLE_PMF */ 68 69 /* 70 * Ensure 8-byte alignment for cpu_ops so that its fields are also 71 * aligned. Also ensure cpu_ops inclusion. 72 */ 73 . = ALIGN(8); 74 __CPU_OPS_START__ = .; 75 KEEP(*(cpu_ops)) 76 __CPU_OPS_END__ = .; 77 78 *(.vectors) 79 __RO_END_UNALIGNED__ = .; 80 /* 81 * Memory page(s) mapped to this section will be marked as read-only, 82 * executable. No RW data from the next section must creep in. 83 * Ensure the rest of the current memory page is unused. 84 */ 85 . = NEXT(4096); 86 __RO_END__ = .; 87 } >RAM 88 89 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, 90 "cpu_ops not defined for this platform.") 91 92 /* 93 * Define a linker symbol to mark start of the RW memory area for this 94 * image. 95 */ 96 __RW_START__ = . ; 97 98 .data . : { 99 __DATA_START__ = .; 100 *(.data*) 101 __DATA_END__ = .; 102 } >RAM 103 104#ifdef BL31_PROGBITS_LIMIT 105 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.") 106#endif 107 108 stacks (NOLOAD) : { 109 __STACKS_START__ = .; 110 *(tzfw_normal_stacks) 111 __STACKS_END__ = .; 112 } >RAM 113 114 /* 115 * The .bss section gets initialised to 0 at runtime. 116 * Its base address must be 16-byte aligned. 117 */ 118 .bss (NOLOAD) : ALIGN(16) { 119 __BSS_START__ = .; 120 *(.bss*) 121 *(COMMON) 122#if !USE_COHERENT_MEM 123 /* 124 * Bakery locks are stored in normal .bss memory 125 * 126 * Each lock's data is spread across multiple cache lines, one per CPU, 127 * but multiple locks can share the same cache line. 128 * The compiler will allocate enough memory for one CPU's bakery locks, 129 * the remaining cache lines are allocated by the linker script 130 */ 131 . = ALIGN(CACHE_WRITEBACK_GRANULE); 132 __BAKERY_LOCK_START__ = .; 133 *(bakery_lock) 134 . = ALIGN(CACHE_WRITEBACK_GRANULE); 135 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(. - __BAKERY_LOCK_START__); 136 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 137 __BAKERY_LOCK_END__ = .; 138#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE 139 ASSERT(__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE, 140 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements"); 141#endif 142#endif 143 144#if ENABLE_PMF 145 /* 146 * Time-stamps are stored in normal .bss memory 147 * 148 * The compiler will allocate enough memory for one CPU's time-stamps, 149 * the remaining memory for other CPU's is allocated by the 150 * linker script 151 */ 152 . = ALIGN(CACHE_WRITEBACK_GRANULE); 153 __PMF_TIMESTAMP_START__ = .; 154 KEEP(*(pmf_timestamp_array)) 155 . = ALIGN(CACHE_WRITEBACK_GRANULE); 156 __PMF_PERCPU_TIMESTAMP_END__ = .; 157 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__); 158 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1)); 159 __PMF_TIMESTAMP_END__ = .; 160#endif /* ENABLE_PMF */ 161 __BSS_END__ = .; 162 } >RAM 163 164 /* 165 * The xlat_table section is for full, aligned page tables (4K). 166 * Removing them from .bss avoids forcing 4K alignment on 167 * the .bss section and eliminates the unecessary zero init 168 */ 169 xlat_table (NOLOAD) : { 170 *(xlat_table) 171 } >RAM 172 173#if USE_COHERENT_MEM 174 /* 175 * The base address of the coherent memory section must be page-aligned (4K) 176 * to guarantee that the coherent data are stored on their own pages and 177 * are not mixed with normal data. This is required to set up the correct 178 * memory attributes for the coherent data page tables. 179 */ 180 coherent_ram (NOLOAD) : ALIGN(4096) { 181 __COHERENT_RAM_START__ = .; 182 /* 183 * Bakery locks are stored in coherent memory 184 * 185 * Each lock's data is contiguous and fully allocated by the compiler 186 */ 187 *(bakery_lock) 188 *(tzfw_coherent_mem) 189 __COHERENT_RAM_END_UNALIGNED__ = .; 190 /* 191 * Memory page(s) mapped to this section will be marked 192 * as device memory. No other unexpected data must creep in. 193 * Ensure the rest of the current memory page is unused. 194 */ 195 . = NEXT(4096); 196 __COHERENT_RAM_END__ = .; 197 } >RAM 198#endif 199 200 /* 201 * Define a linker symbol to mark end of the RW memory area for this 202 * image. 203 */ 204 __RW_END__ = .; 205 __BL31_END__ = .; 206 207 __BSS_SIZE__ = SIZEOF(.bss); 208#if USE_COHERENT_MEM 209 __COHERENT_RAM_UNALIGNED_SIZE__ = 210 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__; 211#endif 212 213 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.") 214} 215