Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration

* changes:
plat: marvell: armada: mcbin: squash several IO windows into one
plat: marvell: armada: fix BL32

Merge changes I9feae1fc,I5cbe7192,I1867ece3,I85c2434a,If8edeeec, ... into integration

* changes:
plat: marvell: armada: mcbin: squash several IO windows into one
plat: marvell: armada: fix BL32 extra parameters usage
drivers: marvell: Fix the LLC SRAM driver
plat: marvell: armada: a8k: change CCU LLC SRAM mapping
plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS
drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW
plat: marvell: armada: move mg conf related code to appropriate driver
marvell: comphy: start AP FW when comphy AP mode selected
drivers: marvell: mg_conf_cm3: add basic driver
tools: doimage: change the binary image alignment to 16
tools: doimage: migrate to mbedtls v2.8 APIs

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Add myself and Andre Przywara as code owners for the Arm FPGA platform port

Signed-off-by: Javier Almansa Sobrino <javier.almansasobrino@arm.com>
Change-Id: I6d3949a971fada5a086b788dbe274f8451fcfc0d

plat/arm: Fix build failure due to increase in BL2 size

BL2 size gets increased due to the libfdt library update and
that eventually cause no-optimization build failure for BL2 as below:
aarch64-no

plat/arm: Fix build failure due to increase in BL2 size

BL2 size gets increased due to the libfdt library update and
that eventually cause no-optimization build failure for BL2 as below:
aarch64-none-elf-ld.bfd: BL2 image has exceeded its limit.
aarch64-none-elf-ld.bfd: region `RAM' overflowed by 4096 bytes
Makefile:1070: recipe for target 'build/fvp/debug/bl2/bl2.elf' failed
make: *** [build/fvp/debug/bl2/bl2.elf] Error 1

Fixed build failure by increasing BL2 image size limit by 4Kb.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I92a57eb4db601561a98e254b64994bb921a88db3

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plat: marvell: armada: mcbin: squash several IO windows into one

There is no need to open tree different IO window when there is
possibility of having one covering required range.

Change-Id: I9feae

plat: marvell: armada: mcbin: squash several IO windows into one

There is no need to open tree different IO window when there is
possibility of having one covering required range.

Change-Id: I9feae1fc583df1f7d97d28161cf7601f43513856
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: marvell: armada: fix BL32 extra parameters usage

Update missing code releated to the BL32 payload.

Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semiha

plat: marvell: armada: fix BL32 extra parameters usage

Update missing code releated to the BL32 payload.

Change-Id: I5cbe71921467c53c45be5510f950cefdacc110e1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>

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drivers: marvell: Fix the LLC SRAM driver

- Fix the line address macro
- LLC invalidate and enable before ways lock for allocation
- Add support for limited SRAM size allocation
- Add SRAM RW test f

drivers: marvell: Fix the LLC SRAM driver

- Fix the line address macro
- LLC invalidate and enable before ways lock for allocation
- Add support for limited SRAM size allocation
- Add SRAM RW test function

Change-Id: I1867ece3047566ddd7931bd7472e1f47fb42c8d4
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: a8k: change CCU LLC SRAM mapping

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
unt

plat: marvell: armada: a8k: change CCU LLC SRAM mapping

The LLC SRAM will be enabled in OP-TEE OS for usage as secure storage.
The CCU have to prepare SRAM window, but point to the DRAM-0 target
until the SRAM is actually enabled.
This patch changes CCU SRAM window target to DRAM-0
Remove dependence between LLC_SRAM and LLC_ENABLE and update the
build documentation.
The SRAМ base moved to follow the OP-TEE SHMEM area (0x05400000)

Change-Id: I85c2434a3d515ec37da5ae8eb729e3280f91c456
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS

Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.

Change-Id: If8edeeec5861b52

plat: marvell: armada: adjust trusted DRAM size to match OP-TEE OS

Area used as trusted DRAM is 12MB in Marvell OP-TEE OS module.
It is followed by 4MB of shared memory.

Change-Id: If8edeeec5861b529408baca25f78c06a0a440d8c
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instanc

drivers: marvell: mg_conf_cm3: pass comphy lane number to AP FW

Since the AP process can be enabled on different setups, the information
about used comphy lane should be passed to AP FW. For instance:
- A8K development board uses comphy lane 2 for eth 0
- cn913x development board uses comphy lane 4 for eth 0

Change-Id: Icf001fb3eea4d9c24c09384e49844ecaf8655ad2
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Si

plat: marvell: armada: move mg conf related code to appropriate driver

Now when mg_conf_cm3 driver is present - move all relevant code there.

Change-Id: I444d9e877c450d6ee69ca3a49b547e4c3aeac0be
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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marvell: comphy: start AP FW when comphy AP mode selected

After configuring comphy to AP mode also start AP FW.

Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4
Signed-off-by: Grzegorz Jaszczyk

marvell: comphy: start AP FW when comphy AP mode selected

After configuring comphy to AP mode also start AP FW.

Change-Id: Ib28977d7ee643575a818ba17f69dea0b7e8e0df4
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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drivers: marvell: mg_conf_cm3: add basic driver

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semiha

drivers: marvell: mg_conf_cm3: add basic driver

Implement function which will allow to start AP FW.

Change-Id: Ie0fc8ad138bf56b10809cdc92d1e5e96a2aaf33f
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>

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tools: doimage: change the binary image alignment to 16

Change the binary image alignment from 4 to 16.
The PKCS signature verification fails for unaligned images.

Change-Id: Ieb08dc3ea128790f542ad

tools: doimage: change the binary image alignment to 16

Change the binary image alignment from 4 to 16.
The PKCS signature verification fails for unaligned images.

Change-Id: Ieb08dc3ea128790f542ad93e3c948117567a65af
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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tools: doimage: migrate to mbedtls v2.8 APIs

Replace deprecated mbedtls_sha256 with mbedtls_sha256_ret
The mbedtls_pk_parse_key does not work correctly anymore
with the DER buffer embedded in the se

tools: doimage: migrate to mbedtls v2.8 APIs

Replace deprecated mbedtls_sha256 with mbedtls_sha256_ret
The mbedtls_pk_parse_key does not work correctly anymore
with the DER buffer embedded in the secure image extentson
using the buffer size as the the key length.
Move to mbedtls_pk_parse_subpubkey API that handles such
case correctly.
The DER format already contains the key length, so there
is no particular reason to supply it to the key parser.
Update the doimage version to 3.3

Change-Id: I0ec5ee84b7d1505b43138e0b7a6bdba44a6702b6
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>

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plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Ma

plat: imx8mp: Add the basic support for i.MX8MP

The i.MX 8MP Media Applications Processor is part of the growing
i.MX8M family targeting the consumer and industrial market. It brings
an effective Machine Learning and AI accelerator that enables a new
class of applications. It is built in 14LPP to achieve both high
performance and low power consumption and relies on a powerful fully
coherent core complex based on a quad core Arm Cortex-A53 cluster and
Cortex-M7 low-power coprocessor, audio digital signal processor, machine
learning and graphics accelerators.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I98311ebc32bee20af05031492e9fc24d06e55f4a

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Merge "plat/arm, dts: Update platform device tree for CoT" into integration

plat/arm, dts: Update platform device tree for CoT

Included cot_descriptors.dtsi in platform device tree
(fvp_tb_fw_config.dts).

Also, updated the maximum size of tb_fw_config to 0x1800
in order to

plat/arm, dts: Update platform device tree for CoT

Included cot_descriptors.dtsi in platform device tree
(fvp_tb_fw_config.dts).

Also, updated the maximum size of tb_fw_config to 0x1800
in order to accomodate the device tree for CoT descriptors.

Follow up patch will parse the device tree for these CoT descriptors
and fill the CoT descriptor structures at runtime instead of using
static CoT descriptor structures in the code base.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I90122bc713f6842b82fb019b04caf42629b4f45a

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Merge "dts: Add CoT descriptor nodes and properties in device tree" into integration

dts: Add CoT descriptor nodes and properties in device tree

Added CoT descriptor nodes and properties in device tree.
Currently, CoT descriptors which are used by BL2 are added as part
of device tre

dts: Add CoT descriptor nodes and properties in device tree

Added CoT descriptor nodes and properties in device tree.
Currently, CoT descriptors which are used by BL2 are added as part
of device tree.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: Iff23cff843e5489fac18bcee5f5d6a71de5ad0d0

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Merge "make, doc: Add build option to create chain of trust at runtime" into integration

plat: imx8m: Move the gpc hw reg to a separate header file

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some sligh

plat: imx8m: Move the gpc hw reg to a separate header file

Although the GPC provides the similar functions for all the
i.MX8M SoC family, the HW register offset and bit defines
still have some slight difference, so move the hw reg
offset & most of the bitfield defines in 'gpc_reg.h' that
is specific to each SoC.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I291c435fe98c2f6e6ff8fe0c715ff3a83daa6a0f

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io_storage: remove redundant assigments

The assignments to 'result' are unneeded.

Change-Id: I18899f10bf9bd7f219f0e47a981683d8b4701bde
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

arm_fpga: Predefine DTB and BL33 load addresses

The memory layout for the FPGA is fairly uniform for most of the FPGA
images, and we already assume that DRAM starts at 2GB by default.

Prepopulate P

arm_fpga: Predefine DTB and BL33 load addresses

The memory layout for the FPGA is fairly uniform for most of the FPGA
images, and we already assume that DRAM starts at 2GB by default.

Prepopulate PRELOADED_BL33_BASE and FPGA_PRELOADED_DTB_BASE to some
sane default values, to simplify building some stock image.
If people want to deviate from that, they can always override those
addresses on the make command line.

Change-Id: I2238fafb3f8253a01ad2d88d45827c141d9b29dd
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Add Klein and Matterhorn support

To support FPGAs with those cores as well, as the respective cpulib
files to the Makefile.

Change-Id: I1a60867d5937be88b32b210c7817be4274554a76
Signed-off

arm_fpga: Add Klein and Matterhorn support

To support FPGAs with those cores as well, as the respective cpulib
files to the Makefile.

Change-Id: I1a60867d5937be88b32b210c7817be4274554a76
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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arm_fpga: Support more CPU clusters

The maximum number of clusters is currently set to 2, which is quite
limiting. As there are FPGA images with 4 clusters, let's increase the
limit to 4.

Change-Id

arm_fpga: Support more CPU clusters

The maximum number of clusters is currently set to 2, which is quite
limiting. As there are FPGA images with 4 clusters, let's increase the
limit to 4.

Change-Id: I9a85ca07ebbd2a018ad9668536d867ad6b75e537
Signed-off-by: Andre Przywara <andre.przywara@arm.com>

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