| 5096aeb2 | 01-Dec-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
feat(spmc): add FF-A secure partition manager core
This patch introduces the core support for enabling an SPMC in EL3
as per the FF-A spec.
The current implemented functionality is targeted to enab
feat(spmc): add FF-A secure partition manager core
This patch introduces the core support for enabling an SPMC in EL3
as per the FF-A spec.
The current implemented functionality is targeted to enable
initialization of the SPMC itself and initial support for
bringing up a single S-EL1 SP.
This includes initialization of the SPMC's internal state,
parsing of an SP's manifest, preparing the cpu contexts and
appropriate system registers for the Secure Partition.
The spmc_smc_handler is the main handler for all incoming SMCs
to the SPMC, FF-A ABI handlers and functionality will
be implemented in subsequent patches.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: Ib33c240b91e54cbd018a69fec880d02adfbe12b9
show more ...
|
| 8b95e848 | 31-Jan-2022 |
Zelalem Aweke <zelalem.aweke@arm.com> |
refactor(context mgmt): add cm_prepare_el3_exit_ns function
As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' fun
refactor(context mgmt): add cm_prepare_el3_exit_ns function
As part of the RFC:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/13651,
this patch adds the 'cm_prepare_el3_exit_ns' function. The function is
a wrapper to 'cm_prepare_el3_exit' function for Non-secure state.
When EL2 sysregs context exists (CTX_INCLUDE_EL2_REGS is
enabled) EL1 and EL2 sysreg values are restored from the context
instead of directly updating the registers.
Signed-off-by: Zelalem Aweke <zelalem.aweke@arm.com>
Change-Id: I9b071030576bb05500d54090e2a03b3f125d1653
show more ...
|
| b61d94a1 | 19-Dec-2021 |
Marc Bonnici <marc.bonnici@arm.com> |
refactor(spm_mm): reorganize secure partition manager code
In preparation for adding the EL3 SPMC configuration as defined in
the FF-A specification, restructure the existing SPM_MM code.
With this
refactor(spm_mm): reorganize secure partition manager code
In preparation for adding the EL3 SPMC configuration as defined in
the FF-A specification, restructure the existing SPM_MM code.
With this restructuring of the code, the 'spm_mm' directory is
renamed as 'spm' and the code inside has been split into two
sub-directories named 'common' and 'spm_mm'. The code in 'spm_mm'
directory contains the code that implements the MM interface.
In subsequent patches, the 'spmc' directory will be introduced
under the 'spm' directory providing the code that implements
the 'FF-A' interface.
Currently the common functionality for S-EL1 partitions is
limited to assembler functions to enter and exit an SP
synchronously.
Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
Change-Id: I37739b9b53bc68e151ab5c1c0c6a15b3ee362241
show more ...
|
| a0435105 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
paramete
feat(rme): add dummy realm attestation key to RMMD
Add a dummy realm attestation key to RMMD, and return it on request.
The realm attestation key is requested with an SMC with the following
parameters:
* Fid (0xC400001B2).
* Attestation key buffer PA (the realm attestation key is copied
at this address by the monitor).
* Attestation key buffer length as input and size of realm
attesation key as output.
* Type of elliptic curve.
Signed-off-by: Tamas Ban <tamas.ban@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I12d8d98fd221f4638ef225c9383374ddf6e65eac
show more ...
|
| 0f9159b7 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC4000
feat(rme): add dummy platform token to RMMD
Add a dummy platform token to RMMD and return it on request. The
platform token is requested with an SMC with the following parameters:
* Fid (0xC40001B3).
* Platform token PA (the platform token is copied at this address by
the monitor). The challenge object needs to be passed by
the caller in this buffer.
* Platform token len.
* Challenge object len.
When calling the SMC, the platform token buffer received by EL3 contains
the challenge object. It is not used on the FVP and is only printed to
the log.
Signed-off-by: Mate Toth-Pal <mate.toth-pal@arm.com>
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I8b2f1d54426c04e76d7a3baa6b0fbc40b0116348
show more ...
|
| 319fb084 | 22-Mar-2022 |
Soby Mathew <soby.mathew@arm.com> |
refactor(rme): reorg existing RMMD EL3 service FIDs
This patch reworks the GTSI service implementation in RMMD
such that it is made internal to RMMD. This rework also
lays the ground work for additi
refactor(rme): reorg existing RMMD EL3 service FIDs
This patch reworks the GTSI service implementation in RMMD
such that it is made internal to RMMD. This rework also
lays the ground work for additional RMMD services which
can be invoked from RMM.
The rework renames some of the FID macros to make it
more suited for adding more RMMD services. All the RMM-EL31
service SMCs are now routed via rmmd_rmm_el3_handler().
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: Ic52ca0f33b79a1fd1deefa8136f9586b088b2e07
show more ...
|
| d555233f | 18-Mar-2022 |
Federico Recanati <federico.recanati@arm.com> |
feat(spm): add FFA_RX_ACQUIRE forwarding in SPMD
Add FF-A v1.1 FFA_RX_ACQUIRE ABI forwarding to SPMD.
RX acquire interface is used by Hypervisor to acquire ownership of a
VM's RX buffer from SPMC wh
feat(spm): add FFA_RX_ACQUIRE forwarding in SPMD
Add FF-A v1.1 FFA_RX_ACQUIRE ABI forwarding to SPMD.
RX acquire interface is used by Hypervisor to acquire ownership of a
VM's RX buffer from SPMC when it needs to deliver a message to the VM.
Change-Id: I5f57240a9c9e94eb696a5a394ec0644170380026
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
show more ...
|
| 9b2510b6 | 24-Feb-2022 |
Bipin Ravi <bipin.ravi@arm.com> |
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new
fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57
This patch applies CVE-2022-23960 workarounds for Cortex-A75,
Cortex-A73, Cortex-A72 & Cortex-A57. This patch also implements
the new SMCCC_ARCH_WORKAROUND_3 and enables necessary discovery
hooks for Coxtex-A72, Cortex-A57, Cortex-A73 and Cortex-A75 to
enable discovery of this SMC via SMC_FEATURES. SMCCC_ARCH_WORKAROUND_3
is implemented for A57/A72 because some revisions are affected by both
CVE-2022-23960 and CVE-2017-5715 and this allows callers to replace
SMCCC_ARCH_WORKAROUND_1 calls with SMCCC_ARCH_WORKAROUND_3. For details
of SMCCC_ARCH_WORKAROUND_3, please refer SMCCCv1.4 specification.
Signed-off-by: Bipin Ravi <bipin.ravi@arm.com>
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Ifa6d9c7baa6764924638efe3c70468f98d60ed7c
show more ...
|
| 6a00e9b0 | 21-Oct-2021 |
Robert Wakim <robert.wakim@arm.com> |
fix(gpt_rme): rework delegating/undelegating sequence
The previous delegating/undelegating sequence was incorrect as per the
specification DDI0615, "Architecture Reference Manual Supplement, The
Rea
fix(gpt_rme): rework delegating/undelegating sequence
The previous delegating/undelegating sequence was incorrect as per the
specification DDI0615, "Architecture Reference Manual Supplement, The
Realm Management Extension (RME), for Armv9-A" Sections A1.1.1 and
A1.1.2
Off topic:
- cleaning the gpt_is_gpi_valid and gpt_check_pass_overlap
Change-Id: Idb64d0a2e6204f1708951137062847938ab5e0ac
Signed-off-by: Robert Wakim <robert.wakim@arm.com>
show more ...
|
| b298d4df | 04-Mar-2022 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(ff-a): forward FFA_VERSION from SPMD to SPMC" into integration |
| c2eba07c | 03-Feb-2022 |
Federico Recanati <federico.recanati@arm.com> |
feat(spm): add FFA_MSG_SEND2 forwarding in SPMD
Add FF-A v1.1 indirect messaging ABI FFA_MSG_SEND2 to SPMD to allow
message forwarding across normal/secure worlds.
Change-Id: I074fbd2e4d13893925f98
feat(spm): add FFA_MSG_SEND2 forwarding in SPMD
Add FF-A v1.1 indirect messaging ABI FFA_MSG_SEND2 to SPMD to allow
message forwarding across normal/secure worlds.
Change-Id: I074fbd2e4d13893925f987cee271d49da3aaf64b
Signed-off-by: Federico Recanati <federico.recanati@arm.com>
show more ...
|
| 9944f557 | 09-Dec-2021 |
Daniel Boulby <daniel.boulby@arm.com> |
feat(ff-a): forward FFA_VERSION from SPMD to SPMC
Introduced by FF-A v1.1 we must forward a call to FFA_VERSION
to the SPMC so that the ffa version of the caller can be stored
for later use. Since t
feat(ff-a): forward FFA_VERSION from SPMD to SPMC
Introduced by FF-A v1.1 we must forward a call to FFA_VERSION
to the SPMC so that the ffa version of the caller can be stored
for later use. Since the return of FFA_VERSION is not wrapped in
a FF-A call we need to use a direct message request to do this
forwarding. For the spmd_handler in the SPMC to hand off to the
correct function we use w2 to specify a target framework function.
Therefore we must update PSCI CPU_OFF to do this as well.
Change-Id: Ibaa6832b66f1597b3d65aa8986034f0c5916016d
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
show more ...
|
| 4d482156 | 22-Oct-2021 |
Daniel Boulby <daniel.boulby@arm.com> |
test(el3-runtime): dit is retained on world switch
Add tsp service to check the value of the PSTATE DIT bit is as
expected and toggle it's value. This is used to ensure that
the DIT bit is maintaine
test(el3-runtime): dit is retained on world switch
Add tsp service to check the value of the PSTATE DIT bit is as
expected and toggle it's value. This is used to ensure that
the DIT bit is maintained during a switch from the Normal to
Secure worlds and back.
Change-Id: I4e8bdfa6530e5e75925c0079d4fa2795133c5105
Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
show more ...
|
| 9697e459 | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(trp): Distinguish between cold and warm boot" into integration |
| 00e81131 | 01-Dec-2021 |
Mark Dykes <mark.dykes@arm.com> |
fix(trp): Distinguish between cold and warm boot
The original design prevented the primary CPU from doing a
warm boot sequence. This patch allows the primary to do warm
boot as well.
Signed-off-by:
fix(trp): Distinguish between cold and warm boot
The original design prevented the primary CPU from doing a
warm boot sequence. This patch allows the primary to do warm
boot as well.
Signed-off-by: Mark Dykes <mark.dykes@arm.com>
Change-Id: I6baa50c3dff3051ff8b3e5a922d340634f651867
show more ...
|
| 3082a330 | 10-Dec-2021 |
Alexei Fedorov <Alexei.Fedorov@arm.com> |
Merge "fix(rmmd/sve): enable/disable SVE/FPU for Realms" into integration |
| a4cc85c1 | 09-Dec-2021 |
Subhasish Ghosh <subhasish.ghosh@arm.com> |
fix(rmmd/sve): enable/disable SVE/FPU for Realms
This patch enable/disable SVE/FPU for Realms depending
upon it's state in NS.
When this feature is enabled, traps to EL3 on SVE/FPU access from
Real
fix(rmmd/sve): enable/disable SVE/FPU for Realms
This patch enable/disable SVE/FPU for Realms depending
upon it's state in NS.
When this feature is enabled, traps to EL3 on SVE/FPU access from
Realms are disabled. However, RMM must ensure that the Realm <-> NS
SVE/FPU registers are not corrupted by each other and Realms do
not leak information to NS.
Change-Id: I0a27a055787976507017b72879ba6458f066624e
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
show more ...
|
| b9fd2d3c | 14-Nov-2021 |
Subhasish Ghosh <subhasish.ghosh@arm.com> |
fix(rmmd): align RMI and GTSI FIDs with SMCCC
This patch allocates the RMI and GTSI FIDs from the reserved
range in Standard Secure Service call range of SMCCC.
Signed-off-by: Subhasish Ghosh <subh
fix(rmmd): align RMI and GTSI FIDs with SMCCC
This patch allocates the RMI and GTSI FIDs from the reserved
range in Standard Secure Service call range of SMCCC.
Signed-off-by: Subhasish Ghosh <subhasish.ghosh@arm.com>
Change-Id: I82e77778882194c2a78ca6340788d53bab7c3a50
show more ...
|
| 11578303 | 17-Nov-2021 |
Soby Mathew <soby.mathew@arm.com> |
fix(rmmd): preserve x4-x7 as per SMCCCv1.1
The RMI command handling in RMMD did not preserve x4 to x7 when
returning to NS caller. Although this is allowed for SMCCCv1.0, this is
not correct as per
fix(rmmd): preserve x4-x7 as per SMCCCv1.1
The RMI command handling in RMMD did not preserve x4 to x7 when
returning to NS caller. Although this is allowed for SMCCCv1.0, this is
not correct as per v1.1. This fixes the same by differentiating the
onward and backward path during SMC handling.
This patch also fixes an issue with the backward path wherein the first
argument was being truncated to 32 bits.
Change-Id: Ibc85d574d5a2178a763975ddb32e456a12e7dc88
Signed-off-by: Soby Mathew <soby.mathew@arm.com>
show more ...
|
| 4333f95b | 15-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
fix(spm_mm): do not compile if SVE/SME is enabled
As spm_mm cannot handle SVE/SME usage in NS world so its better to give
compilation error when ENABLE_SVE_FOR_NS=1 or ENABLE_SME_FOR_NS=1.
Signed-o
fix(spm_mm): do not compile if SVE/SME is enabled
As spm_mm cannot handle SVE/SME usage in NS world so its better to give
compilation error when ENABLE_SVE_FOR_NS=1 or ENABLE_SME_FOR_NS=1.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I69dbb272ca681bb020501342008eda20d4c0b096
show more ...
|
| dc78e62d | 08-Jul-2021 |
johpow01 <john.powell@arm.com> |
feat(sme): enable SME functionality
This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively.
feat(sme): enable SME functionality
This patch adds two new compile time options to enable SME in TF-A:
ENABLE_SME_FOR_NS and ENABLE_SME_FOR_SWD for use in non-secure and
secure worlds respectively. Setting ENABLE_SME_FOR_NS=1 will enable
SME for non-secure worlds and trap SME, SVE, and FPU/SIMD instructions
in secure context. Setting ENABLE_SME_FOR_SWD=1 will disable these
traps, but support for SME context management does not yet exist in
SPM so building with SPD=spmd will fail.
The existing ENABLE_SVE_FOR_NS and ENABLE_SVE_FOR_SWD options cannot
be used with SME as it is a superset of SVE and will enable SVE and
FPU/SIMD along with SME.
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Iaaac9d22fe37b4a92315207891da848a8fd0ed73
show more ...
|
| b6b486f3 | 10-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(sdei): fix assert while kdump issue" into integration |
| 2461bd3a | 09-Nov-2021 |
Manish Pandey <manish.pandey2@arm.com> |
fix(gpt_rme): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Mani
fix(gpt_rme): use correct print format for uint64_t
sha 4ce3e99a3 introduced printf format specifiers for fixed width
types, which uses PRI*64 instead of "ll" for 64 bit values.
Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I30472411467061d58cc6ee22407ed3bad2552751
show more ...
|
| 0c23e6f4 | 09-Nov-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
fix(spmd): error macro to use correct print format
Following merge of [1] then [2] broke the build because of an incorrect
format specifier in an ERROR macro. Fix to use the correct print format.
[
fix(spmd): error macro to use correct print format
Following merge of [1] then [2] broke the build because of an incorrect
format specifier in an ERROR macro. Fix to use the correct print format.
[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/5437
[2] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9211
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: I14d4c31091f6a5f4c3252f6d810e9d2bb2f545c4
show more ...
|
| a127b99d | 09-Nov-2021 |
Olivier Deprez <olivier.deprez@arm.com> |
Merge "feat(SPMD): route secure interrupts to SPMC" into integration |