1 /* 2 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/debug.h> 10 #include <drivers/arm/cci.h> 11 #include <drivers/arm/ccn.h> 12 #include <drivers/arm/gicv2.h> 13 #include <drivers/arm/sp804_delay_timer.h> 14 #include <drivers/generic_delay_timer.h> 15 #include <lib/mmio.h> 16 #include <lib/smccc.h> 17 #include <lib/xlat_tables/xlat_tables_compat.h> 18 #include <platform_def.h> 19 #include <services/arm_arch_svc.h> 20 #if SPM_MM 21 #include <services/spm_mm_partition.h> 22 #endif 23 24 #include <plat/arm/common/arm_config.h> 25 #include <plat/arm/common/plat_arm.h> 26 #include <plat/common/platform.h> 27 28 #include "fvp_private.h" 29 30 /* Defines for GIC Driver build time selection */ 31 #define FVP_GICV2 1 32 #define FVP_GICV3 2 33 34 /******************************************************************************* 35 * arm_config holds the characteristics of the differences between the three FVP 36 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 37 * at each boot stage by the primary before enabling the MMU (to allow 38 * interconnect configuration) & used thereafter. Each BL will have its own copy 39 * to allow independent operation. 40 ******************************************************************************/ 41 arm_config_t arm_config; 42 43 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 44 DEVICE0_SIZE, \ 45 MT_DEVICE | MT_RW | MT_SECURE) 46 47 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 48 DEVICE1_SIZE, \ 49 MT_DEVICE | MT_RW | MT_SECURE) 50 51 #if FVP_GICR_REGION_PROTECTION 52 #define MAP_GICD_MEM MAP_REGION_FLAT(BASE_GICD_BASE, \ 53 BASE_GICD_SIZE, \ 54 MT_DEVICE | MT_RW | MT_SECURE) 55 56 /* Map all core's redistributor memory as read-only. After boots up, 57 * per-core map its redistributor memory as read-write */ 58 #define MAP_GICR_MEM MAP_REGION_FLAT(BASE_GICR_BASE, \ 59 (BASE_GICR_SIZE * PLATFORM_CORE_COUNT),\ 60 MT_DEVICE | MT_RO | MT_SECURE) 61 #endif /* FVP_GICR_REGION_PROTECTION */ 62 63 /* 64 * Need to be mapped with write permissions in order to set a new non-volatile 65 * counter value. 66 */ 67 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 68 DEVICE2_SIZE, \ 69 MT_DEVICE | MT_RW | MT_SECURE) 70 71 /* 72 * Table of memory regions for various BL stages to map using the MMU. 73 * This doesn't include Trusted SRAM as setup_page_tables() already takes care 74 * of mapping it. 75 */ 76 #ifdef IMAGE_BL1 77 const mmap_region_t plat_arm_mmap[] = { 78 ARM_MAP_SHARED_RAM, 79 V2M_MAP_FLASH0_RO, 80 V2M_MAP_IOFPGA, 81 MAP_DEVICE0, 82 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 83 MAP_DEVICE1, 84 #endif 85 #if TRUSTED_BOARD_BOOT 86 /* To access the Root of Trust Public Key registers. */ 87 MAP_DEVICE2, 88 /* Map DRAM to authenticate NS_BL2U image. */ 89 ARM_MAP_NS_DRAM1, 90 #endif 91 {0} 92 }; 93 #endif 94 #ifdef IMAGE_BL2 95 const mmap_region_t plat_arm_mmap[] = { 96 ARM_MAP_SHARED_RAM, 97 V2M_MAP_FLASH0_RW, 98 V2M_MAP_IOFPGA, 99 MAP_DEVICE0, 100 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 101 MAP_DEVICE1, 102 #endif 103 ARM_MAP_NS_DRAM1, 104 #ifdef __aarch64__ 105 ARM_MAP_DRAM2, 106 #endif 107 /* 108 * Required to load HW_CONFIG, SPMC and SPs to trusted DRAM. 109 */ 110 ARM_MAP_TRUSTED_DRAM, 111 #if ENABLE_RME 112 ARM_MAP_RMM_DRAM, 113 ARM_MAP_GPT_L1_DRAM, 114 #endif /* ENABLE_RME */ 115 #ifdef SPD_tspd 116 ARM_MAP_TSP_SEC_MEM, 117 #endif 118 #if TRUSTED_BOARD_BOOT 119 /* To access the Root of Trust Public Key registers. */ 120 MAP_DEVICE2, 121 #endif /* TRUSTED_BOARD_BOOT */ 122 123 #if CRYPTO_SUPPORT && !BL2_AT_EL3 124 /* 125 * To access shared the Mbed TLS heap while booting the 126 * system with Crypto support 127 */ 128 ARM_MAP_BL1_RW, 129 #endif /* CRYPTO_SUPPORT && !BL2_AT_EL3 */ 130 #if SPM_MM || SPMC_AT_EL3 131 ARM_SP_IMAGE_MMAP, 132 #endif 133 #if ARM_BL31_IN_DRAM 134 ARM_MAP_BL31_SEC_DRAM, 135 #endif 136 #ifdef SPD_opteed 137 ARM_MAP_OPTEE_CORE_MEM, 138 ARM_OPTEE_PAGEABLE_LOAD_MEM, 139 #endif 140 {0} 141 }; 142 #endif 143 #ifdef IMAGE_BL2U 144 const mmap_region_t plat_arm_mmap[] = { 145 MAP_DEVICE0, 146 V2M_MAP_IOFPGA, 147 {0} 148 }; 149 #endif 150 #ifdef IMAGE_BL31 151 const mmap_region_t plat_arm_mmap[] = { 152 ARM_MAP_SHARED_RAM, 153 #if USE_DEBUGFS 154 /* Required by devfip, can be removed if devfip is not used */ 155 V2M_MAP_FLASH0_RW, 156 #endif /* USE_DEBUGFS */ 157 ARM_MAP_EL3_TZC_DRAM, 158 V2M_MAP_IOFPGA, 159 MAP_DEVICE0, 160 #if FVP_GICR_REGION_PROTECTION 161 MAP_GICD_MEM, 162 MAP_GICR_MEM, 163 #else 164 MAP_DEVICE1, 165 #endif /* FVP_GICR_REGION_PROTECTION */ 166 ARM_V2M_MAP_MEM_PROTECT, 167 #if SPM_MM 168 ARM_SPM_BUF_EL3_MMAP, 169 #endif 170 #if ENABLE_RME 171 ARM_MAP_GPT_L1_DRAM, 172 ARM_MAP_EL3_RMM_SHARED_MEM, 173 #endif 174 {0} 175 }; 176 177 #if defined(IMAGE_BL31) && SPM_MM 178 const mmap_region_t plat_arm_secure_partition_mmap[] = { 179 V2M_MAP_IOFPGA_EL0, /* for the UART */ 180 MAP_REGION_FLAT(DEVICE0_BASE, \ 181 DEVICE0_SIZE, \ 182 MT_DEVICE | MT_RO | MT_SECURE | MT_USER), 183 ARM_SP_IMAGE_MMAP, 184 ARM_SP_IMAGE_NS_BUF_MMAP, 185 ARM_SP_IMAGE_RW_MMAP, 186 ARM_SPM_BUF_EL0_MMAP, 187 {0} 188 }; 189 #endif 190 #endif 191 #ifdef IMAGE_BL32 192 const mmap_region_t plat_arm_mmap[] = { 193 #ifndef __aarch64__ 194 ARM_MAP_SHARED_RAM, 195 ARM_V2M_MAP_MEM_PROTECT, 196 #endif 197 V2M_MAP_IOFPGA, 198 MAP_DEVICE0, 199 MAP_DEVICE1, 200 {0} 201 }; 202 #endif 203 204 #ifdef IMAGE_RMM 205 const mmap_region_t plat_arm_mmap[] = { 206 V2M_MAP_IOFPGA, 207 MAP_DEVICE0, 208 MAP_DEVICE1, 209 {0} 210 }; 211 #endif 212 213 ARM_CASSERT_MMAP 214 215 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 216 static const int fvp_cci400_map[] = { 217 PLAT_FVP_CCI400_CLUS0_SL_PORT, 218 PLAT_FVP_CCI400_CLUS1_SL_PORT, 219 }; 220 221 static const int fvp_cci5xx_map[] = { 222 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 223 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 224 }; 225 226 static unsigned int get_interconnect_master(void) 227 { 228 unsigned int master; 229 u_register_t mpidr; 230 231 mpidr = read_mpidr_el1(); 232 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ? 233 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 234 235 assert(master < FVP_CLUSTER_COUNT); 236 return master; 237 } 238 #endif 239 240 #if defined(IMAGE_BL31) && SPM_MM 241 /* 242 * Boot information passed to a secure partition during initialisation. Linear 243 * indices in MP information will be filled at runtime. 244 */ 245 static spm_mm_mp_info_t sp_mp_info[] = { 246 [0] = {0x80000000, 0}, 247 [1] = {0x80000001, 0}, 248 [2] = {0x80000002, 0}, 249 [3] = {0x80000003, 0}, 250 [4] = {0x80000100, 0}, 251 [5] = {0x80000101, 0}, 252 [6] = {0x80000102, 0}, 253 [7] = {0x80000103, 0}, 254 }; 255 256 const spm_mm_boot_info_t plat_arm_secure_partition_boot_info = { 257 .h.type = PARAM_SP_IMAGE_BOOT_INFO, 258 .h.version = VERSION_1, 259 .h.size = sizeof(spm_mm_boot_info_t), 260 .h.attr = 0, 261 .sp_mem_base = ARM_SP_IMAGE_BASE, 262 .sp_mem_limit = ARM_SP_IMAGE_LIMIT, 263 .sp_image_base = ARM_SP_IMAGE_BASE, 264 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE, 265 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE, 266 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE, 267 .sp_shared_buf_base = PLAT_SPM_BUF_BASE, 268 .sp_image_size = ARM_SP_IMAGE_SIZE, 269 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE, 270 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE, 271 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE, 272 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE, 273 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS, 274 .num_cpus = PLATFORM_CORE_COUNT, 275 .mp_info = &sp_mp_info[0], 276 }; 277 278 const struct mmap_region *plat_get_secure_partition_mmap(void *cookie) 279 { 280 return plat_arm_secure_partition_mmap; 281 } 282 283 const struct spm_mm_boot_info *plat_get_secure_partition_boot_info( 284 void *cookie) 285 { 286 return &plat_arm_secure_partition_boot_info; 287 } 288 #endif 289 290 /******************************************************************************* 291 * A single boot loader stack is expected to work on both the Foundation FVP 292 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 293 * SYS_ID register provides a mechanism for detecting the differences between 294 * these platforms. This information is stored in a per-BL array to allow the 295 * code to take the correct path.Per BL platform configuration. 296 ******************************************************************************/ 297 void __init fvp_config_setup(void) 298 { 299 unsigned int rev, hbi, bld, arch, sys_id; 300 301 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 302 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 303 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 304 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 305 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 306 307 if (arch != ARCH_MODEL) { 308 ERROR("This firmware is for FVP models\n"); 309 panic(); 310 } 311 312 /* 313 * The build field in the SYS_ID tells which variant of the GIC 314 * memory is implemented by the model. 315 */ 316 switch (bld) { 317 case BLD_GIC_VE_MMAP: 318 ERROR("Legacy Versatile Express memory map for GIC peripheral" 319 " is not supported\n"); 320 panic(); 321 break; 322 case BLD_GIC_A53A57_MMAP: 323 break; 324 default: 325 ERROR("Unsupported board build %x\n", bld); 326 panic(); 327 } 328 329 /* 330 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 331 * for the Foundation FVP. 332 */ 333 switch (hbi) { 334 case HBI_FOUNDATION_FVP: 335 arm_config.flags = 0; 336 337 /* 338 * Check for supported revisions of Foundation FVP 339 * Allow future revisions to run but emit warning diagnostic 340 */ 341 switch (rev) { 342 case REV_FOUNDATION_FVP_V2_0: 343 case REV_FOUNDATION_FVP_V2_1: 344 case REV_FOUNDATION_FVP_v9_1: 345 case REV_FOUNDATION_FVP_v9_6: 346 break; 347 default: 348 WARN("Unrecognized Foundation FVP revision %x\n", rev); 349 break; 350 } 351 break; 352 case HBI_BASE_FVP: 353 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 354 355 /* 356 * Check for supported revisions 357 * Allow future revisions to run but emit warning diagnostic 358 */ 359 switch (rev) { 360 case REV_BASE_FVP_V0: 361 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 362 break; 363 case REV_BASE_FVP_REVC: 364 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 365 ARM_CONFIG_FVP_HAS_CCI5XX); 366 break; 367 default: 368 WARN("Unrecognized Base FVP revision %x\n", rev); 369 break; 370 } 371 break; 372 default: 373 ERROR("Unsupported board HBI number 0x%x\n", hbi); 374 panic(); 375 } 376 377 /* 378 * We assume that the presence of MT bit, and therefore shifted 379 * affinities, is uniform across the platform: either all CPUs, or no 380 * CPUs implement it. 381 */ 382 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U) 383 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 384 } 385 386 387 void __init fvp_interconnect_init(void) 388 { 389 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 390 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 391 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported"); 392 panic(); 393 } 394 395 plat_arm_interconnect_init(); 396 #else 397 uintptr_t cci_base = 0U; 398 const int *cci_map = NULL; 399 unsigned int map_size = 0U; 400 401 /* Initialize the right interconnect */ 402 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) { 403 cci_base = PLAT_FVP_CCI5XX_BASE; 404 cci_map = fvp_cci5xx_map; 405 map_size = ARRAY_SIZE(fvp_cci5xx_map); 406 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) { 407 cci_base = PLAT_FVP_CCI400_BASE; 408 cci_map = fvp_cci400_map; 409 map_size = ARRAY_SIZE(fvp_cci400_map); 410 } else { 411 return; 412 } 413 414 assert(cci_base != 0U); 415 assert(cci_map != NULL); 416 cci_init(cci_base, cci_map, map_size); 417 #endif 418 } 419 420 void fvp_interconnect_enable(void) 421 { 422 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 423 plat_arm_interconnect_enter_coherency(); 424 #else 425 unsigned int master; 426 427 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 428 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 429 master = get_interconnect_master(); 430 cci_enable_snoop_dvm_reqs(master); 431 } 432 #endif 433 } 434 435 void fvp_interconnect_disable(void) 436 { 437 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 438 plat_arm_interconnect_exit_coherency(); 439 #else 440 unsigned int master; 441 442 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 443 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) { 444 master = get_interconnect_master(); 445 cci_disable_snoop_dvm_reqs(master); 446 } 447 #endif 448 } 449 450 #if CRYPTO_SUPPORT 451 int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size) 452 { 453 assert(heap_addr != NULL); 454 assert(heap_size != NULL); 455 456 return arm_get_mbedtls_heap(heap_addr, heap_size); 457 } 458 #endif /* CRYPTO_SUPPORT */ 459 460 void fvp_timer_init(void) 461 { 462 #if USE_SP804_TIMER 463 /* Enable the clock override for SP804 timer 0, which means that no 464 * clock dividers are applied and the raw (35MHz) clock will be used. 465 */ 466 mmio_write_32(V2M_SP810_BASE, FVP_SP810_CTRL_TIM0_OV); 467 468 /* Initialize delay timer driver using SP804 dual timer 0 */ 469 sp804_timer_init(V2M_SP804_TIMER0_BASE, 470 SP804_TIMER_CLKMULT, SP804_TIMER_CLKDIV); 471 #else 472 generic_delay_timer_init(); 473 474 /* Enable System level generic timer */ 475 mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF, 476 CNTCR_FCREQ(0U) | CNTCR_EN); 477 #endif /* USE_SP804_TIMER */ 478 } 479 480 /***************************************************************************** 481 * plat_is_smccc_feature_available() - This function checks whether SMCCC 482 * feature is availabile for platform. 483 * @fid: SMCCC function id 484 * 485 * Return SMC_ARCH_CALL_SUCCESS if SMCCC feature is available and 486 * SMC_ARCH_CALL_NOT_SUPPORTED otherwise. 487 *****************************************************************************/ 488 int32_t plat_is_smccc_feature_available(u_register_t fid) 489 { 490 switch (fid) { 491 case SMCCC_ARCH_SOC_ID: 492 return SMC_ARCH_CALL_SUCCESS; 493 default: 494 return SMC_ARCH_CALL_NOT_SUPPORTED; 495 } 496 } 497 498 /* Get SOC version */ 499 int32_t plat_get_soc_version(void) 500 { 501 return (int32_t) 502 (SOC_ID_SET_JEP_106(ARM_SOC_CONTINUATION_CODE, 503 ARM_SOC_IDENTIFICATION_CODE) | 504 (FVP_SOC_ID & SOC_ID_IMPL_DEF_MASK)); 505 } 506 507 /* Get SOC revision */ 508 int32_t plat_get_soc_revision(void) 509 { 510 unsigned int sys_id; 511 512 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 513 return (int32_t)(((sys_id >> V2M_SYS_ID_REV_SHIFT) & 514 V2M_SYS_ID_REV_MASK) & SOC_ID_REV_MASK); 515 } 516 517 #if ENABLE_RME 518 /* 519 * Get a pointer to the RMM-EL3 Shared buffer and return it 520 * through the pointer passed as parameter. 521 * 522 * This function returns the size of the shared buffer. 523 */ 524 size_t plat_rmmd_get_el3_rmm_shared_mem(uintptr_t *shared) 525 { 526 *shared = (uintptr_t)RMM_SHARED_BASE; 527 528 return (size_t)RMM_SHARED_SIZE; 529 } 530 #endif 531