Derive stack alignment from CACHE_WRITEBACK_GRANULE

The per-cpu stacks should be aligned to the cache-line size and
the `declare_stack` helper in asm_macros.S macro assumed a
cache-line size of 64 b

Derive stack alignment from CACHE_WRITEBACK_GRANULE

The per-cpu stacks should be aligned to the cache-line size and
the `declare_stack` helper in asm_macros.S macro assumed a
cache-line size of 64 bytes. The platform defines the cache-line
size via CACHE_WRITEBACK_GRANULE macro. This patch modifies
`declare_stack` helper macro to derive stack alignment from the
platform defined macro.

Change-Id: I1e1b00fc8806ecc88190ed169f4c8d3dd25fe95b

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Merge pull request #651 from Xilinx/zynqmp_uart

zynqmp: Make UART selectable

Merge pull request #652 from soby-mathew/sm/pmf_psci_stat

Introduce PMF and implement PSCI STAT APIs

Enable PSCI_STAT_COUNT/RESIDENCY for ARM standard platforms

This patch enables optional PSCI functions `PSCI_STAT_COUNT` and
`PSCI_STAT_RESIDENCY` for ARM standard platforms. The optional platform
A

Enable PSCI_STAT_COUNT/RESIDENCY for ARM standard platforms

This patch enables optional PSCI functions `PSCI_STAT_COUNT` and
`PSCI_STAT_RESIDENCY` for ARM standard platforms. The optional platform
API 'translate_power_state_by_mpidr()' is implemented for the Juno
platform. 'validate_power_state()' on Juno downgrades PSCI CPU_SUSPEND
requests for the system power level to the cluster power level.
Hence, it is not suitable for validating the 'power_state' parameter
passed in a PSCI_STAT_COUNT/RESIDENCY call.

Change-Id: I9548322676fa468d22912392f2325c2a9f96e4d2

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zynqmp: Add option to select between Cadence UARTs

Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd
UART available in the SoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@x

zynqmp: Add option to select between Cadence UARTs

Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd
UART available in the SoC.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>

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Merge pull request #650 from Xilinx/zynqmp-updates

Zynqmp updates

Merge pull request #646 from davwan01/dw/gicv3-wakeup

CSS: Add support to wake up the core from wfi in GICv3

Add support for QEMU virt ARMv8-A target

This patch adds support for the QEMU virt ARMv8-A target.

Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>

CSS: Add support to wake up the core from wfi in GICv3

In GICv3 mode, the non secure group1 interrupts are signalled via the
FIQ line in EL3. To support waking up from CPU_SUSPEND to standby on
thes

CSS: Add support to wake up the core from wfi in GICv3

In GICv3 mode, the non secure group1 interrupts are signalled via the
FIQ line in EL3. To support waking up from CPU_SUSPEND to standby on
these systems, EL3 should route FIQ to EL3 temporarily before wfi and
restore the original setting after resume. This patch makes this change
for the CSS platforms in the `css_cpu_standby` psci pm ops hook.

Change-Id: Ibf3295d16e2f08da490847c1457bc839e1bac144

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zynqmp: pm: Added NODE_IPI_APU slave node ID in pm_defs.h

NODE_IPI_APU is the node ID of APU's IPI device. If APU should be
woken-up on an IPI from FPD power down, this node shall be set as
the wake

zynqmp: pm: Added NODE_IPI_APU slave node ID in pm_defs.h

NODE_IPI_APU is the node ID of APU's IPI device. If APU should be
woken-up on an IPI from FPD power down, this node shall be set as
the wake-up source upon suspend.

Signed-off-by: Mirela Simonovic <mirela.simonovic@aggios.com>

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Merge pull request #641 from antonio-nino-diaz-arm/an/fvp-set-nv-ctr

Implement plat_set_nv_ctr for FVP platforms

Merge pull request #640 from sandrine-bailleux-arm/sb/fix-syntax-error

Fix a syntax error in plat/arm/common/aarch64/arm_common.c

Merge pull request #637 from yatharth-arm/yk/genfw-1134

Add support for ARM Cortex-A73 MPCore Processor

Fix a syntax error

Building TF with ERROR_DEPRECATED=1 fails because of a missing
semi-column. This patch fixes this syntax error.

Change-Id: I98515840ce74245b0a0215805f85c8e399094f68

Implement plat_set_nv_ctr for FVP platforms

Replaced placeholder implementation of plat_set_nv_ctr for FVP
platforms by a working one.

On FVP, the mapping of region DEVICE2 has been changed from RO

Implement plat_set_nv_ctr for FVP platforms

Replaced placeholder implementation of plat_set_nv_ctr for FVP
platforms by a working one.

On FVP, the mapping of region DEVICE2 has been changed from RO to RW
to prevent exceptions when writing to the NV counter, which is
contained in this region.

Change-Id: I56a49631432ce13905572378cbdf106f69c82f57

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Add support for ARM Cortex-A73 MPCore Processor

This patch adds ARM Cortex-A73 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.

Add support for ARM Cortex-A73 MPCore Processor

This patch adds ARM Cortex-A73 MPCore Processor support
in the CPU specific operations framework. It also includes
this support for the Base FVP port.

Change-Id: I0e26b594f2ec1d28eb815db9810c682e3885716d

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zynqmp: Remove double ';'

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

zynqmp: Fix spelling of endianness

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

Merge pull request #632 from rockchip-linux/support-for-gpio-driver-v2

rockchip/rk3399: Support the gpio driver and configure

rockchip: support system off function for rk3399

if define power off gpio, BL31 will do system power off through
gpio control.

rockchip: support reset SoC through gpio for rk3399

If define a reset gpio, BL31 will use gpio to reset SOC,
otherwise use CRU reset.

rockchip: add reset or power off gpio configuration for rk3399

We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured a

rockchip: add reset or power off gpio configuration for rk3399

We add plat parameter structs to support BL2 to pass variable-length,
variable-type parameters to BL31. The parameters are structured as a
link list. During bl31 setup time, we travse the list to process each
parameter. throuth this way, we can get the reset or power off gpio
parameter, and do hardware control in BL31. This structure also can
pass other parameter to BL31 in future.

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rockchip: support rk3399 gpio driver

There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-program

rockchip: support rk3399 gpio driver

There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.

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zynqmp: PSCI: Wait for FW completing wake requests

Powering up cores didn't wait for the PMUFW to complete the request,
which could result in cores failing to power up in Linux.

Reported-by: Kotesw

zynqmp: PSCI: Wait for FW completing wake requests

Powering up cores didn't wait for the PMUFW to complete the request,
which could result in cores failing to power up in Linux.

Reported-by: Koteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>

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Add CCN support to FVP platform port

This patch adds support to select CCN driver for FVP during build.
A new build option `FVP_INTERCONNECT_DRIVER` is added to allow
selection between the CCI and C

Add CCN support to FVP platform port

This patch adds support to select CCN driver for FVP during build.
A new build option `FVP_INTERCONNECT_DRIVER` is added to allow
selection between the CCI and CCN driver. Currently only the CCN-502
variant is supported on FVP.

The common ARM CCN platform helper file now verifies the cluster
count declared by platform is equal to the number of root node
masters exported by the ARM Standard platform.

Change-Id: I71d7b4785f8925ed499c153b2e9b9925fcefd57a

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