1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <arch_helpers.h> 32 #include <assert.h> 33 #include <cassert.h> 34 #include <css_pm.h> 35 #include <debug.h> 36 #include <errno.h> 37 #include <plat_arm.h> 38 #include <platform.h> 39 #include <platform_def.h> 40 #include "css_scpi.h" 41 42 /* Macros to read the CSS power domain state */ 43 #define CSS_CORE_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL0] 44 #define CSS_CLUSTER_PWR_STATE(state) (state)->pwr_domain_state[ARM_PWR_LVL1] 45 #define CSS_SYSTEM_PWR_STATE(state) ((PLAT_MAX_PWR_LVL > ARM_PWR_LVL1) ?\ 46 (state)->pwr_domain_state[ARM_PWR_LVL2] : 0) 47 48 /* Allow CSS platforms to override `plat_arm_psci_pm_ops` */ 49 #pragma weak plat_arm_psci_pm_ops 50 51 #if ARM_RECOM_STATE_ID_ENC 52 /* 53 * The table storing the valid idle power states. Ensure that the 54 * array entries are populated in ascending order of state-id to 55 * enable us to use binary search during power state validation. 56 * The table must be terminated by a NULL entry. 57 */ 58 const unsigned int arm_pm_idle_states[] = { 59 /* State-id - 0x001 */ 60 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 61 ARM_LOCAL_STATE_RET, ARM_PWR_LVL0, PSTATE_TYPE_STANDBY), 62 /* State-id - 0x002 */ 63 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_RUN, 64 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL0, PSTATE_TYPE_POWERDOWN), 65 /* State-id - 0x022 */ 66 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_RUN, ARM_LOCAL_STATE_OFF, 67 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL1, PSTATE_TYPE_POWERDOWN), 68 #if PLAT_MAX_PWR_LVL > ARM_PWR_LVL1 69 /* State-id - 0x222 */ 70 arm_make_pwrstate_lvl2(ARM_LOCAL_STATE_OFF, ARM_LOCAL_STATE_OFF, 71 ARM_LOCAL_STATE_OFF, ARM_PWR_LVL2, PSTATE_TYPE_POWERDOWN), 72 #endif 73 0, 74 }; 75 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 76 77 /* 78 * All the power management helpers in this file assume at least cluster power 79 * level is supported. 80 */ 81 CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1, 82 assert_max_pwr_lvl_supported_mismatch); 83 84 /******************************************************************************* 85 * Handler called when a power domain is about to be turned on. The 86 * level and mpidr determine the affinity instance. 87 ******************************************************************************/ 88 int css_pwr_domain_on(u_register_t mpidr) 89 { 90 /* 91 * SCP takes care of powering up parent power domains so we 92 * only need to care about level 0 93 */ 94 scpi_set_css_power_state(mpidr, scpi_power_on, scpi_power_on, 95 scpi_power_on); 96 97 return PSCI_E_SUCCESS; 98 } 99 100 static void css_pwr_domain_on_finisher_common( 101 const psci_power_state_t *target_state) 102 { 103 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 104 105 /* 106 * Perform the common cluster specific operations i.e enable coherency 107 * if this cluster was off. 108 */ 109 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 110 plat_arm_interconnect_enter_coherency(); 111 } 112 113 /******************************************************************************* 114 * Handler called when a power level has just been powered on after 115 * being turned off earlier. The target_state encodes the low power state that 116 * each level has woken up from. This handler would never be invoked with 117 * the system power domain uninitialized as either the primary would have taken 118 * care of it as part of cold boot or the first core awakened from system 119 * suspend would have already initialized it. 120 ******************************************************************************/ 121 void css_pwr_domain_on_finish(const psci_power_state_t *target_state) 122 { 123 /* Assert that the system power domain need not be initialized */ 124 assert(CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_RUN); 125 126 css_pwr_domain_on_finisher_common(target_state); 127 128 /* Program the gic per-cpu distributor or re-distributor interface */ 129 plat_arm_gic_pcpu_init(); 130 131 /* Enable the gic cpu interface */ 132 plat_arm_gic_cpuif_enable(); 133 } 134 135 /******************************************************************************* 136 * Common function called while turning a cpu off or suspending it. It is called 137 * from css_off() or css_suspend() when these functions in turn are called for 138 * power domain at the highest power level which will be powered down. It 139 * performs the actions common to the OFF and SUSPEND calls. 140 ******************************************************************************/ 141 static void css_power_down_common(const psci_power_state_t *target_state) 142 { 143 uint32_t cluster_state = scpi_power_on; 144 uint32_t system_state = scpi_power_on; 145 146 /* Prevent interrupts from spuriously waking up this cpu */ 147 plat_arm_gic_cpuif_disable(); 148 149 /* Check if power down at system power domain level is requested */ 150 if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 151 system_state = scpi_power_retention; 152 153 /* Cluster is to be turned off, so disable coherency */ 154 if (CSS_CLUSTER_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) { 155 plat_arm_interconnect_exit_coherency(); 156 cluster_state = scpi_power_off; 157 } 158 159 /* 160 * Ask the SCP to power down the appropriate components depending upon 161 * their state. 162 */ 163 scpi_set_css_power_state(read_mpidr_el1(), 164 scpi_power_off, 165 cluster_state, 166 system_state); 167 } 168 169 /******************************************************************************* 170 * Handler called when a power domain is about to be turned off. The 171 * target_state encodes the power state that each level should transition to. 172 ******************************************************************************/ 173 void css_pwr_domain_off(const psci_power_state_t *target_state) 174 { 175 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 176 css_power_down_common(target_state); 177 } 178 179 /******************************************************************************* 180 * Handler called when a power domain is about to be suspended. The 181 * target_state encodes the power state that each level should transition to. 182 ******************************************************************************/ 183 void css_pwr_domain_suspend(const psci_power_state_t *target_state) 184 { 185 /* 186 * CSS currently supports retention only at cpu level. Just return 187 * as nothing is to be done for retention. 188 */ 189 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 190 return; 191 192 assert(CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF); 193 css_power_down_common(target_state); 194 } 195 196 /******************************************************************************* 197 * Handler called when a power domain has just been powered on after 198 * having been suspended earlier. The target_state encodes the low power state 199 * that each level has woken up from. 200 * TODO: At the moment we reuse the on finisher and reinitialize the secure 201 * context. Need to implement a separate suspend finisher. 202 ******************************************************************************/ 203 void css_pwr_domain_suspend_finish( 204 const psci_power_state_t *target_state) 205 { 206 /* Return as nothing is to be done on waking up from retention. */ 207 if (CSS_CORE_PWR_STATE(target_state) == ARM_LOCAL_STATE_RET) 208 return; 209 210 /* Perform system domain restore if woken up from system suspend */ 211 if (CSS_SYSTEM_PWR_STATE(target_state) == ARM_LOCAL_STATE_OFF) 212 arm_system_pwr_domain_resume(); 213 else 214 /* Enable the gic cpu interface */ 215 plat_arm_gic_cpuif_enable(); 216 217 css_pwr_domain_on_finisher_common(target_state); 218 } 219 220 /******************************************************************************* 221 * Handlers to shutdown/reboot the system 222 ******************************************************************************/ 223 void __dead2 css_system_off(void) 224 { 225 uint32_t response; 226 227 /* Send the power down request to the SCP */ 228 response = scpi_sys_power_state(scpi_system_shutdown); 229 230 if (response != SCP_OK) { 231 ERROR("CSS System Off: SCP error %u.\n", response); 232 panic(); 233 } 234 wfi(); 235 ERROR("CSS System Off: operation not handled.\n"); 236 panic(); 237 } 238 239 void __dead2 css_system_reset(void) 240 { 241 uint32_t response; 242 243 /* Send the system reset request to the SCP */ 244 response = scpi_sys_power_state(scpi_system_reboot); 245 246 if (response != SCP_OK) { 247 ERROR("CSS System Reset: SCP error %u.\n", response); 248 panic(); 249 } 250 wfi(); 251 ERROR("CSS System Reset: operation not handled.\n"); 252 panic(); 253 } 254 255 /******************************************************************************* 256 * Handler called when the CPU power domain is about to enter standby. 257 ******************************************************************************/ 258 void css_cpu_standby(plat_local_state_t cpu_state) 259 { 260 unsigned int scr; 261 262 assert(cpu_state == ARM_LOCAL_STATE_RET); 263 264 scr = read_scr_el3(); 265 /* 266 * Enable the Non secure interrupt to wake the CPU. 267 * In GICv3 affinity routing mode, the non secure group1 interrupts use 268 * the PhysicalFIQ at EL3 whereas in GICv2, it uses the PhysicalIRQ. 269 * Enabling both the bits works for both GICv2 mode and GICv3 affinity 270 * routing mode. 271 */ 272 write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT); 273 isb(); 274 dsb(); 275 wfi(); 276 277 /* 278 * Restore SCR to the original value, synchronisation of scr_el3 is 279 * done by eret while el3_exit to save some execution cycles. 280 */ 281 write_scr_el3(scr); 282 } 283 284 /******************************************************************************* 285 * Handler called to return the 'req_state' for system suspend. 286 ******************************************************************************/ 287 void css_get_sys_suspend_power_state(psci_power_state_t *req_state) 288 { 289 unsigned int i; 290 291 /* 292 * System Suspend is supported only if the system power domain node 293 * is implemented. 294 */ 295 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 296 297 for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++) 298 req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF; 299 } 300 301 /******************************************************************************* 302 * Handler to query CPU/cluster power states from SCP 303 ******************************************************************************/ 304 int css_node_hw_state(u_register_t mpidr, unsigned int power_level) 305 { 306 int rc, element; 307 unsigned int cpu_state, cluster_state; 308 309 /* 310 * The format of 'power_level' is implementation-defined, but 0 must 311 * mean a CPU. We also allow 1 to denote the cluster 312 */ 313 if (power_level != ARM_PWR_LVL0 && power_level != ARM_PWR_LVL1) 314 return PSCI_E_INVALID_PARAMS; 315 316 /* Query SCP */ 317 rc = scpi_get_css_power_state(mpidr, &cpu_state, &cluster_state); 318 if (rc != 0) 319 return PSCI_E_INVALID_PARAMS; 320 321 /* Map power states of CPU and cluster to expected PSCI return codes */ 322 if (power_level == ARM_PWR_LVL0) { 323 /* 324 * The CPU state returned by SCP is an 8-bit bit mask 325 * corresponding to each CPU in the cluster 326 */ 327 element = mpidr & MPIDR_AFFLVL_MASK; 328 return CSS_CPU_PWR_STATE(cpu_state, element) == 329 CSS_CPU_PWR_STATE_ON ? HW_ON : HW_OFF; 330 } else { 331 assert(cluster_state == CSS_CLUSTER_PWR_STATE_ON || 332 cluster_state == CSS_CLUSTER_PWR_STATE_OFF); 333 return cluster_state == CSS_CLUSTER_PWR_STATE_ON ? HW_ON : 334 HW_OFF; 335 } 336 } 337 338 /******************************************************************************* 339 * Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard 340 * platform will take care of registering the handlers with PSCI. 341 ******************************************************************************/ 342 const plat_psci_ops_t plat_arm_psci_pm_ops = { 343 .pwr_domain_on = css_pwr_domain_on, 344 .pwr_domain_on_finish = css_pwr_domain_on_finish, 345 .pwr_domain_off = css_pwr_domain_off, 346 .cpu_standby = css_cpu_standby, 347 .pwr_domain_suspend = css_pwr_domain_suspend, 348 .pwr_domain_suspend_finish = css_pwr_domain_suspend_finish, 349 .system_off = css_system_off, 350 .system_reset = css_system_reset, 351 .validate_power_state = arm_validate_power_state, 352 .validate_ns_entrypoint = arm_validate_ns_entrypoint, 353 .get_node_hw_state = css_node_hw_state 354 }; 355