1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __CSS_DEF_H__ 32 #define __CSS_DEF_H__ 33 34 #include <arm_def.h> 35 #include <tzc400.h> 36 37 /************************************************************************* 38 * Definitions common to all ARM Compute SubSystems (CSS) 39 *************************************************************************/ 40 #define NSROM_BASE 0x1f000000 41 #define NSROM_SIZE 0x00001000 42 43 /* Following covers CSS Peripherals excluding NSROM and NSRAM */ 44 #define CSS_DEVICE_BASE 0x20000000 45 #define CSS_DEVICE_SIZE 0x0e000000 46 47 #define NSRAM_BASE 0x2e000000 48 #define NSRAM_SIZE 0x00008000 49 50 /* System Security Control Registers */ 51 #define SSC_REG_BASE 0x2a420000 52 #define SSC_GPRETN (SSC_REG_BASE + 0x030) 53 54 /* The slave_bootsecure controls access to GPU, DMC and CS. */ 55 #define CSS_NIC400_SLAVE_BOOTSECURE 8 56 57 /* Interrupt handling constants */ 58 #define CSS_IRQ_MHU 69 59 #define CSS_IRQ_GPU_SMMU_0 71 60 #define CSS_IRQ_TZC 80 61 #define CSS_IRQ_TZ_WDOG 86 62 #define CSS_IRQ_SEC_SYS_TIMER 91 63 64 /* 65 * Define a list of Group 1 Secure interrupts as per GICv3 terminology. On a 66 * GICv2 system or mode, the interrupts will be treated as Group 0 interrupts. 67 */ 68 #define CSS_G1S_IRQS CSS_IRQ_MHU, \ 69 CSS_IRQ_GPU_SMMU_0, \ 70 CSS_IRQ_TZC, \ 71 CSS_IRQ_TZ_WDOG, \ 72 CSS_IRQ_SEC_SYS_TIMER 73 74 /* 75 * SCP <=> AP boot configuration 76 * 77 * The SCP/AP boot configuration is a 32-bit word located at a known offset from 78 * the start of the Trusted SRAM. 79 * 80 * Note that the value stored at this address is only valid at boot time, before 81 * the SCP_BL2 image is transferred to SCP. 82 */ 83 #define SCP_BOOT_CFG_ADDR PLAT_CSS_SCP_COM_SHARED_MEM_BASE 84 85 #define CSS_MAP_DEVICE MAP_REGION_FLAT( \ 86 CSS_DEVICE_BASE, \ 87 CSS_DEVICE_SIZE, \ 88 MT_DEVICE | MT_RW | MT_SECURE) 89 90 /* Platform ID address */ 91 #define SSC_VERSION_OFFSET 0x040 92 93 #define SSC_VERSION_CONFIG_SHIFT 28 94 #define SSC_VERSION_MAJOR_REV_SHIFT 24 95 #define SSC_VERSION_MINOR_REV_SHIFT 20 96 #define SSC_VERSION_DESIGNER_ID_SHIFT 12 97 #define SSC_VERSION_PART_NUM_SHIFT 0x0 98 #define SSC_VERSION_CONFIG_MASK 0xf 99 #define SSC_VERSION_MAJOR_REV_MASK 0xf 100 #define SSC_VERSION_MINOR_REV_MASK 0xf 101 #define SSC_VERSION_DESIGNER_ID_MASK 0xff 102 #define SSC_VERSION_PART_NUM_MASK 0xfff 103 104 #ifndef __ASSEMBLY__ 105 106 /* SSC_VERSION related accessors */ 107 108 /* Returns the part number of the platform */ 109 #define GET_SSC_VERSION_PART_NUM(val) \ 110 (((val) >> SSC_VERSION_PART_NUM_SHIFT) & \ 111 SSC_VERSION_PART_NUM_MASK) 112 113 /* Returns the configuration number of the platform */ 114 #define GET_SSC_VERSION_CONFIG(val) \ 115 (((val) >> SSC_VERSION_CONFIG_SHIFT) & \ 116 SSC_VERSION_CONFIG_MASK) 117 118 #endif /* __ASSEMBLY__ */ 119 120 /************************************************************************* 121 * Required platform porting definitions common to all 122 * ARM Compute SubSystems (CSS) 123 ************************************************************************/ 124 125 /* 126 * The loading of SCP images(SCP_BL2 or SCP_BL2U) is done if there 127 * respective base addresses are defined (i.e SCP_BL2_BASE, SCP_BL2U_BASE). 128 * Hence, `CSS_LOAD_SCP_IMAGES` needs to be set to 1 if BL2 needs to load 129 * an SCP_BL2/SCP_BL2U image. 130 */ 131 #if CSS_LOAD_SCP_IMAGES 132 /* 133 * Load address of SCP_BL2 in CSS platform ports 134 * SCP_BL2 is loaded to the same place as BL31. Once SCP_BL2 is transferred to the 135 * SCP, it is discarded and BL31 is loaded over the top. 136 */ 137 #define SCP_BL2_BASE BL31_BASE 138 139 #define SCP_BL2U_BASE BL31_BASE 140 #endif /* CSS_LOAD_SCP_IMAGES */ 141 142 /* Load address of Non-Secure Image for CSS platform ports */ 143 #define PLAT_ARM_NS_IMAGE_OFFSET 0xE0000000 144 145 /* TZC related constants */ 146 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT_ALL 147 148 /* Trusted mailbox base address common to all CSS */ 149 #define PLAT_ARM_TRUSTED_MAILBOX_BASE ARM_TRUSTED_SRAM_BASE 150 151 /* 152 * Parsing of CPU and Cluster states, as returned by 'Get CSS Power State' SCP 153 * command 154 */ 155 #define CSS_CLUSTER_PWR_STATE_ON 0 156 #define CSS_CLUSTER_PWR_STATE_OFF 3 157 158 #define CSS_CPU_PWR_STATE_ON 1 159 #define CSS_CPU_PWR_STATE_OFF 0 160 #define CSS_CPU_PWR_STATE(state, n) (((state) >> (n)) & 1) 161 162 #endif /* __CSS_DEF_H__ */ 163