Merge pull request #1082 from vchong/load_img_v2_parse_optee_header

hikey*: Add LOAD_IMAGE_V2 and OP-TEE header parsing support

Merge pull request #1080 from soby-mathew/eb/RSA-PKCS1-5_support_1

Support legacy RSA PKCS#1 v1.5 in cert create

CSS: Changes for SDS framework

This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI b

CSS: Changes for SDS framework

This patch does the required changes to enable CSS platforms
to build and use the SDS framework. Since SDS is always coupled with
SCMI protocol, the preexisting SCMI build flag is now renamed to
`CSS_USE_SCMI_SDS_DRIVER` which will enable both SCMI and SDS on
CSS platforms. Also some of the workarounds applied for SCMI are
now removed with SDS in place.

Change-Id: I94e8b93f05e3fe95e475c5501c25bec052588a9c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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SDS: Introduce the sds drivers

This patch introduces the driver for Shared-Data-Structure (SDS)
framework which will be used for communication between SCP and AP
CPU. The SDS framework is intended t

SDS: Introduce the sds drivers

This patch introduces the driver for Shared-Data-Structure (SDS)
framework which will be used for communication between SCP and AP
CPU. The SDS framework is intended to replace the Boot-Over-MHU
(BOM) protocol used currently for the communication

Change-Id: Ic174291121f4e581b174cce3389d22d6435f7269
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Split CSS makefile for sp_min on Juno

This patch factors out common files required for sp_min for all CSS
platforms from the JUNO specific makefile to a the new `css_sp_min.mk`
makefile. This also a

Split CSS makefile for sp_min on Juno

This patch factors out common files required for sp_min for all CSS
platforms from the JUNO specific makefile to a the new `css_sp_min.mk`
makefile. This also allows the common build options that affect CSS
platforms to be configured in a central makefile for sp_min.

Change-Id: Ida952d8833b1aa5eda77ae0a6664a4632aeab24c
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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juno: Fix bug in plat_get_my_entrypoint

plat_get_my_entrypoint was branching to juno_do_reset_to_aarch_32_state,
which is not supposed to return, and in case of returning it implemented
an infinite

juno: Fix bug in plat_get_my_entrypoint

plat_get_my_entrypoint was branching to juno_do_reset_to_aarch_32_state,
which is not supposed to return, and in case of returning it implemented
an infinite loop. The problem was that plat_get_my_entrypoint was using
"b" instead of "bl", so juno_do_reset_to_aarch_32_state was returning to
the caller of plat_get_my_entrypoint instead of stop the system with a
panic.

To avoid this problem juno_do_reset_to_aarch_32_state was modified to
call directly to plat_panic_handler if it tries to return.

Change-Id: I591cf2dd78d27d8568fb15b91366e4b3dce027b5
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Fix BL2 memory map when OP-TEE is the Secure Payload

The commit 3eb2d67 optimizes the memory map for BL2 when TSP
is not present. But this also broke OP-TEE as it was reusing
the TSP mapping. This p

Fix BL2 memory map when OP-TEE is the Secure Payload

The commit 3eb2d67 optimizes the memory map for BL2 when TSP
is not present. But this also broke OP-TEE as it was reusing
the TSP mapping. This patch fixes this problem by adding a
separate mapping for OP-TEE in the BL2 memory map table.

Change-Id: I130a2ea552b7b62d8478081feb1f4ddf5292a118
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1081 from masahir0y/uniphier

uniphier: fix-up for PXs3 SoC

hikey*: Support Trusted OS extra image (OP-TEE header) parsing

Signed-off-by: Victor Chong <victor.chong@linaro.org>

hikey*: Add LOAD_IMAGE_V2 support

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>

uniphier: work around Boot ROM bug for USB boot mode of PXs3 SoC

Due to a bug in the Boot ROM, the USB load API turned out not working
as expected. It is unfixable because the Boot ROM is hard-wire

uniphier: work around Boot ROM bug for USB boot mode of PXs3 SoC

Due to a bug in the Boot ROM, the USB load API turned out not working
as expected. It is unfixable because the Boot ROM is hard-wired.

Add work around code in TF to bypass the problematic Boot ROM code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: fix code indent for conditional statement

checkpatch.pl from Linux reports tons of coding style errors and
warnings. I am just fixing under plat/socionext/uniphier/.

Signed-off-by: Masah

uniphier: fix code indent for conditional statement

checkpatch.pl from Linux reports tons of coding style errors and
warnings. I am just fixing under plat/socionext/uniphier/.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge pull request #1072 from sandrine-bailleux-arm/sb/tsp-mapping

ARM platforms: Map TSP only when TSPD is included

Export KEY_ALG as a user build option

The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undoc

Export KEY_ALG as a user build option

The `KEY_ALG` variable is used to select the algorithm for key
generation by `cert_create` tool for signing the certificates. This
variable was previously undocumented and did not have a global default
value. This patch corrects this and also adds changes to derive the
value of `TF_MBEDTLS_KEY_ALG` based on `KEY_ALG` if it not set by the
platform. The corresponding assignment of these variables are also now
removed from the `arm_common.mk` makefile.

Signed-off-by: Soby Mathew <soby.mathew@arm.com>
Change-Id: I78e2d6f4fc04ed5ad35ce2266118afb63127a5a4

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ARM platforms: Map TSP only when TSPD is included

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry

ARM platforms: Map TSP only when TSPD is included

This patch ensures that the ARM_MAP_TSP_SEC_MEM memory region is mapped
in BL2 only if the TSPD has been included in the build. This saves one
entry in the plat_arm_mmap[] array and avoids to map extra memory when
it's not needed.

Change-Id: I6ae60822ff8f0de198145925b0b0d45355179a94
Signed-off-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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Merge pull request #1077 from soby-mathew/sm/fix_juno_assert_lvl

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`ass

Juno: Define PLAT_LOG_LEVEL_ASSERT to LOG_LEVEL_INFO

This patch fixes the PLAT_LOG_LEVEL_ASSERT to 40 which corresponds
to LOG_LEVEL_INFO. Having this level of log for assertions means that the
`assert()` will not generate the strings implied in the expression taken
as parameter. This allows to save some memory when Juno is built for
LOG_LEVEL = LOG_LEVEL_VERBOSE and DEBUG = 1.

Fixes ARM-software/tf-issues#511

Change-Id: Id84a40f803ab07a5a8f6e587167af96694a07d04
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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Merge pull request #1069 from Leo-Yan/hikey_enable_watchdog_reset

Hikey: enable watchdog reset

Merge pull request #1075 from robertovargas-arm/fix_el3_payload

Don't use zero_normalmem in bl2_platform_setup

Don't use zero_normalmem in bl2_platform_setup

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of E

Don't use zero_normalmem in bl2_platform_setup

zero_normalmem only can zero memory when caches are enabled
and the target memory is a normal memory, otherwise an abort is
generated. In the case of EL3_PAYLOAD_BASE bl2_platform_setup was
calling zero_normalmem with device memory and it generated an abort.

Change-Id: If013603f209a12af488a9c54481f97a8f395b26a
Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>

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Merge pull request #1062 from jeenu-arm/cpu-fixes

Cpu macro fixes

Merge pull request #1071 from jeenu-arm/syntax-fix

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*

CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch re

Tegra: Rename CORTEX_A57_ACTLR_EL1 to *CPUACTLR*

CORTEX_A57_ACTLR_EL1 macro refers to the CPUACTLR_EL1 register. Since
ACTLR_EL1 is a different register (not implemented in Cortex-A57) this
patch renames this macro for clarity.

Change-Id: I94d7d564cd2423ae032bbdd59a99d2dc535cdff6
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

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HiKey: Rename CPUACTRL reg constants

Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register.
Since ACTLR and ACTRL_EL1 are different registers this patch renames
these constants for c

HiKey: Rename CPUACTRL reg constants

Constants named as *ACTLR* refer in fact to the CPUACTRL_EL1 register.
Since ACTLR and ACTRL_EL1 are different registers this patch renames
these constants for clarity.

Change-Id: I2a9e402dab7b0fcb6e481ee0d8a11eda943ed299
Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>

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plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

The current definition of ARM_INSTANTIATE_LOCK macro includes a
semicolon, which means it's omitted where it's used. This is anomalous
for a C state

plat/arm: Fix ARM_INSTANTIATE_LOCK syntax anomaly

The current definition of ARM_INSTANTIATE_LOCK macro includes a
semicolon, which means it's omitted where it's used. This is anomalous
for a C statement in global scope.

Fix this by removing semicolon from the definition; and where it's a
NOP, declare a file-scoped variable explicitly tagged as unused to avoid
compiler warning.

No functional changes.

Change-Id: I2c1d92ece4777e272a025011e03b8003f3543335
Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>

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