1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __CORTEX_A72_H__ 8 #define __CORTEX_A72_H__ 9 #include <utils_def.h> 10 11 /* Cortex-A72 midr for revision 0 */ 12 #define CORTEX_A72_MIDR 0x410FD080 13 14 /******************************************************************************* 15 * CPU Extended Control register specific definitions. 16 ******************************************************************************/ 17 #define CORTEX_A72_ECTLR p15, 1, c15 18 19 #define CORTEX_A72_ECTLR_SMP_BIT (ULL(1) << 6) 20 #define CORTEX_A72_ECTLR_DIS_TWD_ACC_PFTCH_BIT (ULL(1) << 38) 21 #define CORTEX_A72_ECTLR_L2_IPFTCH_DIST_MASK (ULL(0x3) << 35) 22 #define CORTEX_A72_ECTLR_L2_DPFTCH_DIST_MASK (ULL(0x3) << 32) 23 24 /******************************************************************************* 25 * CPU Memory Error Syndrome register specific definitions. 26 ******************************************************************************/ 27 #define CORTEX_A72_MERRSR p15, 2, c15 28 29 /******************************************************************************* 30 * CPU Auxiliary Control register specific definitions. 31 ******************************************************************************/ 32 #define CORTEX_A72_CPUACTLR p15, 0, c15 33 34 #define CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (ULL(1) << 56) 35 #define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49) 36 #define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44) 37 38 /******************************************************************************* 39 * L2 Control register specific definitions. 40 ******************************************************************************/ 41 #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2 42 43 #define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT 0 44 #define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT 6 45 46 #define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES 0x2 47 #define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES 0x1 48 #define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES 0x2 49 50 /******************************************************************************* 51 * L2 Memory Error Syndrome register specific definitions. 52 ******************************************************************************/ 53 #define CORTEX_A72_L2MERRSR p15, 3, c15 54 55 #if !ERROR_DEPRECATED 56 /* 57 * These registers were previously wrongly named. Provide previous definitions so 58 * as not to break platforms that continue using them. 59 */ 60 #define CORTEX_A72_ACTLR CORTEX_A72_CPUACTLR 61 62 #define CORTEX_A72_ACTLR_DISABLE_L1_DCACHE_HW_PFTCH CORTEX_A72_CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH 63 #define CORTEX_A72_ACTLR_NO_ALLOC_WBWA CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA 64 #define CORTEX_A72_ACTLR_DCC_AS_DCCI CORTEX_A72_CPUACTLR_DCC_AS_DCCI 65 #endif /* !ERROR_DEPRECATED */ 66 67 #endif /* __CORTEX_A72_H__ */ 68