1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <bl_common.h> 10 #include <console.h> 11 #include <debug.h> 12 #include <desc_image_load.h> 13 #include <dw_mmc.h> 14 #include <emmc.h> 15 #include <errno.h> 16 #include <hi6220.h> 17 #include <hisi_mcu.h> 18 #include <hisi_sram_map.h> 19 #include <mmio.h> 20 #include <platform_def.h> 21 #include <sp804_delay_timer.h> 22 #include <string.h> 23 24 #include "hikey_def.h" 25 #include "hikey_private.h" 26 27 /* 28 * The next 2 constants identify the extents of the code & RO data region. 29 * These addresses are used by the MMU setup code and therefore they must be 30 * page-aligned. It is the responsibility of the linker script to ensure that 31 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. 32 */ 33 #define BL2_RO_BASE (unsigned long)(&__RO_START__) 34 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__) 35 36 /* 37 * The next 2 constants identify the extents of the coherent memory region. 38 * These addresses are used by the MMU setup code and therefore they must be 39 * page-aligned. It is the responsibility of the linker script to ensure that 40 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to 41 * page-aligned addresses. 42 */ 43 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__) 44 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__) 45 46 static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); 47 48 #if !LOAD_IMAGE_V2 49 50 /******************************************************************************* 51 * This structure represents the superset of information that is passed to 52 * BL31, e.g. while passing control to it from BL2, bl31_params 53 * and other platform specific params 54 ******************************************************************************/ 55 typedef struct bl2_to_bl31_params_mem { 56 bl31_params_t bl31_params; 57 image_info_t bl31_image_info; 58 image_info_t bl32_image_info; 59 image_info_t bl33_image_info; 60 entry_point_info_t bl33_ep_info; 61 entry_point_info_t bl32_ep_info; 62 entry_point_info_t bl31_ep_info; 63 } bl2_to_bl31_params_mem_t; 64 65 static bl2_to_bl31_params_mem_t bl31_params_mem; 66 67 meminfo_t *bl2_plat_sec_mem_layout(void) 68 { 69 return &bl2_tzram_layout; 70 } 71 72 void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) 73 { 74 scp_bl2_meminfo->total_base = SCP_BL2_BASE; 75 scp_bl2_meminfo->total_size = SCP_BL2_SIZE; 76 scp_bl2_meminfo->free_base = SCP_BL2_BASE; 77 scp_bl2_meminfo->free_size = SCP_BL2_SIZE; 78 } 79 #endif /* LOAD_IMAGE_V2 */ 80 81 /******************************************************************************* 82 * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. 83 * Return 0 on success, -1 otherwise. 84 ******************************************************************************/ 85 #if LOAD_IMAGE_V2 86 int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info) 87 #else 88 int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info) 89 #endif 90 { 91 /* Enable MCU SRAM */ 92 hisi_mcu_enable_sram(); 93 94 /* Load MCU binary into SRAM */ 95 hisi_mcu_load_image(scp_bl2_image_info->image_base, 96 scp_bl2_image_info->image_size); 97 /* Let MCU running */ 98 hisi_mcu_start_run(); 99 100 INFO("%s: MCU PC is at 0x%x\n", 101 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2)); 102 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is 0x%x\n", 103 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4)); 104 return 0; 105 } 106 107 /******************************************************************************* 108 * Gets SPSR for BL32 entry 109 ******************************************************************************/ 110 uint32_t hikey_get_spsr_for_bl32_entry(void) 111 { 112 /* 113 * The Secure Payload Dispatcher service is responsible for 114 * setting the SPSR prior to entry into the BL3-2 image. 115 */ 116 return 0; 117 } 118 119 /******************************************************************************* 120 * Gets SPSR for BL33 entry 121 ******************************************************************************/ 122 #ifndef AARCH32 123 uint32_t hikey_get_spsr_for_bl33_entry(void) 124 { 125 unsigned int mode; 126 uint32_t spsr; 127 128 /* Figure out what mode we enter the non-secure world in */ 129 mode = EL_IMPLEMENTED(2) ? MODE_EL2 : MODE_EL1; 130 131 /* 132 * TODO: Consider the possibility of specifying the SPSR in 133 * the FIP ToC and allowing the platform to have a say as 134 * well. 135 */ 136 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); 137 return spsr; 138 } 139 #else 140 uint32_t hikey_get_spsr_for_bl33_entry(void) 141 { 142 unsigned int hyp_status, mode, spsr; 143 144 hyp_status = GET_VIRT_EXT(read_id_pfr1()); 145 146 mode = (hyp_status) ? MODE32_hyp : MODE32_svc; 147 148 /* 149 * TODO: Consider the possibility of specifying the SPSR in 150 * the FIP ToC and allowing the platform to have a say as 151 * well. 152 */ 153 spsr = SPSR_MODE32(mode, plat_get_ns_image_entrypoint() & 0x1, 154 SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS); 155 return spsr; 156 } 157 #endif /* AARCH32 */ 158 159 #if LOAD_IMAGE_V2 160 int hikey_bl2_handle_post_image_load(unsigned int image_id) 161 { 162 int err = 0; 163 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 164 assert(bl_mem_params); 165 166 switch (image_id) { 167 #ifdef AARCH64 168 case BL32_IMAGE_ID: 169 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl32_entry(); 170 break; 171 #endif 172 173 case BL33_IMAGE_ID: 174 /* BL33 expects to receive the primary CPU MPID (through r0) */ 175 bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr(); 176 bl_mem_params->ep_info.spsr = hikey_get_spsr_for_bl33_entry(); 177 break; 178 179 #ifdef SCP_BL2_BASE 180 case SCP_BL2_IMAGE_ID: 181 /* The subsequent handling of SCP_BL2 is platform specific */ 182 err = plat_hikey_bl2_handle_scp_bl2(&bl_mem_params->image_info); 183 if (err) { 184 WARN("Failure in platform-specific handling of SCP_BL2 image.\n"); 185 } 186 break; 187 #endif 188 } 189 190 return err; 191 } 192 193 /******************************************************************************* 194 * This function can be used by the platforms to update/use image 195 * information for given `image_id`. 196 ******************************************************************************/ 197 int bl2_plat_handle_post_image_load(unsigned int image_id) 198 { 199 return hikey_bl2_handle_post_image_load(image_id); 200 } 201 202 #else /* LOAD_IMAGE_V2 */ 203 204 bl31_params_t *bl2_plat_get_bl31_params(void) 205 { 206 bl31_params_t *bl2_to_bl31_params = NULL; 207 208 /* 209 * Initialise the memory for all the arguments that needs to 210 * be passed to BL3-1 211 */ 212 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t)); 213 214 /* Assign memory for TF related information */ 215 bl2_to_bl31_params = &bl31_params_mem.bl31_params; 216 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0); 217 218 /* Fill BL3-1 related information */ 219 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info; 220 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY, 221 VERSION_1, 0); 222 223 /* Fill BL3-2 related information if it exists */ 224 #if BL32_BASE 225 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info; 226 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP, 227 VERSION_1, 0); 228 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info; 229 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY, 230 VERSION_1, 0); 231 #endif 232 233 /* Fill BL3-3 related information */ 234 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info; 235 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info, 236 PARAM_EP, VERSION_1, 0); 237 238 /* BL3-3 expects to receive the primary CPU MPID (through x0) */ 239 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr(); 240 241 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info; 242 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY, 243 VERSION_1, 0); 244 245 return bl2_to_bl31_params; 246 } 247 248 struct entry_point_info *bl2_plat_get_bl31_ep_info(void) 249 { 250 #if DEBUG 251 bl31_params_mem.bl31_ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL; 252 #endif 253 254 return &bl31_params_mem.bl31_ep_info; 255 } 256 257 void bl2_plat_set_bl31_ep_info(image_info_t *image, 258 entry_point_info_t *bl31_ep_info) 259 { 260 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); 261 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, 262 DISABLE_ALL_EXCEPTIONS); 263 } 264 265 /******************************************************************************* 266 * Before calling this function BL32 is loaded in memory and its entrypoint 267 * is set by load_image. This is a placeholder for the platform to change 268 * the entrypoint of BL32 and set SPSR and security state. 269 * On Hikey we only set the security state of the entrypoint 270 ******************************************************************************/ 271 #ifdef BL32_BASE 272 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, 273 entry_point_info_t *bl32_ep_info) 274 { 275 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); 276 /* 277 * The Secure Payload Dispatcher service is responsible for 278 * setting the SPSR prior to entry into the BL32 image. 279 */ 280 bl32_ep_info->spsr = 0; 281 } 282 283 /******************************************************************************* 284 * Populate the extents of memory available for loading BL32 285 ******************************************************************************/ 286 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) 287 { 288 /* 289 * Populate the extents of memory available for loading BL32. 290 */ 291 bl32_meminfo->total_base = BL32_BASE; 292 bl32_meminfo->free_base = BL32_BASE; 293 bl32_meminfo->total_size = 294 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 295 bl32_meminfo->free_size = 296 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE; 297 } 298 #endif /* BL32_BASE */ 299 300 void bl2_plat_set_bl33_ep_info(image_info_t *image, 301 entry_point_info_t *bl33_ep_info) 302 { 303 unsigned long el_status; 304 unsigned int mode; 305 306 /* Figure out what mode we enter the non-secure world in */ 307 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT; 308 el_status &= ID_AA64PFR0_ELX_MASK; 309 310 if (el_status) 311 mode = MODE_EL2; 312 else 313 mode = MODE_EL1; 314 315 /* 316 * TODO: Consider the possibility of specifying the SPSR in 317 * the FIP ToC and allowing the platform to have a say as 318 * well. 319 */ 320 bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX, 321 DISABLE_ALL_EXCEPTIONS); 322 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); 323 } 324 325 void bl2_plat_flush_bl31_params(void) 326 { 327 flush_dcache_range((unsigned long)&bl31_params_mem, 328 sizeof(bl2_to_bl31_params_mem_t)); 329 } 330 331 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) 332 { 333 bl33_meminfo->total_base = DDR_BASE; 334 bl33_meminfo->total_size = DDR_SIZE; 335 bl33_meminfo->free_base = DDR_BASE; 336 bl33_meminfo->free_size = DDR_SIZE; 337 } 338 #endif /* LOAD_IMAGE_V2 */ 339 340 static void reset_dwmmc_clk(void) 341 { 342 unsigned int data; 343 344 /* disable mmc0 bus clock */ 345 mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0); 346 do { 347 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 348 } while (data & PERI_CLK0_MMC0); 349 /* enable mmc0 bus clock */ 350 mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0); 351 do { 352 data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); 353 } while (!(data & PERI_CLK0_MMC0)); 354 /* reset mmc0 clock domain */ 355 mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0); 356 357 /* bypass mmc0 clock phase */ 358 data = mmio_read_32(PERI_SC_PERIPH_CTRL2); 359 data |= 3; 360 mmio_write_32(PERI_SC_PERIPH_CTRL2, data); 361 362 /* disable low power */ 363 data = mmio_read_32(PERI_SC_PERIPH_CTRL13); 364 data |= 1 << 3; 365 mmio_write_32(PERI_SC_PERIPH_CTRL13, data); 366 do { 367 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 368 } while (!(data & PERI_RST0_MMC0)); 369 370 /* unreset mmc0 clock domain */ 371 mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0); 372 do { 373 data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0); 374 } while (data & PERI_RST0_MMC0); 375 } 376 377 static void hikey_boardid_init(void) 378 { 379 u_register_t midr; 380 381 midr = read_midr(); 382 mmio_write_32(MEMORY_AXI_CHIP_ADDR, midr); 383 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, 384 (unsigned int)midr); 385 386 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0); 387 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b); 388 389 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234); 390 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678); 391 } 392 393 static void hikey_sd_init(void) 394 { 395 /* switch pinmux to SD */ 396 mmio_write_32(IOMG_SD_CLK, IOMG_MUX_FUNC0); 397 mmio_write_32(IOMG_SD_CMD, IOMG_MUX_FUNC0); 398 mmio_write_32(IOMG_SD_DATA0, IOMG_MUX_FUNC0); 399 mmio_write_32(IOMG_SD_DATA1, IOMG_MUX_FUNC0); 400 mmio_write_32(IOMG_SD_DATA2, IOMG_MUX_FUNC0); 401 mmio_write_32(IOMG_SD_DATA3, IOMG_MUX_FUNC0); 402 403 mmio_write_32(IOCG_SD_CLK, IOCG_INPUT_16MA); 404 mmio_write_32(IOCG_SD_CMD, IOCG_INPUT_12MA); 405 mmio_write_32(IOCG_SD_DATA0, IOCG_INPUT_12MA); 406 mmio_write_32(IOCG_SD_DATA1, IOCG_INPUT_12MA); 407 mmio_write_32(IOCG_SD_DATA2, IOCG_INPUT_12MA); 408 mmio_write_32(IOCG_SD_DATA3, IOCG_INPUT_12MA); 409 410 /* set SD Card detect as nopull */ 411 mmio_write_32(IOCG_GPIO8, 0); 412 } 413 414 static void hikey_jumper_init(void) 415 { 416 /* set jumper detect as nopull */ 417 mmio_write_32(IOCG_GPIO24, 0); 418 /* set jumper detect as GPIO */ 419 mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0); 420 } 421 422 void bl2_early_platform_setup(meminfo_t *mem_layout) 423 { 424 dw_mmc_params_t params; 425 426 /* Initialize the console to provide early debug support */ 427 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE); 428 429 /* Setup the BL2 memory layout */ 430 bl2_tzram_layout = *mem_layout; 431 432 /* Clear SRAM since it'll be used by MCU right now. */ 433 memset((void *)SRAM_BASE, 0, SRAM_SIZE); 434 435 sp804_timer_init(SP804_TIMER0_BASE, 10, 192); 436 dsb(); 437 hikey_ddr_init(); 438 439 hikey_boardid_init(); 440 init_acpu_dvfs(); 441 hikey_sd_init(); 442 hikey_jumper_init(); 443 444 reset_dwmmc_clk(); 445 memset(¶ms, 0, sizeof(dw_mmc_params_t)); 446 params.reg_base = DWMMC0_BASE; 447 params.desc_base = HIKEY_MMC_DESC_BASE; 448 params.desc_size = 1 << 20; 449 params.clk_rate = 24 * 1000 * 1000; 450 params.bus_width = EMMC_BUS_WIDTH_8; 451 params.flags = EMMC_FLAG_CMD23; 452 dw_mmc_init(¶ms); 453 454 hikey_io_setup(); 455 } 456 457 void bl2_plat_arch_setup(void) 458 { 459 hikey_init_mmu_el1(bl2_tzram_layout.total_base, 460 bl2_tzram_layout.total_size, 461 BL2_RO_BASE, 462 BL2_RO_LIMIT, 463 BL2_COHERENT_RAM_BASE, 464 BL2_COHERENT_RAM_LIMIT); 465 } 466 467 void bl2_platform_setup(void) 468 { 469 } 470