1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arm_config.h> 8 #include <arm_def.h> 9 #include <assert.h> 10 #include <cci.h> 11 #include <ccn.h> 12 #include <debug.h> 13 #include <gicv2.h> 14 #include <mmio.h> 15 #include <plat_arm.h> 16 #include <v2m_def.h> 17 #include "../fvp_def.h" 18 19 /* Defines for GIC Driver build time selection */ 20 #define FVP_GICV2 1 21 #define FVP_GICV3 2 22 #define FVP_GICV3_LEGACY 3 23 24 /******************************************************************************* 25 * arm_config holds the characteristics of the differences between the three FVP 26 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot 27 * at each boot stage by the primary before enabling the MMU (to allow 28 * interconnect configuration) & used thereafter. Each BL will have its own copy 29 * to allow independent operation. 30 ******************************************************************************/ 31 arm_config_t arm_config; 32 33 #define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \ 34 DEVICE0_SIZE, \ 35 MT_DEVICE | MT_RW | MT_SECURE) 36 37 #define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \ 38 DEVICE1_SIZE, \ 39 MT_DEVICE | MT_RW | MT_SECURE) 40 41 /* 42 * Need to be mapped with write permissions in order to set a new non-volatile 43 * counter value. 44 */ 45 #define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \ 46 DEVICE2_SIZE, \ 47 MT_DEVICE | MT_RW | MT_SECURE) 48 49 50 /* 51 * Table of memory regions for various BL stages to map using the MMU. 52 * This doesn't include Trusted SRAM as arm_setup_page_tables() already 53 * takes care of mapping it. 54 * 55 * The flash needs to be mapped as writable in order to erase the FIP's Table of 56 * Contents in case of unrecoverable error (see plat_error_handler()). 57 */ 58 #ifdef IMAGE_BL1 59 const mmap_region_t plat_arm_mmap[] = { 60 ARM_MAP_SHARED_RAM, 61 V2M_MAP_FLASH0_RW, 62 V2M_MAP_IOFPGA, 63 MAP_DEVICE0, 64 MAP_DEVICE1, 65 #if TRUSTED_BOARD_BOOT 66 /* To access the Root of Trust Public Key registers. */ 67 MAP_DEVICE2, 68 /* Map DRAM to authenticate NS_BL2U image. */ 69 ARM_MAP_NS_DRAM1, 70 #endif 71 {0} 72 }; 73 #endif 74 #ifdef IMAGE_BL2 75 const mmap_region_t plat_arm_mmap[] = { 76 ARM_MAP_SHARED_RAM, 77 V2M_MAP_FLASH0_RW, 78 V2M_MAP_IOFPGA, 79 MAP_DEVICE0, 80 MAP_DEVICE1, 81 ARM_MAP_NS_DRAM1, 82 #ifdef SPD_tspd 83 ARM_MAP_TSP_SEC_MEM, 84 #endif 85 #if TRUSTED_BOARD_BOOT 86 /* To access the Root of Trust Public Key registers. */ 87 MAP_DEVICE2, 88 #endif 89 #if ARM_BL31_IN_DRAM 90 ARM_MAP_BL31_SEC_DRAM, 91 #endif 92 #ifdef SPD_opteed 93 ARM_OPTEE_PAGEABLE_LOAD_MEM, 94 #endif 95 {0} 96 }; 97 #endif 98 #ifdef IMAGE_BL2U 99 const mmap_region_t plat_arm_mmap[] = { 100 MAP_DEVICE0, 101 V2M_MAP_IOFPGA, 102 {0} 103 }; 104 #endif 105 #ifdef IMAGE_BL31 106 const mmap_region_t plat_arm_mmap[] = { 107 ARM_MAP_SHARED_RAM, 108 V2M_MAP_IOFPGA, 109 MAP_DEVICE0, 110 MAP_DEVICE1, 111 {0} 112 }; 113 #endif 114 #ifdef IMAGE_BL32 115 const mmap_region_t plat_arm_mmap[] = { 116 #ifdef AARCH32 117 ARM_MAP_SHARED_RAM, 118 #endif 119 V2M_MAP_IOFPGA, 120 MAP_DEVICE0, 121 MAP_DEVICE1, 122 {0} 123 }; 124 #endif 125 126 ARM_CASSERT_MMAP 127 128 #if FVP_INTERCONNECT_DRIVER != FVP_CCN 129 static const int fvp_cci400_map[] = { 130 PLAT_FVP_CCI400_CLUS0_SL_PORT, 131 PLAT_FVP_CCI400_CLUS1_SL_PORT, 132 }; 133 134 static const int fvp_cci5xx_map[] = { 135 PLAT_FVP_CCI5XX_CLUS0_SL_PORT, 136 PLAT_FVP_CCI5XX_CLUS1_SL_PORT, 137 }; 138 139 static unsigned int get_interconnect_master(void) 140 { 141 unsigned int master; 142 u_register_t mpidr; 143 144 mpidr = read_mpidr_el1(); 145 master = (arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) ? 146 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr); 147 148 assert(master < FVP_CLUSTER_COUNT); 149 return master; 150 } 151 #endif 152 153 /******************************************************************************* 154 * A single boot loader stack is expected to work on both the Foundation FVP 155 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The 156 * SYS_ID register provides a mechanism for detecting the differences between 157 * these platforms. This information is stored in a per-BL array to allow the 158 * code to take the correct path.Per BL platform configuration. 159 ******************************************************************************/ 160 void fvp_config_setup(void) 161 { 162 unsigned int rev, hbi, bld, arch, sys_id; 163 164 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID); 165 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK; 166 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK; 167 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK; 168 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK; 169 170 if (arch != ARCH_MODEL) { 171 ERROR("This firmware is for FVP models\n"); 172 panic(); 173 } 174 175 /* 176 * The build field in the SYS_ID tells which variant of the GIC 177 * memory is implemented by the model. 178 */ 179 switch (bld) { 180 case BLD_GIC_VE_MMAP: 181 ERROR("Legacy Versatile Express memory map for GIC peripheral" 182 " is not supported\n"); 183 panic(); 184 break; 185 case BLD_GIC_A53A57_MMAP: 186 break; 187 default: 188 ERROR("Unsupported board build %x\n", bld); 189 panic(); 190 } 191 192 /* 193 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010 194 * for the Foundation FVP. 195 */ 196 switch (hbi) { 197 case HBI_FOUNDATION_FVP: 198 arm_config.flags = 0; 199 200 /* 201 * Check for supported revisions of Foundation FVP 202 * Allow future revisions to run but emit warning diagnostic 203 */ 204 switch (rev) { 205 case REV_FOUNDATION_FVP_V2_0: 206 case REV_FOUNDATION_FVP_V2_1: 207 case REV_FOUNDATION_FVP_v9_1: 208 case REV_FOUNDATION_FVP_v9_6: 209 break; 210 default: 211 WARN("Unrecognized Foundation FVP revision %x\n", rev); 212 break; 213 } 214 break; 215 case HBI_BASE_FVP: 216 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC); 217 218 /* 219 * Check for supported revisions 220 * Allow future revisions to run but emit warning diagnostic 221 */ 222 switch (rev) { 223 case REV_BASE_FVP_V0: 224 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400; 225 break; 226 case REV_BASE_FVP_REVC: 227 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 | 228 ARM_CONFIG_FVP_HAS_CCI5XX); 229 break; 230 default: 231 WARN("Unrecognized Base FVP revision %x\n", rev); 232 break; 233 } 234 break; 235 default: 236 ERROR("Unsupported board HBI number 0x%x\n", hbi); 237 panic(); 238 } 239 240 /* 241 * We assume that the presence of MT bit, and therefore shifted 242 * affinities, is uniform across the platform: either all CPUs, or no 243 * CPUs implement it. 244 */ 245 if (read_mpidr_el1() & MPIDR_MT_MASK) 246 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF; 247 } 248 249 250 void fvp_interconnect_init(void) 251 { 252 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 253 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) { 254 ERROR("Unrecognized CCN variant detected. Only CCN-502" 255 " is supported"); 256 panic(); 257 } 258 259 plat_arm_interconnect_init(); 260 #else 261 uintptr_t cci_base = 0; 262 const int *cci_map = 0; 263 unsigned int map_size = 0; 264 265 if (!(arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 266 ARM_CONFIG_FVP_HAS_CCI5XX))) { 267 return; 268 } 269 270 /* Initialize the right interconnect */ 271 if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) { 272 cci_base = PLAT_FVP_CCI5XX_BASE; 273 cci_map = fvp_cci5xx_map; 274 map_size = ARRAY_SIZE(fvp_cci5xx_map); 275 } else if (arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) { 276 cci_base = PLAT_FVP_CCI400_BASE; 277 cci_map = fvp_cci400_map; 278 map_size = ARRAY_SIZE(fvp_cci400_map); 279 } 280 281 assert(cci_base); 282 assert(cci_map); 283 cci_init(cci_base, cci_map, map_size); 284 #endif 285 } 286 287 void fvp_interconnect_enable(void) 288 { 289 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 290 plat_arm_interconnect_enter_coherency(); 291 #else 292 unsigned int master; 293 294 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 295 ARM_CONFIG_FVP_HAS_CCI5XX)) { 296 master = get_interconnect_master(); 297 cci_enable_snoop_dvm_reqs(master); 298 } 299 #endif 300 } 301 302 void fvp_interconnect_disable(void) 303 { 304 #if FVP_INTERCONNECT_DRIVER == FVP_CCN 305 plat_arm_interconnect_exit_coherency(); 306 #else 307 unsigned int master; 308 309 if (arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 | 310 ARM_CONFIG_FVP_HAS_CCI5XX)) { 311 master = get_interconnect_master(); 312 cci_disable_snoop_dvm_reqs(master); 313 } 314 #endif 315 } 316