Build: merge build macros between FIP_ and FWU_FIP_

The build system supports generating two FIP images, fip and fwu_fip.
Accordingly, we have similar build macros.

FIP_ADD_PAYLOAD <--> FWU_F

Build: merge build macros between FIP_ and FWU_FIP_

The build system supports generating two FIP images, fip and fwu_fip.
Accordingly, we have similar build macros.

FIP_ADD_PAYLOAD <--> FWU_FIP_ADD_PAYLOAD
CERT_ADD_CMD_OPT <--> FWU_CERT_ADD_CMD_OPT
FIP_ADD_IMG <--> FWU_FIP_ADD_IMG

The duplicated code increases the maintenance burden. Also, the build
rule of BL2U looks clumsy - we want to call MAKE_BL to compile it from
source files, but we want to put it in fwu_fip. We can not do it in a
single macro call since the current MAKE_BL does not support fwu_fip.

To refactor those in a clean way is to support one more argument to
specify the FIP prefix. If it is empty, the images are targeted to
fip, whereas if the argument is "FWU_", targeted to fwu_fip.

The build macros prefixed with FWU_ go away.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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Merge pull request #1240 from dp-arm/dp/smccc

Implement support for SMCCC v1.1 and optimize security mitigations for CVE-2017-5715 on AArch64

Merge pull request #1236 from dbasehore/gic-save-restore

RK3399 GIC save/restore

rockchip/rk3399: Fix memory corruptions or illegal memory access

Coverity scan done for the coreboot project found the issue:
Coverity (*** CID 1385418: Memory - illegal accesses (OVERRUN))
Coverity

rockchip/rk3399: Fix memory corruptions or illegal memory access

Coverity scan done for the coreboot project found the issue:
Coverity (*** CID 1385418: Memory - illegal accesses (OVERRUN))
Coverity (*** CID 1385419: Memory - corruptions (OVERRUN))

Fix the Converity error issue with store_cru[] loop needs to be one
element bigger.

Fixes: ARM-software/tf-issues#544

Change-Id: I420f0a660b24baaa5fc5e78fca242cf750c9bbc7
Signed-off-by: Caesar Wang <wxt@rock-chips.com>

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hikey: fix memory overlapped in memory map

MAP_TSP_MEM could be either in SRAM or DRAM. When MAP_TSP_MEM is in
DRAM, it's overlapped with MAP_DDR.

Since MAP_OPTEE_PAGEABLE isn't used in SRAM case,

hikey: fix memory overlapped in memory map

MAP_TSP_MEM could be either in SRAM or DRAM. When MAP_TSP_MEM is in
DRAM, it's overlapped with MAP_DDR.

Since MAP_OPTEE_PAGEABLE isn't used in SRAM case, just remove it.

Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>

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Merge pull request #1237 from sandrine-bailleux-arm/sb/spm-timer

SPM: Map devices in the 1st GB

Disable workaround for CVE-2017-5715 on unaffected platforms

Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>

SPM: Map devices in the 1st GB

This patch maps the devices in the first GB of the system address map
on the FVP into the S-EL1&0 translation regime when SPM support is
enabled. This grants the Secur

SPM: Map devices in the 1st GB

This patch maps the devices in the first GB of the system address map
on the FVP into the S-EL1&0 translation regime when SPM support is
enabled. This grants the Secure Partition access to the devices in
this region, for example the memory-mapped Generic Timer device.

Change-Id: I3aeea65f859ecbe83efde2acee20c55500c451bc
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>

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hikey: fix assert in sec_protect()

`assert(e)` was used in place of `if (e) ERROR()` when sec_protect()
was ported from hikey fork so the logic should have been reversed.

Fixes: 3d5d9f5a ("hikey: c

hikey: fix assert in sec_protect()

`assert(e)` was used in place of `if (e) ERROR()` when sec_protect()
was ported from hikey fork so the logic should have been reversed.

Fixes: 3d5d9f5a ("hikey: configure the top 16MB of DRAM as secure")
Fixes: 52988b38 ("hikey: configure 4 MB of secure DRAM for OP-TEE
Secure Data Path")
Signed-off-by: Victor Chong <victor.chong@linaro.org>
Tested-by: Victor Chong <victor.chong@linaro.org>

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Merge pull request #1205 from petegriffin/hikey-protect-memory

Hikey protect optee / sdp memory

rockchip: Disable rdist before pwr_dm_suspend is called

This disables the redistributor before either of the pwr_dm_suspend
functions are called. This is because the rdist save code in the
rk3399 ro

rockchip: Disable rdist before pwr_dm_suspend is called

This disables the redistributor before either of the pwr_dm_suspend
functions are called. This is because the rdist save code in the
rk3399 rockchip_soc_sys_pwr_dm_suspend function requires that each
redistributor be disabled before saving state.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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Merge pull request #1232 from masahir0y/uniphier

uniphier: migrate to BL2-AT-EL3

Merge pull request #1231 from Leo-Yan/hikey960_enable_fiq_handling

Hikey960: Enable invalid FIQ handling

Merge pull request #1223 from vchong/poplar_bl1loadsfip

poplar: Enable emmc and recovery build support

Merge pull request #1193 from jwerner-chromium/JW_coreboot

New console API and coreboot support [v4]

uniphier: switch to BL2-AT-EL3 and remove BL1 support

UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3
support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2
is

uniphier: switch to BL2-AT-EL3 and remove BL1 support

UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3
support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2
is entered at EL1-S. Now, this platform is able to avoid this waste.

Enable the BL2_AT_EL3 option, and remove BL1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailbox

The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS
is disabled.

The warm boot mailbox is useless for UniPhier

uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailbox

The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS
is disabled.

The warm boot mailbox is useless for UniPhier SoC family because BL1
is not the first image. The UniPhier platform implements non-TF ROM,
then BL1 works as a pseudo ROM, so it is never executed in the warm
boot.

The reset vector address is not actually programmable for UniPhier
platform, but it should not hurt to enable PROGRAMMABLE_RESET_ADDRESS
to disable the mailbox and remove pointless plat_get_my_entrypoint.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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hikey: configure 4 MB of secure DRAM for OP-TEE Secure Data Path

Update the memory firewall configuration to reserve 4 MB of secure RAM
for use by the kernel and OP-TEE as the Secure Data Path pool.

hikey: configure 4 MB of secure DRAM for OP-TEE Secure Data Path

Update the memory firewall configuration to reserve 4 MB of secure RAM
for use by the kernel and OP-TEE as the Secure Data Path pool.
Note that this address range (0x3E800000 - 0x3EC00000) falls in the
range already set aside by UEFI (which reserves the upper 32 MB of the
1GB DRAM for OP-TEE [1]) and was previously unused.

[1] https://github.com/96boards-hikey/edk2/blob/hikey/HisiPkg/HiKeyPkg/Library/HiKeyLib/HiKeyMem.c#L44
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>

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hikey: configure the top 16MB of DRAM as secure

DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE and should
therefore be accessible only from secure world.

Signed-off-by: Jerome Forissier

hikey: configure the top 16MB of DRAM as secure

DRAM region 0x3f000000 - 0x3fffffff is reserved for OP-TEE and should
therefore be accessible only from secure world.

Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Victor Chong <victor.chong@linaro.org>

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rockchip/rk3399: Save and restore GIC

This adds calls to the GICv3 save/restore functions for the GIC
distributor and redistributor.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

rockchip/rk3399: Add udelay to wait loops

We were looping for MAX_WAIT_COUNT in several places without any
delays, so this adds the delays to make those loops more predictable.

Signed-off-by: Derek

rockchip/rk3399: Add udelay to wait loops

We were looping for MAX_WAIT_COUNT in several places without any
delays, so this adds the delays to make those loops more predictable.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip/rk3399: Fix QOS save/restore

The code was accidentally restoring the QOS on suspend and saving the
QOS on resume. This is the opposite of what we want.

Signed-off-by: Derek Basehore <dbase

rockchip/rk3399: Fix QOS save/restore

The code was accidentally restoring the QOS on suspend and saving the
QOS on resume. This is the opposite of what we want.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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rockchip/rk3399: Change PD_CTR_LOOP to 10000

This brings ATF into line with the kernel on the timeout for power
domains turning on. We could actually timeout (when we shouldn't) on
resume when turni

rockchip/rk3399: Change PD_CTR_LOOP to 10000

This brings ATF into line with the kernel on the timeout for power
domains turning on. We could actually timeout (when we shouldn't) on
resume when turning power domains on. The guaranteed maximum delay is
now 10ms.

Signed-off-by: Derek Basehore <dbasehore@chromium.org>

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Allow API deprecation for uniphier platform

The `override ERROR_DEPRECATION = 1` setting in uniphier platform
makes deprecation of API difficult. Hence removing the same. This
flag should be specifi

Allow API deprecation for uniphier platform

The `override ERROR_DEPRECATION = 1` setting in uniphier platform
makes deprecation of API difficult. Hence removing the same. This
flag should be specified on the command line if needed.

Change-Id: I8c82d8d13944e450a8cd636de3326137c04d7560
Signed-off-by: Soby Mathew <soby.mathew@arm.com>

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poplar: Add support for recovery build

Signed-off-by: Victor Chong <victor.chong@linaro.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>