| a68346a7 | 22-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab
feat(plat/mdeiatek/mt8186): add power-off function for PSCI
Add support for system-off.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic734696aab1b71ae85bca6ed08e544a522ce5c95
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| 572f8adb | 25-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Ch
feat(plat/mediatek/mt8186): apply erratas for MT8186
MT8186 uses Cortex A76 CPU, so we apply these erratas.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84741535fbe429f664092f624c2da653532204cd
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| 06cb65ef | 14-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f
feat(plat/mediatek/mt8186): add MCDI drivers
Add MCDI related drivers to handle CPU powered on/off in CPU suspend.
TEST=build pass
BUG=b:202871018
Change-Id: I85aaaf3a0e992a39d17c58f3d9d5ff1b5770f748
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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| 1da57e54 | 08-Nov-2021 |
Garmin.Chang <Garmin.Chang@mediatek.com> |
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423
feat(plat/mediatek/mt8186): add CPU hotplug
Implement PSCI platform operations to support CPU hotplug and MCDI.
TEST=bringup 8 CPUs successfully on kernel stage.
BUG=b:202871018
Change-Id: Ibd5423b70b3ca3f91edaa48d7ca5bc094e751510
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
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| 6e5d76ba | 12-Nov-2021 |
Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.
TEST=build pass
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change
feat(plat/mediatek/mt8186): add RTC drivers
Add RTC drivers for EOSC calibration.
TEST=build pass
BUG=b:202871018
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ib48c07204c4a614072ba710c042794b59e8a902a
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| 0fe7ae9c | 09-Nov-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn
fix(plat/mediatek/mt8186): extend MMU region size
In mt8186 suspend/resume flow, ATF has to communicate with a subsys by
read/write the subsys registers. However, the register region of subsys
doesn't include in the MMU mapping region. It triggers MMU faults.
This patch extends the MMU region 0 size to cover all mt8186 HW modules.
This patch also remove MMU region 1 because region 0 covers region 1.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I520c51338578bd68756cd02603ce6783f93daf51
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| 95ea87ff | 01-Nov-2021 |
Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable M
feat(plat/mediatek/mt8186): add DCM driver
DCM means dynamic clock management, and it can dynamically
slow down or gate clocks during CPU or bus idle.
1. Add MCUSYS related DCM drivers.
2. Enable MCUSYS related DCM by default.
TEST=build pass
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: Idc669364c89cde0974d2940bd12987ee833d1965
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| af5a0c40 | 15-Oct-2021 |
Guodong Liu <guodong.liu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b
feat(plat/mediatek/mt8186): add pinctrl support
Add MT8186 pinctrl support.
TEST=build pass
BUG=b:202871018
Signed-off-by: Guodong Liu <guodong.liu@mediatek.corp-partner.google.com>
Change-Id: I5b9c1c60a91c74c7d3f45c78a9403544373fa90f
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| 109b91e3 | 12-Oct-2021 |
Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib
feat(plat/mediatek/mt8186): add sys_cirq support
Add 8186 sys_cirq info.
TEST=build pass
BUG=b:202871018
Signed-off-by: Zhengnan Chen <zhengnan.chen@mediatek.corp-partner.google.com>
Change-Id: Ib8a1c4e995288bf5f7981ea65f27727715fe5787
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| 206f125c | 11-Oct-2021 |
Christine Zhu <christine.zhu@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d02
feat(plat/mediatek/mt8186): initialize GIC
Initialize GIC for mt8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Christine Zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I8d029983c7ce48fa116fafa7fa78c65349308014
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| 5aab27dc | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde
feat(plat/mediatek/mt8186): add SiP service
Add the basic SiP service.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I4dcc7383237bb6c1f2494920cde21197754f6367
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| 5bc88ec6 | 06-Oct-2021 |
James Lo <james.lo@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: Jame
feat(plat/mediatek/mt8186): add pwrap and pmic driver
1. Add 8186 pwrap driver to access pmic.
2. Add 6366 pmic driver to support clean PWRHOLD.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I3bc90460a6a55dff8d3293e04482abcad789bbb2
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| d73e15e6 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f
feat(plat/mediatek/mt8186): initialize delay_timer
Initialize delay_timer for delay functions.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib8f52d1c674537795cc478015c83cca0f872df60
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| a6a0af57 | 06-Oct-2021 |
Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d0944
feat(plat/mediatek/mt8186): initialize systimer
Add systimer to support timer function.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I505f7d094410d178e4203e3a9294b851a30ba150
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| 1b17e34c | 03-Oct-2021 |
Penny Jan <penny.jan@mediatek.corp-partner.google.com> |
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and w
feat(plat/mediatek/mt8186): add EMI MPU basic driver
EMI MPU stands for external memory interface memory protect unit.
MT8186 supports 32 regions and 16 domains.
We add basic driver currently, and will add more settings for
EMI MPU in next patch.
TEST=build pass
BUG=b:202871018
Signed-off-by: Penny Jan <penny.jan@mediatek.corp-partner.google.com>
Change-Id: Ia9e5030164e40e060a05e8f91d2ac88258c2e98e
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| c2d75fa7 | 22-Dec-2021 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge "fix(errata): workaround for Cortex X2 erratum 2083908" into integration |
| f480c9c4 | 17-Dec-2021 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(stm32mp1): correct include order" into integration |
| ff7675eb | 17-Dec-2021 |
Yann Gautier <yann.gautier@st.com> |
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0e
fix(stm32mp1): correct include order
Warnings about header files include order were triggered by CI.
Correct the include order to mathc CI requirements.
Change-Id: Iaca959add924e0e1fa2e56fab2348f0ee36e5fa7
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| 1db6cd60 | 01-Dec-2021 |
johpow01 <john.powell@arm.com> |
fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found he
fix(errata): workaround for Cortex X2 erratum 2083908
Cortex X2 erratum 2083908 is a Cat B erratum present in the Cortex
X2 core. It applies to revision r2p0 and is still open.
SDEN can be found here:
https://developer.arm.com/documentation/SDEN1775100
Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: Id9dca2b042bf48e75fb3013ab37d1c5925824728
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| 07302a23 | 02-Dec-2021 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
fix(morello): change the AP runtime UART address
SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.
Sig
fix(morello): change the AP runtime UART address
SoC UART1 is internally connected to MCP UART1 so this
cannot be used as AP runtime UART instead we use the
IOFPGA UART0 as the AP runtime UART.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: Iecefb0d2cb875b3ecf97e0983b06f6e914835021
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| 6ad6465e | 18-Nov-2021 |
sah01 <sahil@arm.com> |
feat(morello): add support for nt_fw_config
This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.
Signed-off-by: sah0
feat(morello): add support for nt_fw_config
This patch adds support to load nt_fw_config
with the information from plat_info sds
structure which is then passed from BL2 to BL33.
Signed-off-by: sah01 <sahil@arm.com>
Change-Id: I2242da7404c72a4f9c2e3d7f3b5c154890a78526
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| 4a7a9daf | 02-Dec-2021 |
sah01 <sahil@arm.com> |
feat(morello): split platform_info sds struct
Different platform_info sds struct definition will be used
for fvp and soc.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfe
feat(morello): split platform_info sds struct
Different platform_info sds struct definition will be used
for fvp and soc.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: I92f0e1b2d0d755ad0405ceebfeb78d6e4c67013d
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| 4af53977 | 10-Jan-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): add changes to enable TBBR boot
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.
Signed-off-by: sahil <sahil@arm.com>
Change-Id
feat(morello): add changes to enable TBBR boot
This patch adds all SOC and FVP related changes required to boot
a standard TBBR style boot on Morello.
Signed-off-by: sahil <sahil@arm.com>
Change-Id: Ib8f7f326790b13082cbe8db21a980e048e3db88c
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| 572c8ce2 | 15-Sep-2021 |
Manoj Kumar <manoj.kumar3@arm.com> |
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-of
feat(morello): add DTS for Morello SoC platform
Added Morello SoC specific DTS file.
Change-Id: I099e74ec95ed9e1b47f7d5a68b0dd1e251439e11
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
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| 9b8c431e | 30-Nov-2021 |
Chandni Cherukuri <chandni.cherukuri@arm.com> |
feat(morello): configure DMC-Bing mode
Based on the SCC configuration value obtained from the SDS
platform information structure configure DMC-Bing Server or
Client mode after zeroing out the memory
feat(morello): configure DMC-Bing mode
Based on the SCC configuration value obtained from the SDS
platform information structure configure DMC-Bing Server or
Client mode after zeroing out the memory.
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Change-Id: I0555fa06c9c1906264848f4e32ca413b4742cdee
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