1 /* 2 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/debug.h> 10 #include <drivers/nand.h> 11 #include <drivers/raw_nand.h> 12 #include <drivers/spi_nand.h> 13 #include <drivers/spi_nor.h> 14 #include <lib/utils.h> 15 #include <plat/common/platform.h> 16 17 #define SZ_512 0x200U 18 #define SZ_64M 0x4000000U 19 20 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 21 static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) 22 { 23 uint32_t nand_param; 24 25 /* Check if NAND parameters are stored in OTP */ 26 if (stm32_get_otp_value(NAND_OTP, &nand_param) != 0) { 27 ERROR("BSEC: NAND_OTP Error\n"); 28 return -EACCES; 29 } 30 31 if (nand_param == 0U) { 32 return 0; 33 } 34 35 if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { 36 goto ecc; 37 } 38 39 /* NAND parameter shall be read from OTP */ 40 if ((nand_param & NAND_WIDTH_MASK) != 0U) { 41 nand_dev->buswidth = NAND_BUS_WIDTH_16; 42 } else { 43 nand_dev->buswidth = NAND_BUS_WIDTH_8; 44 } 45 46 switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { 47 case NAND_PAGE_SIZE_2K: 48 nand_dev->page_size = 0x800U; 49 break; 50 51 case NAND_PAGE_SIZE_4K: 52 nand_dev->page_size = 0x1000U; 53 break; 54 55 case NAND_PAGE_SIZE_8K: 56 nand_dev->page_size = 0x2000U; 57 break; 58 59 default: 60 ERROR("Cannot read NAND page size\n"); 61 return -EINVAL; 62 } 63 64 switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { 65 case NAND_BLOCK_SIZE_64_PAGES: 66 nand_dev->block_size = 64U * nand_dev->page_size; 67 break; 68 69 case NAND_BLOCK_SIZE_128_PAGES: 70 nand_dev->block_size = 128U * nand_dev->page_size; 71 break; 72 73 case NAND_BLOCK_SIZE_256_PAGES: 74 nand_dev->block_size = 256U * nand_dev->page_size; 75 break; 76 77 default: 78 ERROR("Cannot read NAND block size\n"); 79 return -EINVAL; 80 } 81 82 nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> 83 NAND_BLOCK_NB_SHIFT) * 84 NAND_BLOCK_NB_UNIT * nand_dev->block_size; 85 86 ecc: 87 if (is_slc) { 88 switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> 89 NAND_ECC_BIT_NB_SHIFT) { 90 case NAND_ECC_BIT_NB_1_BITS: 91 nand_dev->ecc.max_bit_corr = 1U; 92 break; 93 94 case NAND_ECC_BIT_NB_4_BITS: 95 nand_dev->ecc.max_bit_corr = 4U; 96 break; 97 98 case NAND_ECC_BIT_NB_8_BITS: 99 nand_dev->ecc.max_bit_corr = 8U; 100 break; 101 102 case NAND_ECC_ON_DIE: 103 nand_dev->ecc.mode = NAND_ECC_ONDIE; 104 break; 105 106 default: 107 if (nand_dev->ecc.max_bit_corr == 0U) { 108 ERROR("No valid eccbit number\n"); 109 return -EINVAL; 110 } 111 } 112 } else { 113 /* Selected multiple plane NAND */ 114 if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) { 115 nand_dev->nb_planes = 2U; 116 } else { 117 nand_dev->nb_planes = 1U; 118 } 119 } 120 121 VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size, 122 nand_dev->page_size, nand_dev->size); 123 124 return 0; 125 } 126 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ 127 128 #if STM32MP_RAW_NAND 129 int plat_get_raw_nand_data(struct rawnand_device *device) 130 { 131 device->nand_dev->ecc.mode = NAND_ECC_HW; 132 device->nand_dev->ecc.size = SZ_512; 133 134 return get_data_from_otp(device->nand_dev, true); 135 } 136 #endif 137 138 #if STM32MP_SPI_NAND 139 int plat_get_spi_nand_data(struct spinand_device *device) 140 { 141 zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op)); 142 device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X; 143 device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 144 device->spi_read_cache_op.addr.nbytes = 2U; 145 device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 146 device->spi_read_cache_op.dummy.nbytes = 1U; 147 device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 148 device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 149 device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN; 150 151 return get_data_from_otp(device->nand_dev, false); 152 } 153 #endif 154 155 #if STM32MP_SPI_NOR 156 int plat_get_nor_data(struct nor_device *device) 157 { 158 device->size = SZ_64M; 159 160 zeromem(&device->read_op, sizeof(struct spi_mem_op)); 161 device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4; 162 device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 163 device->read_op.addr.nbytes = 3U; 164 device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 165 device->read_op.dummy.nbytes = 1U; 166 device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 167 device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 168 device->read_op.data.dir = SPI_MEM_DATA_IN; 169 170 return 0; 171 } 172 #endif 173