1 /* 2 * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <errno.h> 9 #include <string.h> 10 11 #include <arch_helpers.h> 12 #include <common/bl_common.h> 13 #include <common/debug.h> 14 #include <common/desc_image_load.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <drivers/mmc.h> 17 #include <drivers/st/bsec.h> 18 #include <drivers/st/regulator_fixed.h> 19 #include <drivers/st/stm32_iwdg.h> 20 #include <drivers/st/stm32_uart.h> 21 #include <drivers/st/stm32mp1_clk.h> 22 #include <drivers/st/stm32mp1_pwr.h> 23 #include <drivers/st/stm32mp1_ram.h> 24 #include <drivers/st/stm32mp_pmic.h> 25 #include <lib/fconf/fconf.h> 26 #include <lib/fconf/fconf_dyn_cfg_getter.h> 27 #include <lib/mmio.h> 28 #include <lib/optee_utils.h> 29 #include <lib/xlat_tables/xlat_tables_v2.h> 30 #include <plat/common/platform.h> 31 32 #include <platform_def.h> 33 #include <stm32mp_common.h> 34 #include <stm32mp1_dbgmcu.h> 35 36 static struct stm32mp_auth_ops stm32mp1_auth_ops; 37 38 static void print_reset_reason(void) 39 { 40 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR); 41 42 if (rstsr == 0U) { 43 WARN("Reset reason unknown\n"); 44 return; 45 } 46 47 INFO("Reset reason (0x%x):\n", rstsr); 48 49 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) == 0U) { 50 if ((rstsr & RCC_MP_RSTSCLRR_STDBYRSTF) != 0U) { 51 INFO("System exits from STANDBY\n"); 52 return; 53 } 54 55 if ((rstsr & RCC_MP_RSTSCLRR_CSTDBYRSTF) != 0U) { 56 INFO("MPU exits from CSTANDBY\n"); 57 return; 58 } 59 } 60 61 if ((rstsr & RCC_MP_RSTSCLRR_PORRSTF) != 0U) { 62 INFO(" Power-on Reset (rst_por)\n"); 63 return; 64 } 65 66 if ((rstsr & RCC_MP_RSTSCLRR_BORRSTF) != 0U) { 67 INFO(" Brownout Reset (rst_bor)\n"); 68 return; 69 } 70 71 if ((rstsr & RCC_MP_RSTSCLRR_MCSYSRSTF) != 0U) { 72 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 73 INFO(" System reset generated by MCU (MCSYSRST)\n"); 74 } else { 75 INFO(" Local reset generated by MCU (MCSYSRST)\n"); 76 } 77 return; 78 } 79 80 if ((rstsr & RCC_MP_RSTSCLRR_MPSYSRSTF) != 0U) { 81 INFO(" System reset generated by MPU (MPSYSRST)\n"); 82 return; 83 } 84 85 if ((rstsr & RCC_MP_RSTSCLRR_HCSSRSTF) != 0U) { 86 INFO(" Reset due to a clock failure on HSE\n"); 87 return; 88 } 89 90 if ((rstsr & RCC_MP_RSTSCLRR_IWDG1RSTF) != 0U) { 91 INFO(" IWDG1 Reset (rst_iwdg1)\n"); 92 return; 93 } 94 95 if ((rstsr & RCC_MP_RSTSCLRR_IWDG2RSTF) != 0U) { 96 INFO(" IWDG2 Reset (rst_iwdg2)\n"); 97 return; 98 } 99 100 if ((rstsr & RCC_MP_RSTSCLRR_MPUP0RSTF) != 0U) { 101 INFO(" MPU Processor 0 Reset\n"); 102 return; 103 } 104 105 if ((rstsr & RCC_MP_RSTSCLRR_MPUP1RSTF) != 0U) { 106 INFO(" MPU Processor 1 Reset\n"); 107 return; 108 } 109 110 if ((rstsr & RCC_MP_RSTSCLRR_PADRSTF) != 0U) { 111 INFO(" Pad Reset from NRST\n"); 112 return; 113 } 114 115 if ((rstsr & RCC_MP_RSTSCLRR_VCORERSTF) != 0U) { 116 INFO(" Reset due to a failure of VDD_CORE\n"); 117 return; 118 } 119 120 ERROR(" Unidentified reset reason\n"); 121 } 122 123 void bl2_el3_early_platform_setup(u_register_t arg0, 124 u_register_t arg1 __unused, 125 u_register_t arg2 __unused, 126 u_register_t arg3 __unused) 127 { 128 stm32mp_save_boot_ctx_address(arg0); 129 } 130 131 void bl2_platform_setup(void) 132 { 133 int ret; 134 135 ret = stm32mp1_ddr_probe(); 136 if (ret < 0) { 137 ERROR("Invalid DDR init: error %d\n", ret); 138 panic(); 139 } 140 141 /* Map DDR for binary load, now with cacheable attribute */ 142 ret = mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE, 143 STM32MP_DDR_MAX_SIZE, MT_MEMORY | MT_RW | MT_SECURE); 144 if (ret < 0) { 145 ERROR("DDR mapping: error %d\n", ret); 146 panic(); 147 } 148 149 #if STM32MP_USE_STM32IMAGE 150 #ifdef AARCH32_SP_OPTEE 151 INFO("BL2 runs OP-TEE setup\n"); 152 #else 153 INFO("BL2 runs SP_MIN setup\n"); 154 #endif 155 #endif /* STM32MP_USE_STM32IMAGE */ 156 } 157 158 static void update_monotonic_counter(void) 159 { 160 uint32_t version; 161 uint32_t otp; 162 163 CASSERT(STM32_TF_VERSION <= MAX_MONOTONIC_VALUE, 164 assert_stm32mp1_monotonic_counter_reach_max); 165 166 /* Check if monotonic counter needs to be incremented */ 167 if (stm32_get_otp_index(MONOTONIC_OTP, &otp, NULL) != 0) { 168 panic(); 169 } 170 171 if (stm32_get_otp_value_from_idx(otp, &version) != 0) { 172 panic(); 173 } 174 175 if ((version + 1U) < BIT(STM32_TF_VERSION)) { 176 uint32_t result; 177 178 /* Need to increment the monotonic counter. */ 179 version = BIT(STM32_TF_VERSION) - 1U; 180 181 result = bsec_program_otp(version, otp); 182 if (result != BSEC_OK) { 183 ERROR("BSEC: MONOTONIC_OTP program Error %u\n", 184 result); 185 panic(); 186 } 187 INFO("Monotonic counter has been incremented (value 0x%x)\n", 188 version); 189 } 190 } 191 192 void bl2_el3_plat_arch_setup(void) 193 { 194 const char *board_model; 195 boot_api_context_t *boot_context = 196 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 197 uintptr_t pwr_base; 198 uintptr_t rcc_base; 199 200 if (bsec_probe() != 0U) { 201 panic(); 202 } 203 204 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 205 BL_CODE_END - BL_CODE_BASE, 206 MT_CODE | MT_SECURE); 207 208 #if STM32MP_USE_STM32IMAGE 209 #ifdef AARCH32_SP_OPTEE 210 mmap_add_region(STM32MP_OPTEE_BASE, STM32MP_OPTEE_BASE, 211 STM32MP_OPTEE_SIZE, 212 MT_MEMORY | MT_RW | MT_SECURE); 213 #else 214 /* Prevent corruption of preloaded BL32 */ 215 mmap_add_region(BL32_BASE, BL32_BASE, 216 BL32_LIMIT - BL32_BASE, 217 MT_RO_DATA | MT_SECURE); 218 #endif 219 #endif /* STM32MP_USE_STM32IMAGE */ 220 221 /* Prevent corruption of preloaded Device Tree */ 222 mmap_add_region(DTB_BASE, DTB_BASE, 223 DTB_LIMIT - DTB_BASE, 224 MT_RO_DATA | MT_SECURE); 225 226 configure_mmu(); 227 228 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 229 panic(); 230 } 231 232 pwr_base = stm32mp_pwr_base(); 233 rcc_base = stm32mp_rcc_base(); 234 235 /* 236 * Disable the backup domain write protection. 237 * The protection is enable at each reset by hardware 238 * and must be disabled by software. 239 */ 240 mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP); 241 242 while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) { 243 ; 244 } 245 246 /* Reset backup domain on cold boot cases */ 247 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) { 248 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 249 250 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 251 0U) { 252 ; 253 } 254 255 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 256 } 257 258 /* Disable MCKPROT */ 259 mmio_clrbits_32(rcc_base + RCC_TZCR, RCC_TZCR_MCKPROT); 260 261 /* 262 * Set minimum reset pulse duration to 31ms for discrete power 263 * supplied boards. 264 */ 265 if (dt_pmic_status() <= 0) { 266 mmio_clrsetbits_32(rcc_base + RCC_RDLSICR, 267 RCC_RDLSICR_MRD_MASK, 268 31U << RCC_RDLSICR_MRD_SHIFT); 269 } 270 271 generic_delay_timer_init(); 272 273 #if STM32MP_UART_PROGRAMMER 274 /* Disable programmer UART before changing clock tree */ 275 if (boot_context->boot_interface_selected == 276 BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART) { 277 uintptr_t uart_prog_addr = 278 get_uart_address(boot_context->boot_interface_instance); 279 280 stm32_uart_stop(uart_prog_addr); 281 } 282 #endif 283 if (stm32mp1_clk_probe() < 0) { 284 panic(); 285 } 286 287 if (stm32mp1_clk_init() < 0) { 288 panic(); 289 } 290 291 stm32_save_boot_interface(boot_context->boot_interface_selected, 292 boot_context->boot_interface_instance); 293 294 #if STM32MP_USB_PROGRAMMER 295 /* Deconfigure all UART RX pins configured by ROM code */ 296 stm32mp1_deconfigure_uart_pins(); 297 #endif 298 299 if (stm32mp_uart_console_setup() != 0) { 300 goto skip_console_init; 301 } 302 303 stm32mp_print_cpuinfo(); 304 305 board_model = dt_get_board_model(); 306 if (board_model != NULL) { 307 NOTICE("Model: %s\n", board_model); 308 } 309 310 stm32mp_print_boardinfo(); 311 312 if (boot_context->auth_status != BOOT_API_CTX_AUTH_NO) { 313 NOTICE("Bootrom authentication %s\n", 314 (boot_context->auth_status == BOOT_API_CTX_AUTH_FAILED) ? 315 "failed" : "succeeded"); 316 } 317 318 skip_console_init: 319 if (fixed_regulator_register() != 0) { 320 panic(); 321 } 322 323 if (dt_pmic_status() > 0) { 324 initialize_pmic(); 325 print_pmic_info_and_debug(); 326 } 327 328 stm32mp1_syscfg_init(); 329 330 if (stm32_iwdg_init() < 0) { 331 panic(); 332 } 333 334 stm32_iwdg_refresh(); 335 336 stm32mp1_auth_ops.check_key = boot_context->bootrom_ecdsa_check_key; 337 stm32mp1_auth_ops.verify_signature = 338 boot_context->bootrom_ecdsa_verify_signature; 339 340 stm32mp_init_auth(&stm32mp1_auth_ops); 341 342 stm32mp1_arch_security_setup(); 343 344 print_reset_reason(); 345 346 update_monotonic_counter(); 347 348 stm32mp1_syscfg_enable_io_compensation_finish(); 349 350 #if !STM32MP_USE_STM32IMAGE 351 fconf_populate("TB_FW", STM32MP_DTB_BASE); 352 #endif /* !STM32MP_USE_STM32IMAGE */ 353 354 stm32mp_io_setup(); 355 } 356 357 /******************************************************************************* 358 * This function can be used by the platforms to update/use image 359 * information for given `image_id`. 360 ******************************************************************************/ 361 int bl2_plat_handle_post_image_load(unsigned int image_id) 362 { 363 int err = 0; 364 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 365 bl_mem_params_node_t *bl32_mem_params; 366 bl_mem_params_node_t *pager_mem_params __unused; 367 bl_mem_params_node_t *paged_mem_params __unused; 368 #if !STM32MP_USE_STM32IMAGE 369 const struct dyn_cfg_dtb_info_t *config_info; 370 bl_mem_params_node_t *tos_fw_mem_params; 371 unsigned int i; 372 unsigned int idx; 373 unsigned long long ddr_top __unused; 374 const unsigned int image_ids[] = { 375 BL32_IMAGE_ID, 376 BL33_IMAGE_ID, 377 HW_CONFIG_ID, 378 TOS_FW_CONFIG_ID, 379 }; 380 #endif /* !STM32MP_USE_STM32IMAGE */ 381 382 assert(bl_mem_params != NULL); 383 384 switch (image_id) { 385 #if !STM32MP_USE_STM32IMAGE 386 case FW_CONFIG_ID: 387 /* Set global DTB info for fixed fw_config information */ 388 set_config_info(STM32MP_FW_CONFIG_BASE, STM32MP_FW_CONFIG_MAX_SIZE, FW_CONFIG_ID); 389 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 390 391 idx = dyn_cfg_dtb_info_get_index(TOS_FW_CONFIG_ID); 392 393 /* Iterate through all the fw config IDs */ 394 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 395 if ((image_ids[i] == TOS_FW_CONFIG_ID) && (idx == FCONF_INVALID_IDX)) { 396 continue; 397 } 398 399 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 400 assert(bl_mem_params != NULL); 401 402 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 403 if (config_info == NULL) { 404 continue; 405 } 406 407 bl_mem_params->image_info.image_base = config_info->config_addr; 408 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 409 410 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 411 412 switch (image_ids[i]) { 413 case BL32_IMAGE_ID: 414 bl_mem_params->ep_info.pc = config_info->config_addr; 415 416 /* In case of OPTEE, initialize address space with tos_fw addr */ 417 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 418 pager_mem_params->image_info.image_base = config_info->config_addr; 419 pager_mem_params->image_info.image_max_size = 420 config_info->config_max_size; 421 422 /* Init base and size for pager if exist */ 423 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 424 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 425 (dt_get_ddr_size() - STM32MP_DDR_S_SIZE - 426 STM32MP_DDR_SHMEM_SIZE); 427 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 428 break; 429 430 case BL33_IMAGE_ID: 431 bl_mem_params->ep_info.pc = config_info->config_addr; 432 break; 433 434 case HW_CONFIG_ID: 435 case TOS_FW_CONFIG_ID: 436 break; 437 438 default: 439 return -EINVAL; 440 } 441 } 442 break; 443 #endif /* !STM32MP_USE_STM32IMAGE */ 444 445 case BL32_IMAGE_ID: 446 if (optee_header_is_valid(bl_mem_params->image_info.image_base)) { 447 /* BL32 is OP-TEE header */ 448 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 449 pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID); 450 paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID); 451 assert((pager_mem_params != NULL) && (paged_mem_params != NULL)); 452 453 #if STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) 454 /* Set OP-TEE extra image load areas at run-time */ 455 pager_mem_params->image_info.image_base = STM32MP_OPTEE_BASE; 456 pager_mem_params->image_info.image_max_size = STM32MP_OPTEE_SIZE; 457 458 paged_mem_params->image_info.image_base = STM32MP_DDR_BASE + 459 dt_get_ddr_size() - 460 STM32MP_DDR_S_SIZE - 461 STM32MP_DDR_SHMEM_SIZE; 462 paged_mem_params->image_info.image_max_size = STM32MP_DDR_S_SIZE; 463 #endif /* STM32MP_USE_STM32IMAGE && defined(AARCH32_SP_OPTEE) */ 464 465 err = parse_optee_header(&bl_mem_params->ep_info, 466 &pager_mem_params->image_info, 467 &paged_mem_params->image_info); 468 if (err) { 469 ERROR("OPTEE header parse error.\n"); 470 panic(); 471 } 472 473 /* Set optee boot info from parsed header data */ 474 bl_mem_params->ep_info.args.arg0 = paged_mem_params->image_info.image_base; 475 bl_mem_params->ep_info.args.arg1 = 0; /* Unused */ 476 bl_mem_params->ep_info.args.arg2 = 0; /* No DT supported */ 477 } else { 478 #if !STM32MP_USE_STM32IMAGE 479 bl_mem_params->ep_info.pc = bl_mem_params->image_info.image_base; 480 tos_fw_mem_params = get_bl_mem_params_node(TOS_FW_CONFIG_ID); 481 bl_mem_params->image_info.image_max_size += 482 tos_fw_mem_params->image_info.image_max_size; 483 #endif /* !STM32MP_USE_STM32IMAGE */ 484 bl_mem_params->ep_info.args.arg0 = 0; 485 } 486 break; 487 488 case BL33_IMAGE_ID: 489 bl32_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID); 490 assert(bl32_mem_params != NULL); 491 bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc; 492 #if !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT 493 stm32mp1_fwu_set_boot_idx(); 494 #endif /* !STM32MP_USE_STM32IMAGE && PSA_FWU_SUPPORT */ 495 break; 496 497 default: 498 /* Do nothing in default case */ 499 break; 500 } 501 502 #if STM32MP_SDMMC || STM32MP_EMMC 503 /* 504 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 505 * We take the worst case which is 2 MMC blocks. 506 */ 507 if ((image_id != FW_CONFIG_ID) && 508 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 509 inv_dcache_range(bl_mem_params->image_info.image_base + 510 bl_mem_params->image_info.image_size, 511 2U * MMC_BLOCK_SIZE); 512 } 513 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 514 515 return err; 516 } 517 518 void bl2_el3_plat_prepare_exit(void) 519 { 520 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 521 522 switch (boot_itf) { 523 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 524 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 525 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 526 /* Invalidate the downloaded buffer used with io_memmap */ 527 inv_dcache_range(DWL_BUFFER_BASE, DWL_BUFFER_SIZE); 528 break; 529 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 530 default: 531 /* Do nothing in default case */ 532 break; 533 } 534 535 stm32mp1_security_setup(); 536 } 537