1 /* 2 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <errno.h> 8 9 #include <common/debug.h> 10 #include <drivers/nand.h> 11 #include <drivers/raw_nand.h> 12 #include <drivers/spi_nand.h> 13 #include <drivers/spi_nor.h> 14 #include <lib/utils.h> 15 #include <plat/common/platform.h> 16 17 #define SZ_512 0x200U 18 #define SZ_64M 0x4000000U 19 20 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 21 static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc) 22 { 23 int result; 24 uint32_t nand_param; 25 26 /* Check if NAND parameters are stored in OTP */ 27 result = bsec_shadow_read_otp(&nand_param, NAND_OTP); 28 if (result != BSEC_OK) { 29 ERROR("BSEC: NAND_OTP Error %i\n", result); 30 return -EACCES; 31 } 32 33 if (nand_param == 0U) { 34 return 0; 35 } 36 37 if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) { 38 goto ecc; 39 } 40 41 /* NAND parameter shall be read from OTP */ 42 if ((nand_param & NAND_WIDTH_MASK) != 0U) { 43 nand_dev->buswidth = NAND_BUS_WIDTH_16; 44 } else { 45 nand_dev->buswidth = NAND_BUS_WIDTH_8; 46 } 47 48 switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) { 49 case NAND_PAGE_SIZE_2K: 50 nand_dev->page_size = 0x800U; 51 break; 52 53 case NAND_PAGE_SIZE_4K: 54 nand_dev->page_size = 0x1000U; 55 break; 56 57 case NAND_PAGE_SIZE_8K: 58 nand_dev->page_size = 0x2000U; 59 break; 60 61 default: 62 ERROR("Cannot read NAND page size\n"); 63 return -EINVAL; 64 } 65 66 switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) { 67 case NAND_BLOCK_SIZE_64_PAGES: 68 nand_dev->block_size = 64U * nand_dev->page_size; 69 break; 70 71 case NAND_BLOCK_SIZE_128_PAGES: 72 nand_dev->block_size = 128U * nand_dev->page_size; 73 break; 74 75 case NAND_BLOCK_SIZE_256_PAGES: 76 nand_dev->block_size = 256U * nand_dev->page_size; 77 break; 78 79 default: 80 ERROR("Cannot read NAND block size\n"); 81 return -EINVAL; 82 } 83 84 nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >> 85 NAND_BLOCK_NB_SHIFT) * 86 NAND_BLOCK_NB_UNIT * nand_dev->block_size; 87 88 ecc: 89 if (is_slc) { 90 switch ((nand_param & NAND_ECC_BIT_NB_MASK) >> 91 NAND_ECC_BIT_NB_SHIFT) { 92 case NAND_ECC_BIT_NB_1_BITS: 93 nand_dev->ecc.max_bit_corr = 1U; 94 break; 95 96 case NAND_ECC_BIT_NB_4_BITS: 97 nand_dev->ecc.max_bit_corr = 4U; 98 break; 99 100 case NAND_ECC_BIT_NB_8_BITS: 101 nand_dev->ecc.max_bit_corr = 8U; 102 break; 103 104 case NAND_ECC_ON_DIE: 105 nand_dev->ecc.mode = NAND_ECC_ONDIE; 106 break; 107 108 default: 109 if (nand_dev->ecc.max_bit_corr == 0U) { 110 ERROR("No valid eccbit number\n"); 111 return -EINVAL; 112 } 113 } 114 } else { 115 /* Selected multiple plane NAND */ 116 if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) { 117 nand_dev->nb_planes = 2U; 118 } else { 119 nand_dev->nb_planes = 1U; 120 } 121 } 122 123 VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size, 124 nand_dev->page_size, nand_dev->size); 125 126 return 0; 127 } 128 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ 129 130 #if STM32MP_RAW_NAND 131 int plat_get_raw_nand_data(struct rawnand_device *device) 132 { 133 device->nand_dev->ecc.mode = NAND_ECC_HW; 134 device->nand_dev->ecc.size = SZ_512; 135 136 return get_data_from_otp(device->nand_dev, true); 137 } 138 #endif 139 140 #if STM32MP_SPI_NAND 141 int plat_get_spi_nand_data(struct spinand_device *device) 142 { 143 zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op)); 144 device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X; 145 device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 146 device->spi_read_cache_op.addr.nbytes = 2U; 147 device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 148 device->spi_read_cache_op.dummy.nbytes = 1U; 149 device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 150 device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 151 device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN; 152 153 return get_data_from_otp(device->nand_dev, false); 154 } 155 #endif 156 157 #if STM32MP_SPI_NOR 158 int plat_get_nor_data(struct nor_device *device) 159 { 160 device->size = SZ_64M; 161 162 zeromem(&device->read_op, sizeof(struct spi_mem_op)); 163 device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4; 164 device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 165 device->read_op.addr.nbytes = 3U; 166 device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 167 device->read_op.dummy.nbytes = 1U; 168 device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE; 169 device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE; 170 device->read_op.data.dir = SPI_MEM_DATA_IN; 171 172 return 0; 173 } 174 #endif 175