| c1baf178 | 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): common cpu features enablement
Enable SVE, SME, RNG, FGT in one place.
qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG
Signed-off-by: Marcin Juszkiewicz <ma
refactor(qemu): common cpu features enablement
Enable SVE, SME, RNG, FGT in one place.
qemu gains FGT (needed for 'max' cpu to boot Linux)
qemu_sbsa gains RNG
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I2e8f971ef3e42d9ebe9f20641b288cc8c40f806a
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| 18884750 | 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): common BL31 sources
Move BL31 source list into common file.
Change-Id: Iaa27cfd8f87b691728379c87a6ff6331e87951e1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
| 71f5359b | 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): common BL1/2 sources
Move BL1 and BL2 source list into common file.
Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro
refactor(qemu): common BL1/2 sources
Move BL1 and BL2 source list into common file.
Change-Id: I8f9a835f6cd1c5d67728a071860173f80f03c84e
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| 886688d1 | 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): move CPU definitions into one place
Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not
refactor(qemu): move CPU definitions into one place
Keep list of supported cpu cores in one place for both platforms.
qemu_sbsa does not handle some of them but with 256MB firmware space it
does not matter.
Change-Id: I5b8f7d18dc903e86e0cc7babbc2fb3f26a1bfdfa
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| a63cdc74 | 24-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
refactor(qemu): move FDT stuff into one place
Move libfdt includes into common file and use definitions from them.
Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkie
refactor(qemu): move FDT stuff into one place
Move libfdt includes into common file and use definitions from them.
Change-Id: Ic4fe784fdbedcf5e9e3804a633fcac68464f38a6
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
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| c7efb78f | 15-Aug-2023 |
Margarita Glushkin <rutigl@gmail.com> |
fix(nuvoton): fix typo in platform.mk
Fix typo of SPMD_SPM_AT_SEL2 in platform.mk
Signed-off-by: Margarita Glushkin <rutigl@gmail.com>
Change-Id: I06cfe2f1f0783edff513d83fef08eeed5f4fc58b |
| ca9d6edc | 26-Jun-2023 |
XiaoDong Huang <derrick.huang@rock-chips.com> |
fix(scmi): add parameter for plat_scmi_clock_rates_array
Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.
Signed-off-by: XiaoDong
fix(scmi): add parameter for plat_scmi_clock_rates_array
Pass "start_idx" to plat_scmi_clock_rates_array.
This parameter is required to obtain the rate table
a second time.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
Change-Id: I97c6751e7d34c839ced8f22bddc39fb534978cc4
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| b3d7e9c2 | 21-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "build(juno): added error check for BL32 dependency" into integration |
| c89d5912 | 21-Aug-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal-net): don't clear pending interrupts" into integration |
| 75574864 | 09-Aug-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
build(juno): added error check for BL32 dependency
Macro PLAT_ARM_MAX_BL32_SIZE definition is dependent on
JUNO_AARCH32_EL3_RUNTIME=1. When this value is not set and building
for AArch32, the build
build(juno): added error check for BL32 dependency
Macro PLAT_ARM_MAX_BL32_SIZE definition is dependent on
JUNO_AARCH32_EL3_RUNTIME=1. When this value is not set and building
for AArch32, the build fails as it cannot find the definition of the
first macro. With this patch, the problem is addressed by producing
an error when the dependency is not set properly.
Change-Id: Ibe4e976bf79892fd26f3b266bd546218f5616825
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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| fb73ea6c | 15-Aug-2023 |
Saeed Nowshadi <saeed.nowshadi@amd.com> |
fix(versal-net): don't clear pending interrupts
All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.
Signed-of
fix(versal-net): don't clear pending interrupts
All pending interrupts should be handled by their interrupt handlers. CPU
cores remain in suspend state if pending interrupts are cleared.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@amd.com>
Change-Id: Id8ddf36cbcc07484f232c477277c4da106985c8f
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| abc79c27 | 16-Aug-2023 |
Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com> |
fix(zynqmp): validate clock_id to avoid OOB variable access
The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
ac
fix(zynqmp): validate clock_id to avoid OOB variable access
The input argument clock_id in pm_api_clock_get_name function is not
validated against the maximum allowed number. This can lead to OOB
access for ext_clocks variable.
Add check in the pm_api_clock_get_name() to validate clock_id against
CLK_MAX.
Signed-off-by: Naman Trivedi Manojbhai <naman.trivedimanojbhai@amd.com>
Change-Id: Ifa0033d2c557efd6a87b40e366560bc3ba8c602b
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| abc2919c | 14-Aug-2023 |
Lauren Wehrmeister <lauren.wehrmeister@arm.com> |
Merge "feat(cpus): add support for Gelas CPU" into integration |
| 4ede8c39 | 14-Aug-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "el3_direct_msg" into integration
* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition
Merge changes from topic "el3_direct_msg" into integration
* changes:
docs(spm): document new build option
feat(fvp): spmd logical partition smc handler
feat(fvp): add spmd logical partition
feat(spmd): get logical partitions info
feat(spmd): add partition info get regs
refactor(ff-a): move structure definitions
feat(spmd): el3 direct message API
feat(spmd): add spmd logical partitions
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| 34d9d619 | 01-Aug-2023 |
Dawei Chien <dawei.chien@mediatek.corp-partner.google.com> |
feat(mt8188): add support for SMC from OP-TEE
- Add MTK_SIP_SMC_FROM_S_EL1_TABLE to handle the SMC call from OP-TEE.
- Register optee for EMI MPU.
Change-Id: Ie94542f0e3966c4c25f2b7233b9355d41f8f36
feat(mt8188): add support for SMC from OP-TEE
- Add MTK_SIP_SMC_FROM_S_EL1_TABLE to handle the SMC call from OP-TEE.
- Register optee for EMI MPU.
Change-Id: Ie94542f0e3966c4c25f2b7233b9355d41f8f36a5
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
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| a1a9a950 | 09-Apr-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(fvp): spmd logical partition smc handler
This patch adds a basic el3 spmd logical partition to the fvp platform
via a platform specific smc handler. One of the use cases for el3
logical partiti
feat(fvp): spmd logical partition smc handler
This patch adds a basic el3 spmd logical partition to the fvp platform
via a platform specific smc handler. One of the use cases for el3
logical partitions is to have the ability to translate sip calls into
ff-a direct requests via the use of spmd logical partitions. The smc
handler creates a direct request based on the incoming smc parameters
and forwards the call as a direct request from the spmd logical
partition to the target secure partition.
Change-Id: If8ba9aab8203924bd00fc1dcdf9cd05a9a04a147
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| 5cf311f3 | 04-Mar-2023 |
Raghu Krishnamurthy <raghu.ncstate@gmail.com> |
feat(fvp): add spmd logical partition
This patch changes spmd.mk to include one or more SPMD logical
partitions specific to a platform. It also adds a basic SPMD logical
partition to fvp.
Change-Id
feat(fvp): add spmd logical partition
This patch changes spmd.mk to include one or more SPMD logical
partitions specific to a platform. It also adds a basic SPMD logical
partition to fvp.
Change-Id: I2075e0458c92813913b28cbf4cfffc1f151e65cf
Signed-off-by: Raghu Krishnamurthy <raghu.ncstate@gmail.com>
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| 02586e0e | 05-Jul-2023 |
Juan Pablo Conde <juanpablo.conde@arm.com> |
feat(cpus): add support for Gelas CPU
This patch adds the necessary CPU library code to support the Gelas CPU
Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <j
feat(cpus): add support for Gelas CPU
This patch adds the necessary CPU library code to support the Gelas CPU
Change-Id: I13ec4a8bb7055c1ebd0796a4a1378983d930fcb3
Signed-off-by: Juan Pablo Conde <juanpablo.conde@arm.com>
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| 705832b3 | 11-Aug-2023 |
Bipin Ravi <bipin.ravi@arm.com> |
Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration
* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_
Merge changes I2f4961fe,I0039c724,Iaa3076c1,Ic19973a8 into integration
* changes:
feat(bl32): print entry point before exiting SP_MIN
fix(bl32): avoid clearing argument registers in RESET_TO_SP_MIN case
fix(bl32): always include arm_arch_svc in SP_MIN
fix(services): disable workaround discovery on aarch32 for now
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| 38d1679d | 10-Aug-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_security_flag_change" into integration
* changes:
fix(versal-net): make pmc ipi channel as secure
fix(versal): make pmc ipi channel as secure
fix(versal-net): ad
Merge changes from topic "xlnx_security_flag_change" into integration
* changes:
fix(versal-net): make pmc ipi channel as secure
fix(versal): make pmc ipi channel as secure
fix(versal-net): add redundant call to avoid glitches
fix(versal-net): change flag to increase security
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| 72e8f245 | 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "chore: update to use Arm word across TF-A" into integration |
| 4c700c15 | 01-Aug-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.co
chore: update to use Arm word across TF-A
Align entire TF-A to use Arm in copyright header.
Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
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| c399679c | 08-Aug-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "feat(stm32mp1): add FWU with boot from NOR-SPI" into integration |
| 2c65b79e | 31-Jul-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal-net): make pmc ipi channel as secure
Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <ja
fix(versal-net): make pmc ipi channel as secure
Make PMC IPI channel for Versal NET as secure so that NS
systems cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I75ba8796859dcb35644f3e144d7dc5926755ef78
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| 96eaafa3 | 31-Jul-2023 |
Jay Buddhabhatti <jay.buddhabhatti@amd.com> |
fix(versal): make pmc ipi channel as secure
Make PMC IPI channel for Versal as secure so that NS systems
cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddha
fix(versal): make pmc ipi channel as secure
Make PMC IPI channel for Versal as secure so that NS systems
cannot directly access or modify secure systems.
Signed-off-by: Jay Buddhabhatti <jay.buddhabhatti@amd.com>
Change-Id: I22148653fa2d27941cb3031ac790892cee0d1796
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