| 56d1857e | 10-Jul-2023 |
Amit Nagal <amit.nagal@amd.com> |
feat(versal): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build tim
feat(versal): ddr address reservation in dtb at runtime
When the TF-A is placed in DDR memory range, the DDR memory range
needs to be explicitly reserved in the default device tree.
A new build time parameter, XILINX_OF_BOARD_DTB_ADDR, is introduced.
The TF-A will reserve the DDR memory only when a valid DTB address
is provided to XILINX_OF_BOARD_DTB_ADDR during build.
Now the user has options, either manually reserve the desired DDR
address range for TF-A in device tree or let TF-A access and modify
the device tree, to reserve the DDR address range, in runtime using
the build parameter.
Change-Id: I4442a90e1cab5a3a115f4eeb8a7e09e247189ff0
Signed-off-by: Amit Nagal <amit.nagal@amd.com>
Signed-off-by: Akshay Belsare <akshay.belsare@amd.com>
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| cd1838cc | 11-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(intel): resolved coverity checking" into integration |
| 21fcd9f4 | 10-Jul-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge changes from topic "psci-osi" into integration
* changes:
fix(sc7280): update system suspend in OS-initiated mode
fix(fvp): update system suspend in OS-initiated mode |
| 0a9270ab | 28-Jun-2023 |
Wing Li <wingers@google.com> |
fix(sc7280): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_
fix(sc7280): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ib9ff606b7eebd8a8224891a0d239a4e13311fe2a
Signed-off-by: Wing Li <wingers@google.com>
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| e0ef05bb | 28-Jun-2023 |
Wing Li <wingers@google.com> |
fix(fvp): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR
fix(fvp): update system suspend in OS-initiated mode
This patch fixes system suspend in OS-initiated mode by setting the
value of `last_at_pwrlvl` in the `psci_power_state_t` object to
`PLAT_MAX_PWR_LVL`, which otherwise would result in undefined behavior.
This is conditionally compiled into the build depending on the value of
the `PSCI_OS_INIT_MODE` build option.
Change-Id: Ia0fb1e68af9320370325642b17c4569e9580aa3a
Signed-off-by: Wing Li <wingers@google.com>
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| 1af7bf71 | 07-Jul-2023 |
Sieu Mun Tang <sieu.mun.tang@intel.com> |
fix(intel): resolved coverity checking
Coverity checking fix. Resolved unused value, deadcode and uninit.
1. CID: 395326
2. CID: 395327
3. CID: 395328
4. CID: 395329
5. CID: 395330
Signed-off
fix(intel): resolved coverity checking
Coverity checking fix. Resolved unused value, deadcode and uninit.
1. CID: 395326
2. CID: 395327
3. CID: 395328
4. CID: 395329
5. CID: 395330
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
Change-Id: I86b8af28dc345542b142ce53e1935bb855888238
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| 1eb5e903 | 10-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "fix(rcar): add mandatory fields in 'reserved-memory' node" into integration |
| bd596a10 | 06-Jul-2023 |
Govindraj Raja <govindraj.raja@arm.com> |
build(fpga): remove a710 from fpga build
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framewor
build(fpga): remove a710 from fpga build
Currently we have a large series of errata_refactor patches pending
and they are all failing on arm_fpga build when we add errata_framework.
Errata framework can cause the size to grow and thus causing build
failure on bl31 size. This as of today is blocking us from
merging most of our changes as it will introduce a CI failure.
As an workaround we try to just reduce the arm_fpga build by a710
platform, we have a715 and a720 which should be ok I think.
Once everyone are available for further discussion we could revert this
change back and discuss further whats the right approach.
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
Change-Id: I96a821e10aaecf04db7407fb2df38012839bfb94
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| 3393060c | 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for A
Merge changes from topic "agilex5" into integration
* changes:
feat(intel): platform enablement for Agilex5 SoC FPGA
feat(intel): ccu driver for Agilex5 SoC FPGA
feat(intel): vab support for Agilex5 SoC FPGA
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
feat(intel): ddr driver for Agilex5 SoC FPGA
feat(intel): power manager for Agilex5 SoC FPGA
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
feat(intel): reset manager support for Agilex5 SoC FPGA
feat(intel): mailbox and SMC support for Agilex5 SoC FPGA
feat(intel): system manager support for Agilex5 SoC FPGA
feat(intel): memory controller support for Agilex5 SoC FPGA
feat(intel): clock manager support for Agilex5 SoC FPGA
feat(intel): mmc support for Agilex5 SoC FPGA
feat(intel): uart support for Agilex5 SoC FPGA
feat(intel): pinmux, peripheral and Handoff support for Agilex5 SoC FPGA
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| 0e74b661 | 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "imx93_basic_support" into integration
* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only
Merge changes from topic "imx93_basic_support" into integration
* changes:
docs(imx9): add imx93 platform
feat(imx93): add OPTEE support
feat(imx93): protect OPTEE memory to secure access only
feat(imx93): add cpuidle and basic suspend support
feat(imx93): add reset & poweroff support
feat(imx93): allow SoC masters access to system TCM
feat(imx93): update the ocram trdc config for did10
feat(imx93): add the basic support
feat(imx93): add the trdc driver
build(changelog): add new scopes for nxp imx platform
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| 74599321 | 06-Jul-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "feat(qemu): add "neoverse-v1" cpu support" into integration |
| da36a232 | 06-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge changes from topic "mb/mb-rss-refactor" into integration
* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS
Merge changes from topic "mb/mb-rss-refactor" into integration
* changes:
refactor(tc): update RSS driver inteface calls
refactor(fvp): update RSS driver inteface calls
refactor(rss): make RSS driver standalone for Measured Boot
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| 1fc20d7f | 30-Jun-2023 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(tc): rename macro to match PSA spec
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I583
fix(tc): rename macro to match PSA spec
Update 'PSA_INITIAL_ATTEST_TOKEN_MAX_SIZE' to
'PSA_INITIAL_ATTEST_MAX_TOKEN_SIZE' which is defined
in the PSA Certified Attestation API spec.
Change-Id: I5837fea552e6fe18a203412eb90d41e2f90ad6f1
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
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| b0542b58 | 04-Jul-2023 |
Jimmy Brisson <jimmy.brisson@arm.com> |
fix(tc): Correct return type
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-te
fix(tc): Correct return type
The fact that this was void instead of int, as required, caused
the test-running code to assume that the tests always failed.
Fixing the return type fixes the always-tests-failing bug.
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>
Change-Id: Ief55fe15c437c87dac1d03419a8e148f5d864b8d
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| 3c283af5 | 05-Jul-2023 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(n1sdp): configure platform specific secure SPIs" into integration |
| 6d8d7d23 | 05-Jul-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
feat(qemu): add "neoverse-v1" cpu support
Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b5
feat(qemu): add "neoverse-v1" cpu support
Add support to qemu "neoverse-v1" cpu for "qemu" ('virt') platform.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Change-Id: I4821115b54ca596fe27cb9d74a95429cd3cb21d9
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| 30b44fa5 | 05-Jul-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "feat(qemu): add "neoverse-v1" cpu support" into integration |
| 7931d332 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): platform enablement for Agilex5 SoC FPGA
This patch is used to enable platform enablement for
Agilex5 SoC FPGA.
New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
feat(intel): platform enablement for Agilex5 SoC FPGA
This patch is used to enable platform enablement for
Agilex5 SoC FPGA.
New feature:
1. Added ATF->Zephyr boot option
2. Added xlat_v2 for MMU
3. Added ATF->Linux boot option
4. Added SMP support
5. Added HPS bridges support
6. Added EMULATOR support
7. Added DDR support
8. Added GICv3 Redistirbution init
9. Added SDMMC/NAND/Combo Phy support
10. Updated GIC as secure access
11. Added CCU driver support
12. Updated product name -> Agilex5
13. Updated register address based on y22ww52.2 RTL
14. Updated system counter freq to 400MHz
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ice82f3e4535527cfd01500d4d528402985f72009
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| 02df4990 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): ccu driver for Agilex5 SoC FPGA
This patch is used to implement CCU driver for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c
feat(intel): ccu driver for Agilex5 SoC FPGA
This patch is used to implement CCU driver for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ic5e38499c969486682761c00d9e050e60c883725
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| 47549250 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): vab support for Agilex5 SoC FPGA
This patch is used to implement VAB to support for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35
feat(intel): vab support for Agilex5 SoC FPGA
This patch is used to implement VAB to support for
Agilex5 SoC FPGA.
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I421f11225cd549f35f06e87b8ad2c44b716b2a78
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| ddaf02d1 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-
feat(intel): sdmmc/nand/combo-phy/qspi driver for Agilex5 SoC FPGA
This patch is used to implement sdmmc/nand/combo-phy
driver to support Cadence IP for Agilex5 SoC FPGA.
1. Added SDMMC/NAND/COMBO-PHY support.
2. Updated product name -> Agilex5
3. Updated QSPI base address
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I6db689d2b784c9f59a25701ab34517f6f6b0a0e6
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| 29461e4c | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): ddr driver for Agilex5 SoC FPGA
This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5
Signed-off-
feat(intel): ddr driver for Agilex5 SoC FPGA
This patch is used to implement ddr driver to
support IO96b for Agilex5 SoC FPGA.
1. Added DDR support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Ibda053de6dbec4a0f12f011d8feeb6c5890fc7a4
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| a8bf898f | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): power manager for Agilex5 SoC FPGA
This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5
feat(intel): power manager for Agilex5 SoC FPGA
This patch is used to implement power manager data
support for Agilex5 SoC FPGA.
1. Added power manager support.
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: If0630c5088a1bc63dff64b1aab225fc70effa6e3
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| 79626f46 | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5
Signe
feat(intel): cold/warm reset and smp support for Agilex5 SoC FPGA
This patch is used to implement
1. Cold/Warm reset and SMP support for
Agilex5 SoC FPGA
2. Updated product name -> Agilex5
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: I2c0645bcbf3a5907a4c79f35cffe674920b48f9d
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| 9b8d813c | 17-May-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
feat(intel): reset manager support for Agilex5 SoC FPGA
This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SD
feat(intel): reset manager support for Agilex5 SoC FPGA
This patch is used to enable reset manager support
for Agilex5 SoC FPGA.
1. Added HPS bridges support
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC
2. Added EMULATOR support
3. Added WDT support
4. Updated product name -> Agilex5
5. Added SMP support
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
Change-Id: Icab15b25f787fdccce1de75d102604db23beaf11
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