feat(ti): add TI clock multiplexer driver

Add clock multiplexer driver for selecting between multiple clock
sources.

Change-Id: I10a90875a96870b4db584a3c3bc3f46e27f1d6df
Signed-off-by: Kamlesh Guru

feat(ti): add TI clock multiplexer driver

Add clock multiplexer driver for selecting between multiple clock
sources.

Change-Id: I10a90875a96870b4db584a3c3bc3f46e27f1d6df
Signed-off-by: Kamlesh Gurudasani <kamlesh@ti.com>

show more ...

feat(qti): reorganize bear-based SoCs under a common family directory

Group the bear SoC platforms (mdm9607, msm8909, msm8916, msm8939)
under a new plat/qti/bear/ directory to better classify and or

feat(qti): reorganize bear-based SoCs under a common family directory

Group the bear SoC platforms (mdm9607, msm8909, msm8916, msm8939)
under a new plat/qti/bear/ directory to better classify and organize
the platform code by SoC family.

The following SoC platforms are grouped under plat/qti/bear/:

mdm9607: Qualcomm MDM9607 SoC
msm8909: Qualcomm MSM8909 SoC
msm8916: Qualcomm MSM8916 SoC (Cortex-A7/A53, GICv2)
msm8939: Qualcomm MSM8939 SoC

Change-Id: I337f6e0c64a91c79405fd2df234531c7733b83f2
Signed-off-by: dongnanw <dongnanw@qti.qualcomm.com>

show more ...

feat(mediatek): support write-access for DSU PMU in EL1

Access to the PMU scheme management and thread scheme system registers
from S-EL1/NS-EL1 is controlled by ACTLR_EL3 and ACTLR_EL2. If the
corr

feat(mediatek): support write-access for DSU PMU in EL1

Access to the PMU scheme management and thread scheme system registers
from S-EL1/NS-EL1 is controlled by ACTLR_EL3 and ACTLR_EL2. If the
correstonding enables are not set, EL1 write may trap to EL3. To allow
kernel write these registers, it is necessary to enable
write-accessibility.

Change-Id: Ic957193da2542f714341274efba8d2e1903a4f04
Signed-off-by: Runyang Chen <runyang.chen@mediatek.com>

show more ...

fix(juno): increase BL2 maximum size to 0x16000

Following the recent upgrade to GCC v5.12, several Juno build is
failing in coverity, so increase the BL2 size limit to 0x16000.

Change-Id: I8fc3c127

fix(juno): increase BL2 maximum size to 0x16000

Following the recent upgrade to GCC v5.12, several Juno build is
failing in coverity, so increase the BL2 size limit to 0x16000.

Change-Id: I8fc3c12714eb07ef4b5bbf2f87ff77350c853119
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

feat(qti): reorganize hoya-based SoCs under a common family directory

Group the hoya-based SoC platforms (sc7180, kodiak, lemans, qcs615)
under a new plat/qti/hoya/ directory to better classify and

feat(qti): reorganize hoya-based SoCs under a common family directory

Group the hoya-based SoC platforms (sc7180, kodiak, lemans, qcs615)
under a new plat/qti/hoya/ directory to better classify and organize
the platform code by SoC family.

The following platforms are moved under plat/qti/hoya/:
- sc7180: Qualcomm SC7180 SoC
- kodiak: Qualcomm SC7280-based SoC, supporting rb3gen2 and sc7280_chrome
board configurations
- lemans: Qualcomm Lemans SoC, supporting lemans_evk board configuration
- qcs615: Qualcomm QCS615 SoC

The shared qtiseclib (security library interface) for these SoCs is also
relocated to plat/qti/hoya/qtiseclib/, as it is specific to the
hoya-based SoC family.

Change-Id: I9592d86e4a5ad02350cbcb3f178983bfe31e242d
Signed-off-by: dongnanw <dongnanw@qti.qualcomm.com>

show more ...

fix(rcar4): change the migrate information for OPTEE-OS

This commit fixes the migration information to fit the OPTEE-OS on
R-Car Gen4. The OPTEE-OS port is always running on the boot core and
is not

fix(rcar4): change the migrate information for OPTEE-OS

This commit fixes the migration information to fit the OPTEE-OS on
R-Car Gen4. The OPTEE-OS port is always running on the boot core and
is not MP capable. Instead of patching the opteed SPD code, duplicate
the spd_pm_ops_t opteed_pm into local spd_pm_ops_t rcar_opteed_pm and
rewrite its .svc_migrate_info with rcar_svc_migrate_info already used
by R-Car Gen4. This now covers both SPD=none and SPD=opteed use cases.

Signed-off-by: Hideyuki Nitta <hideyuki.nitta.jf@hitachi.com>
Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com>
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I0a5116ca7f6663bf7f46a87ad0a97a7adce4f3e8

show more ...

feat: enable FEATURE_DETECTION on FVP

FEATURE_DETECTION has received a lot of attention since its introduction
and at this point is quite reliable. Its experimental designation is no
longer appropri

feat: enable FEATURE_DETECTION on FVP

FEATURE_DETECTION has received a lot of attention since its introduction
and at this point is quite reliable. Its experimental designation is no
longer appropriate and it would be quite reasonable to use this feature
by default.

Always enable the feature for FVP so that we can have confidence that
the SW view of HW is up to date.

This patch also drops the mention of errata reporting around
FEATURE_DETECTION as this hasn't been true for some time.

Change-Id: I4a94dce243e430d5d3528c66154075b4352cd520
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "fix(qti): don't fail to write dload mode register" into integration

refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely,

refactor(el3-runtime): generalise sysreg trapping

On a first look, the system register trapping code is quite
straightforward - match the register and call a handler. But looking a
bit more closely, with the intention of adding a new one, it isn't -
matching is based on opaque magic numbers and handlers have a lot of
duplication.

This patch tries to resolve both of these by hoisting common
functionality up towards common code and using S3 encodings for the
register matching. It also moves things around a bit to make them more
reusable in future.

Change-Id: Ia69289bfb16615312cc7adcc5cc3e319174b1bf0
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge changes from topics "mb/fix-include-order", "mb/juno-BL2-size-fix" into integration

* changes:
fix(arm): rearrange the include order
fix(juno): increase BL2 maximum size to 0x15000

Merge changes from topic "xlnx_fix_bl31_addr64" into integration

* changes:
fix(versal2): use 64-bit macros for BL31 checks
fix(versal-net): use 64-bit macros for BL31 checks
fix(versal): use

Merge changes from topic "xlnx_fix_bl31_addr64" into integration

* changes:
fix(versal2): use 64-bit macros for BL31 checks
fix(versal-net): use 64-bit macros for BL31 checks
fix(versal): use 64-bit macros for BL31 checks

show more ...

feat(imx93): enable the s401 clock on/off handshake

Enable s401 clock on/off handshake to make sure s401 is in
idle/known status before glock gating.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Rev

feat(imx93): enable the s401 clock on/off handshake

Enable s401 clock on/off handshake to make sure s401 is in
idle/known status before glock gating.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I6cea378ee62a00404cb4078f2e4c24816b43761f

show more ...

fix(imx93): reduce the pmic stby off delay

The default PMIC STBY OFF delay is about 78ms, it is too long.
To optimize the system resume latency, reduce the PMIC STBY OFF
delay to 1.5ms, This delay i

fix(imx93): reduce the pmic stby off delay

The default PMIC STBY OFF delay is about 78ms, it is too long.
To optimize the system resume latency, reduce the PMIC STBY OFF
delay to 1.5ms, This delay is large enough to cover the PMIC regulator
voltage ramp up latency when PMIC exit from the STBY mode.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I184e85282d43a34beac317f90fcd1789fd8184ee

show more ...

feat(imx93): optimize power switch acknowledgment timing

The PSW_ACK_CTRL register's CNT_MODE field controls the timing of
power switch acknowledgment during low power mode transitions.

The default

feat(imx93): optimize power switch acknowledgment timing

The PSW_ACK_CTRL register's CNT_MODE field controls the timing of
power switch acknowledgment during low power mode transitions.

The default CNT_MODE value of 0x1 introduces an unnecessary ~1ms
delay when exiting low power modes for A55 cores and cluster.

Set CNT_MODE to 0x0 (instant acknowledgment) for A55 core & cluster
to eliminate unnecessary latency.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Change-Id: I7f72d199ad9cd336fc90dde1dafb7012b08b812f

show more ...

feat(imx93): retrieve SoC info from EdgeLock Enclave

Query the EdgeLock Enclave (ELE) during platform setup to obtain
SoC identification information. This enables runtime access to
device-specific d

feat(imx93): retrieve SoC info from EdgeLock Enclave

Query the EdgeLock Enclave (ELE) during platform setup to obtain
SoC identification information. This enables runtime access to
device-specific data such as SoC revision and security state.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I89f10ae02848300e12ff82cf4c5f9f79aa6eaa19

show more ...

refactor(imx93): migrate to common GICv3 driver

Enable USE_GIC_DRIVER to leverage the common GICv3 driver
implementation instead of platform-specific GIC initialization code.

This reduces code dupl

refactor(imx93): migrate to common GICv3 driver

Enable USE_GIC_DRIVER to leverage the common GICv3 driver
implementation instead of platform-specific GIC initialization code.

This reduces code duplication and improves maintainability by
reusing the common GIC driver infrastructure.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: If2f90692a666b2d25aaccff77ff406f3f880fe0b

show more ...

fix(imx93): reduce BL31 limit to reserve DRAM timing area

The DRAM timing parameters are stored at the end of OCRAM region.
Previously, BL31_LIMIT was set to 0x20520000, which overlaps with
this res

fix(imx93): reduce BL31 limit to reserve DRAM timing area

The DRAM timing parameters are stored at the end of OCRAM region.
Previously, BL31_LIMIT was set to 0x20520000, which overlaps with
this reserved area.

Reduce BL31_LIMIT from 0x20520000 to 0x2051C000, reserving the last
16KB of the OCRAM region for DRAM timing storage:

OCRAM layout:
+-------------------+ 0x20480000 (OCRAM_BASE)
| |
+-------------------+ 0x204E0000 (BL31_BASE)
| BL31 |
| (240KB max) |
+-------------------+ 0x2051C000 (BL31_LIMIT)
| DRAM timing |
| (16KB) |
+-------------------+ 0x20520000 (OCRAM_BASE + OCRAM_SIZE)

Introduce BL31_SIZE (256KB) for memory mapping purposes, while
BL31_LIMIT enforces the actual binary size constraint at link time.
This enables the linker to detect potential memory overlap issues
during compilation rather than at runtime.

Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Change-Id: I0c0466d65ebac7f51e74ea279dadae469bd0e991

show more ...

fix(imx93): add null terminator to mmap region array

The mmap_add() API iterates through the memory region array until it
encounters a zero entry. Without a proper null terminator {0}, the
behavior

fix(imx93): add null terminator to mmap region array

The mmap_add() API iterates through the memory region array until it
encounters a zero entry. Without a proper null terminator {0}, the
behavior is undefined.

When TF-A runs on OCRAM, the memory is zeroed by default, masking
this bug. However, when loaded by QNX SPL (which may place TF-A in
non-zeroed memory), the missing terminator causes boot failure.

Add the required {0} terminator to bl_regions[] array.

Signed-off-by: Maximus <maximus.sun@nxp.com>
Change-Id: If7f1313bcb04d97ac760e27984508ba4e6c6c752
Signed-off-by: Jacky Bai <ping.bai@nxp.com>

show more ...

fix(rcar3): fix order of DRAM DT nodes for 1x4 GiB bank

The 1x4 GiB bank has to be split into two 2 GiB memory@ nodes in
the DT, once for memory below 32 bit boundary and one for memory
above 32 bit

fix(rcar3): fix order of DRAM DT nodes for 1x4 GiB bank

The 1x4 GiB bank has to be split into two 2 GiB memory@ nodes in
the DT, once for memory below 32 bit boundary and one for memory
above 32 bit boundary. The order in which those memory nodes are
generated is reversed, because the newly generated node is always
added before the currently present node. This works for all nodes
except this special 1x4 GiB case, in which case the nodes are added
in reverse order. Fix this and generate the memory node below 32
bit boundary last, unless the memory layout is 1x2 GiB or less.

Before:
```
=> fdt print
/ {
...
memory@480000000 {
reg = <0x00000004 0x80000000 0x00000000 0x80000000>;
device_type = "memory";
};
memory@48000000 {
reg = <0x00000000 0x48000000 0x00000000 0x78000000>;
device_type = "memory";
};
...
```

After:
```
=> fdt print
/ {
...
memory@48000000 {
reg = <0x00000000 0x48000000 0x00000000 0x78000000>;
device_type = "memory";
};
memory@480000000 {
reg = <0x00000004 0x80000000 0x00000000 0x80000000>;
device_type = "memory";
};
...
```

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I10d36e040c07d1eb5ecfdd8b325ff1ee6d037502

show more ...

fix(rcar3): fix issue unable to access system RAM after warm boot

After a warm boot (Suspend-to-RAM), system RAM in the address range
0xE6300400 - 0xE6360000 becomes inaccessible in Linux. This can

fix(rcar3): fix issue unable to access system RAM after warm boot

After a warm boot (Suspend-to-RAM), system RAM in the address range
0xE6300400 - 0xE6360000 becomes inaccessible in Linux. This can be
observed in the kernel log as access errors when reading or writing
to this range, for example using devmem userspace tool.

The SPTCRn registers, which configure the security protection settings
for this RAM region are not reconfigured after a warm boot. As a
result, access remains restricted and Linux is unable to use the
protected area.

Call bl2_ram_security_setting_finish() from bl2_secure_setting() to
reconfigure SPTCRn during resume. This restores access permissions
to the protected system RAM region after Suspend-to-RAM.

Signed-off-by: Khuong Nguyen <khuong.nguyen.rb@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Change-Id: I772b918614fcf15c3efb64491632506ab6c09681

show more ...

feat(tc): add fpga flash regions in spmc manifest

Add fpga flash regions in spmc manifest so that fpga flash
can be used from secure partitions.

Change-Id: I14e130d1f840d63372d3ec937f0a8eca74a43da4

feat(tc): add fpga flash regions in spmc manifest

Add fpga flash regions in spmc manifest so that fpga flash
can be used from secure partitions.

Change-Id: I14e130d1f840d63372d3ec937f0a8eca74a43da4
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

feat(tc): support 6mid2big CPU topology for FPGA

Add config option to enable 6-mid/2-big CPU topology which replaces
little core with mid cores, this config is only applicable to
TC4-FPGA.

Change-I

feat(tc): support 6mid2big CPU topology for FPGA

Add config option to enable 6-mid/2-big CPU topology which replaces
little core with mid cores, this config is only applicable to
TC4-FPGA.

Change-Id: I5ba73743203445f95a0b7057305488c2f7a0fee4
Signed-off-by: Icen Zeyada <Icen.Zeyada2@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

fix(tc): don't use non-secure UART

Align FVP and FPGA UART usage

Change-Id: If574683c53dbc245b2d4978998d12cbd640c02b7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Ryan Ever

fix(tc): don't use non-secure UART

Align FVP and FPGA UART usage

Change-Id: If574683c53dbc245b2d4978998d12cbd640c02b7
Signed-off-by: Jagdish Gediya <jagdish.gediya@arm.com>
Signed-off-by: Ryan Everett <ryan.everett@arm.com>

show more ...

fix(arm): rearrange the include order

Rearrange the include order as per the TF-A guidance.

Change-Id: I9e28d4405043c6b9887d4c44b48d58323d047bd8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@ar

fix(arm): rearrange the include order

Rearrange the include order as per the TF-A guidance.

Change-Id: I9e28d4405043c6b9887d4c44b48d58323d047bd8
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...

fix(juno): increase BL2 maximum size to 0x15000

Increase the Juno BL2 size limit to 0x15000 to accommodate recent
BL2 growth.

Change-Id: I3860702630ebf9e74daa960329afc8da9ee86c65
Signed-off-by: Man

fix(juno): increase BL2 maximum size to 0x15000

Increase the Juno BL2 size limit to 0x15000 to accommodate recent
BL2 growth.

Change-Id: I3860702630ebf9e74daa960329afc8da9ee86c65
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...