feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the

feat(tc): use SFCP PSA call instead of RSE comms

Add the platform specific implementation for SFCP (the implementation of
the functions in sfcp_platform.h). This includes functions which specify
the device structures and also the routing tables.

Note that, because initially the SFCP stack is only used to make PSA
calls to the RSE, routing is only implemented for the TF-A <-> RSE
nodes. The only MHU devices defined in the SFCP platform implementation
are for this link and all other routes, as defined in the routing table,
as invalid.

This patch also removes compilation of RSE comms in favour of SFCP for
TC.

Change-Id: I432b05b2955c790c4a5ecff04764605c6ff0ceea
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

show more ...

feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions

feat(tc): add tc_sfcp.c

Add the SFCP platform configuration file for TC. This file defines the
functions in declared in sfcp_platform.h; these are used in
sfcp_link_hal.c.

Note that these functions are expected to be implemented by any TF-A
platform which makes use of the SFCP library, they define the underlying
device driver structures and the routing layout of the platform.

Change-Id: I4af7371decd1faabbd0ed7bc186339668a0c6b1a
Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com>

show more ...

fix(versal2): fix misra rule 8.4 violation

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or
function with externa

fix(versal2): fix misra rule 8.4 violation

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.8.4:
- A compatible declaration shall be visible when an object or
function with external linkage is defined.
- Fix:
- Declare pm_secure_lock as static to give it internal linkage.

Change-Id: Ie538b2382e214ee2a486259b4ecddc12082334fa
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

show more ...

fix(versal2): fix misra rule 5.7 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.5.7:
- A tag name shall be a unique identifier.
- Fix:
- Rename local variables to avoid

fix(versal2): fix misra rule 5.7 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.5.7:
- A tag name shall be a unique identifier.
- Fix:
- Rename local variables to avoid conflict with type names.

Change-Id: Iac8df3166dcc69ceccaaddae2134f9c8a043b3b6
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

show more ...

fix(versal2): fix misra rule 18.1 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.18.1:
- A pointer resulting from arithmetic on a pointer operand shall
address an elem

fix(versal2): fix misra rule 18.1 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.18.1:
- A pointer resulting from arithmetic on a pointer operand shall
address an element of the same array as that pointer operand.
- Fix:
- Add upper bounds check before array access to prevent buffer
overrun.

Change-Id: I56e8201f2bf0de1d276d2ee009dafc73f08caf75
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

show more ...

fix(versal2): fix misra rule 10.4 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic
conversions are per

fix(versal2): fix misra rule 10.4 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.4:
- Both operands of an operator in which the usual arithmetic
conversions are performed shall have the same essential type
category.
- Fix:
- Make operands of the same essential type category.

Change-Id: Idf3489dee8f45a5a27bda4e4392b84510352623e
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

show more ...

fix(versal2): fix misra rule 10.3 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower

fix(versal2): fix misra rule 10.3 violations

Fix below MISRA violation:
- MISRA Violation: MISRA-C:2012 R.10.3:
- The value of an expression shall not be assigned to an object
with a narrower essential type or of a different essential type
category.
- Fix:
- Add explicit type casts to prevent implicit narrowing
conversions.

Change-Id: I756137cf9a403f1f6395c1d7c2d9bb70a3f6ff80
Signed-off-by: Devanshi Chauhan <Devanshi.ChauhanAlpeshbhai@amd.com>

show more ...

fix(mt8196): check apusys write ce binary address

The address and value to be written to the CE bin are set by the image
loaded by the kernel.
Check the address to ensure that no illegal address is

fix(mt8196): check apusys write ce binary address

The address and value to be written to the CE bin are set by the image
loaded by the kernel.
Check the address to ensure that no illegal address is accessed.

Change-Id: I907156cb9f304825839433cae0e31b319abc22bd
Signed-off-by: Yuan-chang Hsieh <yuan-chang.hsieh@mediatek.corp-partner.google.com>

show more ...

fix(mt8196): increase apusys hardware semaphore timeout duration

Increase the hw semaphore timeout duration because the kernel may
occasionally fail to acquire semaphore, resulting in power on/off
f

fix(mt8196): increase apusys hardware semaphore timeout duration

Increase the hw semaphore timeout duration because the kernel may
occasionally fail to acquire semaphore, resulting in power on/off
failed.

Change-Id: I377ef95063eb82abf2a63ea8f8fce803ef45bcf6
Signed-off-by: Yuan-chang Hsieh <yuan-chang.hsieh@mediatek.corp-partner.google.com>

show more ...

feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB

Both are now FEAT_STATE_CHECKED enabled so they can be now be used.

Change-Id: I2485d583349e432014808a775ef57799eed4a596
Signed-off-by: Boyan K

feat(qemu): enable ENABLE_FEAT_RAS and ENABLE_FEAT_SB

Both are now FEAT_STATE_CHECKED enabled so they can be now be used.

Change-Id: I2485d583349e432014808a775ef57799eed4a596
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

FEAT_SB is mostly FEAT_STATE_CHECKED enabled but that is not apparent
from docs and code's check is sub-optimal. Update docs to make this
ap

feat(cpufeat): update FEAT_SB's FEAT_STATE_CHECKED status

FEAT_SB is mostly FEAT_STATE_CHECKED enabled but that is not apparent
from docs and code's check is sub-optimal. Update docs to make this
apparent and update code to have a proper FEAT_STATE_CHECKED fallback.

Also enable it for FVP so it's tested a bit more.

Change-Id: I1374c4828b235ad16904f6c4ac9e39b9c2596a37
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply

feat(cpufeat): enable FEAT_RAS for FEAT_STATE_CHECKED again

FEAT_RAS was originally converted to FEAT_STATE_CHECKED in 6503ff291.
However, the ability to use it was removed with 970a4a8d8 by simply
saying it impacts execution at EL3. That's true, but FEAT_STATE_CHECKED
can still be allowed by being a bit clever about it.

First, the remainder of common code can be converted to use the
is_feat_ras_supported() helper instead of the `#if FEATURE` pattern.
There are no corner cases to consider there. The feature is either
present (and appropriate action must be taken) or the feature is not (so
we can skip RAS code).

A conscious choice is taken to check the RAS code in synchronize_errors
despite it being in a hot path. Any fixed platform that seeks to be
performant should be setting features to 0 or 1. Then, the
SCTLR_EL3.IESB bit is always set if ENABLE_FEAT_RAS != 0 since we expect
FEAT_IESB to be present if FEAT_RAS is (despite the architecture not
guaranteeing it). If FEAT_RAS isn't present then we don't particularly
care about the status of FEAT_IESB.

Second, platforms that don't set ENABLE_FEAT_RAS must continue to work.
This is true out of the box with the is_feat_xyz_supported() helpers, as
they make sure to fully disable code within them.

Third, platforms that do set ENABLE_FEAT_RAS=1 must continue to work.
This is also true out of the box and no logical change is undertaken in
common code.

Finally, ENABLE_FEAT_RAS is set to 2 on FVP. Having RAS implies that the
whole handling machinery will be built-in and registered as appropriate.
However, when RAS is built-in but not present in hardware, these
registrations can still happen, they will only never be invoked at
runtime.

Change-Id: I949e648601dc0951ef9c2b217f34136b6ea4b3dc
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>

show more ...

Merge "feat(cpus): add support for Rosillo cpu" into integration

Merge changes from topic "upstream_ddr_reg_accesories" into integration

* changes:
feat(s32g274ardb): add DDR register accessories
feat(s32g274ardb): add DDR PHY mailbox support

feat(cpus): add support for Rosillo cpu

Add basic CPU library code to support Rosillo CPU

Change-Id: I0e11e511511562297e4dccd2745842ebcfa2bff4
Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>

Merge "refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform" into integration

refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform

Rename console_rcar_ to console_renesas_ prefix for SCIF-based console
driver to make it reusable by other Renesa

refactor(rcar): rename console_rcar_ to console_renesas_ prefix for Renesas platform

Rename console_rcar_ to console_renesas_ prefix for SCIF-based console
driver to make it reusable by other Renesas platforms.

Due to the above renaming, function console_renesas_register is duplicated
in both scif.h and console.h, so it should be removed from scif.h

Change-Id: I42b44d1786578f7ed8db34e7da421836ea60b5e2
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

show more ...

Merge changes from topic "bk/simpler_panic" into integration

* changes:
refactor(aarch64): remove crash reporting's dependency on cpu_data
fix(el3-runtime): remove lower_el_panic()

Merge changes from topic "at/ras-rdaspen" into integration

* changes:
feat(rdaspen/ras): dump the CPER buffer contents
feat(rdaspen/ras): generate CPER at TF-A EL3
feat(rdaspen/ras): add DT bu

Merge changes from topic "at/ras-rdaspen" into integration

* changes:
feat(rdaspen/ras): dump the CPER buffer contents
feat(rdaspen/ras): generate CPER at TF-A EL3
feat(rdaspen/ras): add DT buffer and IRQ setup
feat(rdaspen): event handler for CPU RAS
feat(rdaspen/ras): intr RAS handling for PC CPU

show more ...

Merge "feat(rk3588): report actual measured PVTPLL clocks" into integration

fix(arm): build fails on RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1

Use ARM_FW_CONFIG_BASE and ARM_FW_CONFIG_MAX_SIZE instead of platform
macros PLAT_FW_CONFIG_BASE and PLAT_FW_CONFIG_MAX_SIZE w

fix(arm): build fails on RESET_TO_BL2=1 and ARM_FW_CONFIG_LOAD_ENABLE=1

Use ARM_FW_CONFIG_BASE and ARM_FW_CONFIG_MAX_SIZE instead of platform
macros PLAT_FW_CONFIG_BASE and PLAT_FW_CONFIG_MAX_SIZE when
RESET_TO_BL2 and ARM_FW_CONFIG_LOAD_ENABLE are set to 1.

Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
Change-Id: I0848852250eba5a3328e25cbea4fff413f344327

show more ...

feat(rdaspen/ras): dump the CPER buffer contents

Print the contents of the buffer to verify the fields set.

Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagou

feat(rdaspen/ras): dump the CPER buffer contents

Print the contents of the buffer to verify the fields set.

Change-Id: Ibb0683c99eed17d40ed5ce410fe19fab7e6bb9e6
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

show more ...

feat(rdaspen/ras): generate CPER at TF-A EL3

Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.

The CPER record consists of:
ESB Header
ESB Da

feat(rdaspen/ras): generate CPER at TF-A EL3

Generate CPER buffer at TF-A EL3, that emits the error data,
when there is a CPU RAS error in the system.

The CPER record consists of:
ESB Header
ESB Data Entry
CPER CPU Error Section
- Arm Processor Error Record
- Arm Processor Error Information
- Arm Processor Context Information

Change-Id: I7e9703a69edec15cbb6f0522333700bb8d7007bf
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

show more ...

feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
S

feat(rdaspen/ras): add DT buffer and IRQ setup

Added node to map reserved memory for CPER.
Interrupt set from TF-A for RAS error notification.

Change-Id: Id7e296772275cdf76c81d8d62294b0bce94bbf57
Signed-off-by: Sanjana Virupakshagouda <sanjana.virupakshagouda@arm.com>

show more ...

feat(rdaspen): event handler for CPU RAS

This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.

This also enables all i

feat(rdaspen): event handler for CPU RAS

This patch introduces assembly helpers for cleaning CPU
RAS, and introduces a way to deassert FAULT IRQ generated
from CE injection.

This also enables all inband errors to be handled on AP according
to a CPU RAS event handler:

- Skips spurious entries – returns early when
`ERXSTATUS.{V|CE}` is already clear, disposing of queued phantom
interrupts.

- Clears the error record – rewrites `ERXSTATUS_EL1`, zeros
`ERXMISC0`, `PFG_CTL`, and `PFG_CDN`, then logs the post clear state
for firmware trace.

Inband errors only consist of:
- Corrected Errors
- Deferred Errors

- Change the RAS CPU intr handler logs from VERBOSE to WARN.

Change-Id: I7eb8fecb42095551f51c9d1c5752775f1b577970
Signed-off-by: Ahmed Azeem <ahmed.azeem@arm.com>
Signed-off-by: Ahmed Tiba <ahmed.tiba@arm.com>

show more ...