feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2

feat(intel): increase bl2 size limit

There are several features included in BL2 causing the size getting
bigger for RELEASE mode. When build with DEBUG mode, the size will
be bigger thus causing BL2 image has exceeded its limits.

Change-Id: I7542f5ea001542450695d48e8126bcca8728d76a
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

fix(intel): update stream id to non-secure for SDM

Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.

Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-

fix(intel): update stream id to non-secure for SDM

Update stream id to non-secure for SDM which is to
bring up FPGA config via SMMU.

Change-Id: Ib8836fa0cf31fe0cfc0261123e051772923bb66b
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): revert sys counter to 400MHz

For Simics and official release, revert back to 400MHz instead of
80MHz. Sys counter shall get from a static clock.

Change-Id: I9ee3586bc411af8d7381c8bd6404

fix(intel): revert sys counter to 400MHz

For Simics and official release, revert back to 400MHz instead of
80MHz. Sys counter shall get from a static clock.

Change-Id: I9ee3586bc411af8d7381c8bd6404b8449b0c3f69
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

Merge changes from topic "morello/firmware-revision" into integration

* changes:
feat(morello): add TF-A version string to NT_FW_CONFIG
feat(morello): set NT_FW_CONFIG properties for MCC, PCC an

Merge changes from topic "morello/firmware-revision" into integration

* changes:
feat(morello): add TF-A version string to NT_FW_CONFIG
feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version

show more ...

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support

Merge changes from topic "xlnx_tsp_feat" into integration

* changes:
docs(versal-net): add TSP build documentation
docs(versal): add TSP build documentation
feat(versal-net): add tsp support
feat(versal): add tsp support
refactor(xilinx): add generic TSP makefile
chore(zynqmp): reorganize tsp code into common path
refactor(xilinx): rename platform function to generic name

show more ...

fix(intel): update HPS bridges for Agilex5 SoC FPGA

This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA

fix(intel): update HPS bridges for Agilex5 SoC FPGA

This patch is used to update reset manager support
for Agilex5 Soc FPGA.
1. Update HPS bridges support for socfpga_bridges_disable
a. SOC2FPGA
b. LWSOC2FPGA
c. F2SDRAM
d. F2SOC

Change-Id: Ia539ff289e83303ae3b4d78b9ac1d50c9f9558da
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): temporarily workaround for Zephyr SMP

Temporarily workaround for Zephyr SMP testing.

Change-Id: I9d2d209e9f384d079f0311b3a8b0b760e0566877
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@int

fix(intel): temporarily workaround for Zephyr SMP

Temporarily workaround for Zephyr SMP testing.

Change-Id: I9d2d209e9f384d079f0311b3a8b0b760e0566877
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

fix(intel): update boot scratch cold register to use cold 8

Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id

fix(intel): update boot scratch cold register to use cold 8

Boot scratch cold 8 register is fully used by n5x.
Update to use boot scratch cold 8 bit 19 register for cpu0 ON/OFF
indicator.

Change-Id: I45ebfdcc17c47bcce69f5f611e677ac7838ecf52
Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>

show more ...

feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain

feat(intel): restructure watchdog

This patch is to restructure watchdog.
Move platform dependent MACROs to individual platform socfpga_plat_def.
Common watchdog code file and header file will remain for those common
declaration.

Change-Id: Ibb640f08ac313bbad6d9295596cb8ff26e3e626d
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>

show more ...

feat(morello): add TF-A version string to NT_FW_CONFIG

TF-A version string is passed into NT_FW_CONFIG to allow access in
UEFI.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I9da7b9

feat(morello): add TF-A version string to NT_FW_CONFIG

TF-A version string is passed into NT_FW_CONFIG to allow access in
UEFI.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: I9da7b93d30c9d9230ea9a2cd2730cde897ffc580

show more ...

feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version

SDS firmware version structure is added with MCC, PCC and SCP firmware
version members. These are set in NT_FW_CONFIG to provi

feat(morello): set NT_FW_CONFIG properties for MCC, PCC and SCP version

SDS firmware version structure is added with MCC, PCC and SCP firmware
version members. These are set in NT_FW_CONFIG to provide access to
firmware version information in UEFI.

Signed-off-by: Werner Lewis <werner.lewis@arm.com>
Change-Id: Ib0c476e54ef428fb7904f0de5c6f4df6a5fbd7db

show more ...

feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-o

feat(zynqmp): remove pm_ioctl_set_sgmii_mode api

There are no existing users of pm_ioctl_set_sgmii_mode() API so
cleanup the dead code.

Change-Id: I1088d2f5c944bf54fc5fdd554360bdd321ad798a
Signed-off-by: Ronak Jain <ronak.jain@amd.com>

show more ...

Merge changes from topic "mp/exceptions" into integration

* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict low

Merge changes from topic "mp/exceptions" into integration

* changes:
docs(ras): update RAS documentation
docs(el3-runtime): update BL31 exception vector handling
fix(el3-runtime): restrict lower el EA handlers in FFH mode
fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT
fix(ras): restrict ENABLE_FEAT_RAS to have only two states
feat(ras): use FEAT_IESB for error synchronization
feat(el3-runtime): modify vector entry paths

show more ...

feat(versal-net): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execut

feat(versal-net): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal NET platform. TSP is a component for testing and validating
secure OS and trusted execution environments.

If a BL32 image is present, then there must be a matching Secure-EL1
Payload Dispatcher (SPD) service called TSPD, this service is
responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of BL32
once the runtime services are fully initialized. BL31 invokes such
a registered function to initialize BL32 before running BL33.

The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3 This is
because the S-EL1 can use GIC system registers to manage interrupts
and does not need GIC interface base addresses to be configured.

The secure code load address is initially being pointed to 0x0 in the
handoff parameters, which is different from the default or user-provided
load address of 0x60000000. In this case, set up the PC to the
requested BL32_BASE address to ensure that the secure code is loaded
and executed from the correct location.

Change-Id: I58fe256dc9d6be5cee384c5ebb9baca2737c02a6
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

show more ...

feat(versal): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution envi

feat(versal): add tsp support

Introduces support for the Test Secure Payload (TSP) for AMD-Xilinx
Versal platform. TSP is a component for testing and validating
secure OS and trusted execution environments.

If a BL32 image is present, then there must be a matching Secure-
EL1 Payload Dispatcher (SPD) service called TSPD, this service
is responsible for Initializing the TSP. During initialization that
service must register a function to carry out initialization of
BL32 once the runtime services are fully initialized. BL31 invokes
such a registered function to initialize BL32 before running BL33.

The GICv3 driver is initialized in EL3 and does not need to be
initialized again in SEL1 GICv3 driver is initialized in EL3
This is because the S-EL1 can use GIC system registers to manage
interrupts and does not need GIC interface base addresses to be
configured.

The secure code load address is initially being pointed to 0x0
in the handoff parameters, which is different from the default
or user-provided load address of 0x60000000. In this case, set up
the PC to the requested BL32_BASE address to ensure that the secure
code is loaded and executed from the correct location.

Change-Id: Ida0fc6467a10bfde8927ff9b3755a83f3e16f068
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

show more ...

refactor(xilinx): add generic TSP makefile

Updated the generic TSP makefile in the common path for reuse in
different platforms.

Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by:

refactor(xilinx): add generic TSP makefile

Updated the generic TSP makefile in the common path for reuse in
different platforms.

Change-Id: Idd14675bc547e0a4a95132653a181e7ff39a547a
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

show more ...

Merge changes from topic "fw-caps" into integration

* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove

Merge changes from topic "fw-caps" into integration

* changes:
feat(ti): query firmware for suspend capability
feat(ti): add TI-SCI query firmware capabilities command support
feat(ti): remove extra core counts in cluster 2 and 3

show more ...

fix(tegra): return correct error code for plat_core_pos_by_mpidr

The error code for plat_core_pos_by_mpidr() for an invalid mpidr should
be -1 as mandated by portig guide, but for tegra t186 return

fix(tegra): return correct error code for plat_core_pos_by_mpidr

The error code for plat_core_pos_by_mpidr() for an invalid mpidr should
be -1 as mandated by portig guide, but for tegra t186 return value is
PSCI_E_NOT_PRESENT (-7) even though the comment at top of function says
that it should return -1.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I2b69bc1a56f7966f21b2a3c89c515ebde41e3eb8

show more ...

fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT

This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
inter

fix(ras): remove RAS_FFH_SUPPORT and introduce FFH_SUPPORT

This patch removes RAS_FFH_SUPPORT macro which is the combination of
ENABLE_FEAT_RAS and HANDLE_EA_EL3_FIRST_NS. Instead introduce an
internal macro FFH_SUPPORT which gets enabled when platforms wants
to enable lower EL EA handling at EL3. The internal macro FFH_SUPPORT
will be automatically enabled if HANDLE_EA_EL3_FIRST_NS is enabled.
FFH_SUPPORT along with ENABLE_FEAT_RAS will be used in source files
to provide equivalent check which was provided by RAS_FFH_SUPPORT
earlier. In generic code we needed a macro which could abstract both
HANDLE_EA_EL3_FIRST_NS and RAS_FFH_SUPPORT macros that had limitations.
Former was tied up with NS world only while the latter was tied to RAS
feature.

This is to allow Secure/Realm world to have their own FFH macros
in future.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: Ie5692ccbf462f5dcc3f005a5beea5aa35124ac73

show more ...

chore(zynqmp): reorganize tsp code into common path

Reorganized TSP code into common folder, updated paths in
tsp-zynqmp.mk. Handling the return value of a console registration
function.

Change-Id:

chore(zynqmp): reorganize tsp code into common path

Reorganized TSP code into common folder, updated paths in
tsp-zynqmp.mk. Handling the return value of a console registration
function.

Change-Id: I848f17c3417b3e8c8cbd2058e9642ed13d121325
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

show more ...

refactor(xilinx): rename platform function to generic name

Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_g

refactor(xilinx): rename platform function to generic name

Refactor two platform specific functions, plat_versal_get_mmap() and
plat_versal_net_get_mmap(), to use a more generic function name
plat_get_mmap(). The function can be used in the common code to
obtain memory region.

Change-Id: I3eeb24aff217eef30af60a7742cbebe9d3b2edce
Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>

show more ...

Merge changes from topic "hst/cs1k-add-gpt-support" into integration

* changes:
feat(bl2): add gpt support
fix(corstone-1000): modify boot device dependencies
fix(corstone-1000): removing the

Merge changes from topic "hst/cs1k-add-gpt-support" into integration

* changes:
feat(bl2): add gpt support
fix(corstone-1000): modify boot device dependencies
fix(corstone-1000): removing the signature area

show more ...

fix(ras): restrict ENABLE_FEAT_RAS to have only two states

As part of migrating RAS extension to feature detection mechanism, the
macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_ST

fix(ras): restrict ENABLE_FEAT_RAS to have only two states

As part of migrating RAS extension to feature detection mechanism, the
macro ENABLE_FEAT_RAS was allowed to have dynamic detection (FEAT_STATE
2). Considering this feature does impact execution of EL3 and we need
to know at compile time about the presence of this feature. Do not use
dynamic detection part of feature detection mechanism.

Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
Change-Id: I23858f641f81fbd81b6b17504eb4a2cc65c1a752

show more ...

feat(bl2): add gpt support

This includes initialization of the partition with
the GPT_IMAGE_ID.

Change-Id: I51b09d82ff40207369d76011556f40169196af22
Signed-off-by: Mohamed Omar Asaker <mohamed.omar

feat(bl2): add gpt support

This includes initialization of the partition with
the GPT_IMAGE_ID.

Change-Id: I51b09d82ff40207369d76011556f40169196af22
Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

show more ...

fix(corstone-1000): modify boot device dependencies

Modify boot device dependencies and remove the one's
which are not needed.

Change-Id: I71cd60558ab4bb5162afefad4f00d631c2308e72
Signed-off-by: Mo

fix(corstone-1000): modify boot device dependencies

Modify boot device dependencies and remove the one's
which are not needed.

Change-Id: I71cd60558ab4bb5162afefad4f00d631c2308e72
Signed-off-by: Mohamed Omar Asaker <mohamed.omarasaker@arm.com>
Signed-off-by: Harsimran Singh Tungal <harsimransingh.tungal@arm.com>

show more ...