1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 mailbox_clear_response(); 233 234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 235 CMD_CASUAL, NULL, NULL); 236 237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 238 CMD_CASUAL, response, &resp_len); 239 240 if (status < 0) { 241 bridge_disable = false; 242 request_type = NO_REQUEST; 243 return INTEL_SIP_SMC_STATUS_ERROR; 244 } 245 246 max_blocks = response[0]; 247 bytes_per_block = response[1]; 248 249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 250 fpga_config_buffers[i].size = 0; 251 fpga_config_buffers[i].size_written = 0; 252 fpga_config_buffers[i].addr = 0; 253 fpga_config_buffers[i].write_requested = 0; 254 fpga_config_buffers[i].block_number = 0; 255 fpga_config_buffers[i].subblocks_sent = 0; 256 } 257 258 blocks_submitted = 0; 259 current_block = 0; 260 read_block = 0; 261 current_buffer = 0; 262 263 /* Disable bridge on full reconfiguration */ 264 if (bridge_disable) { 265 socfpga_bridges_disable(~0); 266 } 267 268 return INTEL_SIP_SMC_STATUS_OK; 269 } 270 271 static bool is_fpga_config_buffer_full(void) 272 { 273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 274 if (!fpga_config_buffers[i].write_requested) { 275 return false; 276 } 277 } 278 return true; 279 } 280 281 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 282 { 283 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 284 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 285 286 if (!addr && !size) { 287 return true; 288 } 289 if (size > (UINT64_MAX - addr)) { 290 return false; 291 } 292 if (addr < BL31_LIMIT) { 293 return false; 294 } 295 if (dram_region_end > dram_max_sz) { 296 return false; 297 } 298 299 return true; 300 } 301 302 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 303 { 304 int i; 305 306 intel_fpga_sdm_write_all(); 307 308 if (!is_address_in_ddr_range(mem, size) || 309 is_fpga_config_buffer_full()) { 310 return INTEL_SIP_SMC_STATUS_REJECTED; 311 } 312 313 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 314 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 315 316 if (!fpga_config_buffers[j].write_requested) { 317 fpga_config_buffers[j].addr = mem; 318 fpga_config_buffers[j].size = size; 319 fpga_config_buffers[j].size_written = 0; 320 fpga_config_buffers[j].write_requested = 1; 321 fpga_config_buffers[j].block_number = 322 blocks_submitted++; 323 fpga_config_buffers[j].subblocks_sent = 0; 324 break; 325 } 326 } 327 328 if (is_fpga_config_buffer_full()) { 329 return INTEL_SIP_SMC_STATUS_BUSY; 330 } 331 332 return INTEL_SIP_SMC_STATUS_OK; 333 } 334 335 static int is_out_of_sec_range(uint64_t reg_addr) 336 { 337 #if DEBUG 338 return 0; 339 #endif 340 341 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 342 switch (reg_addr) { 343 case(0xF8011100): /* ECCCTRL1 */ 344 case(0xF8011104): /* ECCCTRL2 */ 345 case(0xF8011110): /* ERRINTEN */ 346 case(0xF8011114): /* ERRINTENS */ 347 case(0xF8011118): /* ERRINTENR */ 348 case(0xF801111C): /* INTMODE */ 349 case(0xF8011120): /* INTSTAT */ 350 case(0xF8011124): /* DIAGINTTEST */ 351 case(0xF801112C): /* DERRADDRA */ 352 case(0xFA000000): /* SMMU SCR0 */ 353 case(0xFA000004): /* SMMU SCR1 */ 354 case(0xFA000400): /* SMMU NSCR0 */ 355 case(0xFA004000): /* SMMU SSD0_REG */ 356 case(0xFA000820): /* SMMU SMR8 */ 357 case(0xFA000c20): /* SMMU SCR8 */ 358 case(0xFA028000): /* SMMU CB8_SCTRL */ 359 case(0xFA001020): /* SMMU CBAR8 */ 360 case(0xFA028030): /* SMMU TCR_LPAE */ 361 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 362 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 363 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 364 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 365 case(0xFA028010): /* SMMU_CB8)TCR2 */ 366 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 367 case(0xFA001820): /* SMMU_CBA2R8 */ 368 case(0xFA000074): /* SMMU_STLBGSTATUS */ 369 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 370 case(0xFA000060): /* SMMU_STLBIALL */ 371 case(0xFA000070): /* SMMU_STLBGSYNC */ 372 case(0xFA028618): /* CB8_TLBALL */ 373 case(0xFA0287F0): /* CB8_TLBSYNC */ 374 case(0xFFD12028): /* SDMMCGRP_CTRL */ 375 case(0xFFD12044): /* EMAC0 */ 376 case(0xFFD12048): /* EMAC1 */ 377 case(0xFFD1204C): /* EMAC2 */ 378 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 379 case(0xFFD12094): /* ECC_INT_MASK_SET */ 380 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 381 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 382 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 383 case(0xFFD120C0): /* NOC_TIMEOUT */ 384 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 385 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 386 case(0xFFD120D0): /* NOC_IDLEACK */ 387 case(0xFFD120D4): /* NOC_IDLESTATUS */ 388 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 389 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 390 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 391 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 392 return 0; 393 #else 394 switch (reg_addr) { 395 396 case(0xF8011104): /* ECCCTRL2 */ 397 case(0xFFD12028): /* SDMMCGRP_CTRL */ 398 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 399 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 400 case(0xFFD120D0): /* NOC_IDLEACK */ 401 402 403 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 404 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 405 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 406 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 407 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 408 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 409 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 410 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 411 412 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 413 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 414 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 415 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 416 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 417 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 418 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 419 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 420 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 421 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 422 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 423 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 424 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 425 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 426 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 427 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 428 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 429 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 430 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 431 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 432 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 433 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 434 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 435 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 436 return 0; 437 #endif 438 default: 439 break; 440 } 441 442 return -1; 443 } 444 445 /* Secure register access */ 446 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 447 { 448 if (is_out_of_sec_range(reg_addr)) { 449 return INTEL_SIP_SMC_STATUS_ERROR; 450 } 451 452 *retval = mmio_read_32(reg_addr); 453 454 return INTEL_SIP_SMC_STATUS_OK; 455 } 456 457 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 458 uint32_t *retval) 459 { 460 if (is_out_of_sec_range(reg_addr)) { 461 return INTEL_SIP_SMC_STATUS_ERROR; 462 } 463 464 switch (reg_addr) { 465 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 466 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 467 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 468 mmio_write_16(reg_addr, val); 469 break; 470 #endif 471 default: 472 mmio_write_32(reg_addr, val); 473 break; 474 } 475 476 return intel_secure_reg_read(reg_addr, retval); 477 } 478 479 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 480 uint32_t val, uint32_t *retval) 481 { 482 if (!intel_secure_reg_read(reg_addr, retval)) { 483 *retval &= ~mask; 484 *retval |= val & mask; 485 return intel_secure_reg_write(reg_addr, *retval, retval); 486 } 487 488 return INTEL_SIP_SMC_STATUS_ERROR; 489 } 490 491 /* Intel Remote System Update (RSU) services */ 492 uint64_t intel_rsu_update_address; 493 494 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 495 { 496 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 497 return INTEL_SIP_SMC_RSU_ERROR; 498 } 499 500 return INTEL_SIP_SMC_STATUS_OK; 501 } 502 503 uint32_t intel_rsu_update(uint64_t update_address) 504 { 505 if (update_address > SIZE_MAX) { 506 return INTEL_SIP_SMC_STATUS_REJECTED; 507 } 508 509 intel_rsu_update_address = update_address; 510 return INTEL_SIP_SMC_STATUS_OK; 511 } 512 513 static uint32_t intel_rsu_notify(uint32_t execution_stage) 514 { 515 if (mailbox_hps_stage_notify(execution_stage) < 0) { 516 return INTEL_SIP_SMC_RSU_ERROR; 517 } 518 519 return INTEL_SIP_SMC_STATUS_OK; 520 } 521 522 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 523 uint32_t *ret_stat) 524 { 525 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 526 return INTEL_SIP_SMC_RSU_ERROR; 527 } 528 529 *ret_stat = respbuf[8]; 530 return INTEL_SIP_SMC_STATUS_OK; 531 } 532 533 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 534 uint64_t dcmf_ver_3_2) 535 { 536 rsu_dcmf_ver[0] = dcmf_ver_1_0; 537 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 538 rsu_dcmf_ver[2] = dcmf_ver_3_2; 539 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 540 541 return INTEL_SIP_SMC_STATUS_OK; 542 } 543 544 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 545 { 546 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 547 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 548 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 549 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 550 551 return INTEL_SIP_SMC_STATUS_OK; 552 } 553 554 /* Intel HWMON services */ 555 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 556 { 557 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 558 return INTEL_SIP_SMC_STATUS_ERROR; 559 } 560 561 return INTEL_SIP_SMC_STATUS_OK; 562 } 563 564 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 565 { 566 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 567 return INTEL_SIP_SMC_STATUS_ERROR; 568 } 569 570 return INTEL_SIP_SMC_STATUS_OK; 571 } 572 573 /* Mailbox services */ 574 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 575 { 576 int status; 577 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 578 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 579 580 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 581 CMD_CASUAL, resp_data, &resp_len); 582 583 if (status < 0) { 584 return INTEL_SIP_SMC_STATUS_ERROR; 585 } 586 587 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 588 return INTEL_SIP_SMC_STATUS_ERROR; 589 } 590 591 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 592 593 return INTEL_SIP_SMC_STATUS_OK; 594 } 595 596 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 597 unsigned int len, uint32_t urgent, uint64_t response, 598 unsigned int resp_len, int *mbox_status, 599 unsigned int *len_in_resp) 600 { 601 *len_in_resp = 0; 602 *mbox_status = GENERIC_RESPONSE_ERROR; 603 604 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 605 return INTEL_SIP_SMC_STATUS_REJECTED; 606 } 607 608 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 609 (uint32_t *) response, &resp_len); 610 611 if (status < 0) { 612 *mbox_status = -status; 613 return INTEL_SIP_SMC_STATUS_ERROR; 614 } 615 616 *mbox_status = 0; 617 *len_in_resp = resp_len; 618 619 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 620 621 return INTEL_SIP_SMC_STATUS_OK; 622 } 623 624 static int intel_smc_get_usercode(uint32_t *user_code) 625 { 626 int status; 627 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 628 629 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 630 0U, CMD_CASUAL, user_code, &resp_len); 631 632 if (status < 0) { 633 return INTEL_SIP_SMC_STATUS_ERROR; 634 } 635 636 return INTEL_SIP_SMC_STATUS_OK; 637 } 638 639 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 640 uint32_t mode, uint32_t *job_id, 641 uint32_t *ret_size, uint32_t *mbox_error) 642 { 643 int status = 0; 644 uint32_t resp_len = size / MBOX_WORD_BYTE; 645 646 if (resp_len > MBOX_DATA_MAX_LEN) { 647 return INTEL_SIP_SMC_STATUS_REJECTED; 648 } 649 650 if (!is_address_in_ddr_range(addr, size)) { 651 return INTEL_SIP_SMC_STATUS_REJECTED; 652 } 653 654 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 655 status = mailbox_read_response_async(job_id, 656 NULL, (uint32_t *) addr, &resp_len, 0); 657 } else { 658 status = mailbox_read_response(job_id, 659 (uint32_t *) addr, &resp_len); 660 661 if (status == MBOX_NO_RESPONSE) { 662 status = MBOX_BUSY; 663 } 664 } 665 666 if (status == MBOX_NO_RESPONSE) { 667 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 668 } 669 670 if (status == MBOX_BUSY) { 671 return INTEL_SIP_SMC_STATUS_BUSY; 672 } 673 674 *ret_size = resp_len * MBOX_WORD_BYTE; 675 flush_dcache_range(addr, *ret_size); 676 677 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 678 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 679 *mbox_error = -status; 680 } else if (status != MBOX_RET_OK) { 681 *mbox_error = -status; 682 return INTEL_SIP_SMC_STATUS_ERROR; 683 } 684 685 return INTEL_SIP_SMC_STATUS_OK; 686 } 687 688 /* Miscellaneous HPS services */ 689 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 690 { 691 int status = 0; 692 693 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 694 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 695 status = socfpga_bridges_enable((uint32_t)mask); 696 } else { 697 status = socfpga_bridges_enable(~0); 698 } 699 } else { 700 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 701 status = socfpga_bridges_disable((uint32_t)mask); 702 } else { 703 status = socfpga_bridges_disable(~0); 704 } 705 } 706 707 if (status < 0) { 708 return INTEL_SIP_SMC_STATUS_ERROR; 709 } 710 711 return INTEL_SIP_SMC_STATUS_OK; 712 } 713 714 /* SDM SEU Error services */ 715 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 716 { 717 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 718 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 719 } 720 721 return INTEL_SIP_SMC_STATUS_OK; 722 } 723 724 /* SDM SAFE SEU Error inject services */ 725 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 726 { 727 if (mailbox_safe_inject_seu_err(command, len) < 0) { 728 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 729 } 730 731 return INTEL_SIP_SMC_STATUS_OK; 732 } 733 734 /* 735 * This function is responsible for handling all SiP calls from the NS world 736 */ 737 738 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 739 u_register_t x1, 740 u_register_t x2, 741 u_register_t x3, 742 u_register_t x4, 743 void *cookie, 744 void *handle, 745 u_register_t flags) 746 { 747 uint32_t retval = 0, completed_addr[3]; 748 uint32_t retval2 = 0; 749 uint32_t mbox_error = 0; 750 uint64_t retval64, rsu_respbuf[9]; 751 uint32_t seu_respbuf[3]; 752 int status = INTEL_SIP_SMC_STATUS_OK; 753 int mbox_status; 754 unsigned int len_in_resp; 755 u_register_t x5, x6, x7; 756 757 switch (smc_fid) { 758 case SIP_SVC_UID: 759 /* Return UID to the caller */ 760 SMC_UUID_RET(handle, intl_svc_uid); 761 762 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 763 status = intel_mailbox_fpga_config_isdone(); 764 SMC_RET4(handle, status, 0, 0, 0); 765 766 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 767 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 768 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 769 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 770 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 771 772 case INTEL_SIP_SMC_FPGA_CONFIG_START: 773 status = intel_fpga_config_start(x1); 774 SMC_RET4(handle, status, 0, 0, 0); 775 776 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 777 status = intel_fpga_config_write(x1, x2); 778 SMC_RET4(handle, status, 0, 0, 0); 779 780 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 781 status = intel_fpga_config_completed_write(completed_addr, 782 &retval, &rcv_id); 783 switch (retval) { 784 case 1: 785 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 786 completed_addr[0], 0, 0); 787 788 case 2: 789 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 790 completed_addr[0], 791 completed_addr[1], 0); 792 793 case 3: 794 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 795 completed_addr[0], 796 completed_addr[1], 797 completed_addr[2]); 798 799 case 0: 800 SMC_RET4(handle, status, 0, 0, 0); 801 802 default: 803 mailbox_clear_response(); 804 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 805 } 806 807 case INTEL_SIP_SMC_REG_READ: 808 status = intel_secure_reg_read(x1, &retval); 809 SMC_RET3(handle, status, retval, x1); 810 811 case INTEL_SIP_SMC_REG_WRITE: 812 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 813 SMC_RET3(handle, status, retval, x1); 814 815 case INTEL_SIP_SMC_REG_UPDATE: 816 status = intel_secure_reg_update(x1, (uint32_t)x2, 817 (uint32_t)x3, &retval); 818 SMC_RET3(handle, status, retval, x1); 819 820 case INTEL_SIP_SMC_RSU_STATUS: 821 status = intel_rsu_status(rsu_respbuf, 822 ARRAY_SIZE(rsu_respbuf)); 823 if (status) { 824 SMC_RET1(handle, status); 825 } else { 826 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 827 rsu_respbuf[2], rsu_respbuf[3]); 828 } 829 830 case INTEL_SIP_SMC_RSU_UPDATE: 831 status = intel_rsu_update(x1); 832 SMC_RET1(handle, status); 833 834 case INTEL_SIP_SMC_RSU_NOTIFY: 835 status = intel_rsu_notify(x1); 836 SMC_RET1(handle, status); 837 838 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 839 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 840 ARRAY_SIZE(rsu_respbuf), &retval); 841 if (status) { 842 SMC_RET1(handle, status); 843 } else { 844 SMC_RET2(handle, status, retval); 845 } 846 847 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 848 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 849 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 850 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 851 852 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 853 status = intel_rsu_copy_dcmf_version(x1, x2); 854 SMC_RET1(handle, status); 855 856 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 857 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 858 ((uint64_t)rsu_dcmf_stat[3] << 48) | 859 ((uint64_t)rsu_dcmf_stat[2] << 32) | 860 ((uint64_t)rsu_dcmf_stat[1] << 16) | 861 rsu_dcmf_stat[0]); 862 863 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 864 status = intel_rsu_copy_dcmf_status(x1); 865 SMC_RET1(handle, status); 866 867 case INTEL_SIP_SMC_RSU_MAX_RETRY: 868 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 869 870 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 871 rsu_max_retry = x1; 872 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 873 874 case INTEL_SIP_SMC_ECC_DBE: 875 status = intel_ecc_dbe_notification(x1); 876 SMC_RET1(handle, status); 877 878 case INTEL_SIP_SMC_SERVICE_COMPLETED: 879 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 880 &len_in_resp, &mbox_error); 881 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 882 883 case INTEL_SIP_SMC_FIRMWARE_VERSION: 884 status = intel_smc_fw_version(&retval); 885 SMC_RET2(handle, status, retval); 886 887 case INTEL_SIP_SMC_MBOX_SEND_CMD: 888 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 889 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 890 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 891 &mbox_status, &len_in_resp); 892 SMC_RET3(handle, status, mbox_status, len_in_resp); 893 894 case INTEL_SIP_SMC_GET_USERCODE: 895 status = intel_smc_get_usercode(&retval); 896 SMC_RET2(handle, status, retval); 897 898 case INTEL_SIP_SMC_FCS_CRYPTION: 899 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 900 901 if (x1 == FCS_MODE_DECRYPT) { 902 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 903 } else if (x1 == FCS_MODE_ENCRYPT) { 904 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 905 } else { 906 status = INTEL_SIP_SMC_STATUS_REJECTED; 907 } 908 909 SMC_RET3(handle, status, x4, x5); 910 911 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 912 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 913 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 914 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 915 916 if (x3 == FCS_MODE_DECRYPT) { 917 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 918 (uint32_t *) &x7, &mbox_error); 919 } else if (x3 == FCS_MODE_ENCRYPT) { 920 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 921 (uint32_t *) &x7, &mbox_error); 922 } else { 923 status = INTEL_SIP_SMC_STATUS_REJECTED; 924 } 925 926 SMC_RET4(handle, status, mbox_error, x6, x7); 927 928 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 929 status = intel_fcs_random_number_gen(x1, &retval64, 930 &mbox_error); 931 SMC_RET4(handle, status, mbox_error, x1, retval64); 932 933 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 934 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 935 &send_id); 936 SMC_RET1(handle, status); 937 938 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 939 status = intel_fcs_send_cert(x1, x2, &send_id); 940 SMC_RET1(handle, status); 941 942 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 943 status = intel_fcs_get_provision_data(&send_id); 944 SMC_RET1(handle, status); 945 946 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 947 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 948 &mbox_error); 949 SMC_RET2(handle, status, mbox_error); 950 951 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 952 status = intel_hps_set_bridges(x1, x2); 953 SMC_RET1(handle, status); 954 955 case INTEL_SIP_SMC_HWMON_READTEMP: 956 status = intel_hwmon_readtemp(x1, &retval); 957 SMC_RET2(handle, status, retval); 958 959 case INTEL_SIP_SMC_HWMON_READVOLT: 960 status = intel_hwmon_readvolt(x1, &retval); 961 SMC_RET2(handle, status, retval); 962 963 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 964 status = intel_fcs_sigma_teardown(x1, &mbox_error); 965 SMC_RET2(handle, status, mbox_error); 966 967 case INTEL_SIP_SMC_FCS_CHIP_ID: 968 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 969 SMC_RET4(handle, status, mbox_error, retval, retval2); 970 971 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 972 status = intel_fcs_attestation_subkey(x1, x2, x3, 973 (uint32_t *) &x4, &mbox_error); 974 SMC_RET4(handle, status, mbox_error, x3, x4); 975 976 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 977 status = intel_fcs_get_measurement(x1, x2, x3, 978 (uint32_t *) &x4, &mbox_error); 979 SMC_RET4(handle, status, mbox_error, x3, x4); 980 981 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 982 status = intel_fcs_get_attestation_cert(x1, x2, 983 (uint32_t *) &x3, &mbox_error); 984 SMC_RET4(handle, status, mbox_error, x2, x3); 985 986 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 987 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 988 SMC_RET2(handle, status, mbox_error); 989 990 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 991 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 992 SMC_RET3(handle, status, mbox_error, retval); 993 994 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 995 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 996 SMC_RET2(handle, status, mbox_error); 997 998 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 999 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1000 SMC_RET1(handle, status); 1001 1002 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1003 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1004 (uint32_t *) &x4, &mbox_error); 1005 SMC_RET4(handle, status, mbox_error, x3, x4); 1006 1007 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1008 status = intel_fcs_remove_crypto_service_key(x1, x2, 1009 &mbox_error); 1010 SMC_RET2(handle, status, mbox_error); 1011 1012 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1013 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1014 (uint32_t *) &x4, &mbox_error); 1015 SMC_RET4(handle, status, mbox_error, x3, x4); 1016 1017 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1018 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1019 status = intel_fcs_get_digest_init(x1, x2, x3, 1020 x4, x5, &mbox_error); 1021 SMC_RET2(handle, status, mbox_error); 1022 1023 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1024 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1025 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1026 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1027 x4, x5, (uint32_t *) &x6, false, 1028 &mbox_error); 1029 SMC_RET4(handle, status, mbox_error, x5, x6); 1030 1031 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1032 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1033 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1034 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1035 x4, x5, (uint32_t *) &x6, true, 1036 &mbox_error); 1037 SMC_RET4(handle, status, mbox_error, x5, x6); 1038 1039 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1040 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1041 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1042 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1043 x4, x5, (uint32_t *) &x6, false, 1044 &mbox_error, &send_id); 1045 SMC_RET4(handle, status, mbox_error, x5, x6); 1046 1047 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1048 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1049 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1050 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1051 x4, x5, (uint32_t *) &x6, true, 1052 &mbox_error, &send_id); 1053 SMC_RET4(handle, status, mbox_error, x5, x6); 1054 1055 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1056 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1057 status = intel_fcs_mac_verify_init(x1, x2, x3, 1058 x4, x5, &mbox_error); 1059 SMC_RET2(handle, status, mbox_error); 1060 1061 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1062 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1063 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1064 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1065 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1066 x4, x5, (uint32_t *) &x6, x7, 1067 false, &mbox_error); 1068 SMC_RET4(handle, status, mbox_error, x5, x6); 1069 1070 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1071 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1072 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1073 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1074 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1075 x4, x5, (uint32_t *) &x6, x7, 1076 true, &mbox_error); 1077 SMC_RET4(handle, status, mbox_error, x5, x6); 1078 1079 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1080 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1081 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1082 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1083 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1084 x4, x5, (uint32_t *) &x6, x7, 1085 false, &mbox_error, &send_id); 1086 SMC_RET4(handle, status, mbox_error, x5, x6); 1087 1088 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1089 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1090 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1091 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1092 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1093 x4, x5, (uint32_t *) &x6, x7, 1094 true, &mbox_error, &send_id); 1095 SMC_RET4(handle, status, mbox_error, x5, x6); 1096 1097 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1098 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1099 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1100 x4, x5, &mbox_error); 1101 SMC_RET2(handle, status, mbox_error); 1102 1103 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1105 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1106 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1107 x3, x4, x5, (uint32_t *) &x6, false, 1108 &mbox_error); 1109 SMC_RET4(handle, status, mbox_error, x5, x6); 1110 1111 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1112 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1113 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1114 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1115 x3, x4, x5, (uint32_t *) &x6, true, 1116 &mbox_error); 1117 SMC_RET4(handle, status, mbox_error, x5, x6); 1118 1119 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1120 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1121 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1122 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1123 x2, x3, x4, x5, (uint32_t *) &x6, false, 1124 &mbox_error, &send_id); 1125 SMC_RET4(handle, status, mbox_error, x5, x6); 1126 1127 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1128 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1129 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1130 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1131 x2, x3, x4, x5, (uint32_t *) &x6, true, 1132 &mbox_error, &send_id); 1133 SMC_RET4(handle, status, mbox_error, x5, x6); 1134 1135 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1136 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1137 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1138 x4, x5, &mbox_error); 1139 SMC_RET2(handle, status, mbox_error); 1140 1141 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1142 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1143 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1144 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1145 x4, x5, (uint32_t *) &x6, &mbox_error); 1146 SMC_RET4(handle, status, mbox_error, x5, x6); 1147 1148 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1149 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1150 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1151 x4, x5, &mbox_error); 1152 SMC_RET2(handle, status, mbox_error); 1153 1154 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1155 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1156 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1157 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1158 x4, x5, (uint32_t *) &x6, &mbox_error); 1159 SMC_RET4(handle, status, mbox_error, x5, x6); 1160 1161 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1162 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1163 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1164 x4, x5, &mbox_error); 1165 SMC_RET2(handle, status, mbox_error); 1166 1167 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1168 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1169 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1170 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1171 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1172 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1173 x7, false, &mbox_error); 1174 SMC_RET4(handle, status, mbox_error, x5, x6); 1175 1176 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1177 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1178 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1179 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1180 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1181 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1182 x7, false, &mbox_error, &send_id); 1183 SMC_RET4(handle, status, mbox_error, x5, x6); 1184 1185 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1186 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1187 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1188 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1189 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1190 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1191 x7, true, &mbox_error, &send_id); 1192 SMC_RET4(handle, status, mbox_error, x5, x6); 1193 1194 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1195 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1196 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1197 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1198 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1199 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1200 x7, true, &mbox_error); 1201 SMC_RET4(handle, status, mbox_error, x5, x6); 1202 1203 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1204 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1205 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1206 x4, x5, &mbox_error); 1207 SMC_RET2(handle, status, mbox_error); 1208 1209 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1210 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1211 (uint32_t *) &x4, &mbox_error); 1212 SMC_RET4(handle, status, mbox_error, x3, x4); 1213 1214 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1215 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1216 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1217 x4, x5, &mbox_error); 1218 SMC_RET2(handle, status, mbox_error); 1219 1220 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1221 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1222 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1223 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1224 x4, x5, (uint32_t *) &x6, &mbox_error); 1225 SMC_RET4(handle, status, mbox_error, x5, x6); 1226 1227 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1228 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1229 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1230 &mbox_error); 1231 SMC_RET2(handle, status, mbox_error); 1232 1233 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1234 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1235 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1236 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1237 x5, x6, false, &send_id); 1238 SMC_RET1(handle, status); 1239 1240 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1241 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1242 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1243 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1244 x5, x6, true, &send_id); 1245 SMC_RET1(handle, status); 1246 1247 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1248 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1249 &mbox_error); 1250 SMC_RET4(handle, status, mbox_error, x1, retval64); 1251 1252 case INTEL_SIP_SMC_SVC_VERSION: 1253 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1254 SIP_SVC_VERSION_MAJOR, 1255 SIP_SVC_VERSION_MINOR); 1256 1257 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1258 status = intel_sdm_seu_err_read(seu_respbuf, 1259 ARRAY_SIZE(seu_respbuf)); 1260 if (status) { 1261 SMC_RET1(handle, status); 1262 } else { 1263 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1264 } 1265 1266 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1267 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1268 SMC_RET1(handle, status); 1269 1270 default: 1271 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1272 cookie, handle, flags); 1273 } 1274 } 1275 1276 uintptr_t sip_smc_handler(uint32_t smc_fid, 1277 u_register_t x1, 1278 u_register_t x2, 1279 u_register_t x3, 1280 u_register_t x4, 1281 void *cookie, 1282 void *handle, 1283 u_register_t flags) 1284 { 1285 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1286 1287 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1288 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1289 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1290 cookie, handle, flags); 1291 } else { 1292 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1293 cookie, handle, flags); 1294 } 1295 } 1296 1297 DECLARE_RT_SVC( 1298 socfpga_sip_svc, 1299 OEN_SIP_START, 1300 OEN_SIP_END, 1301 SMC_TYPE_FAST, 1302 NULL, 1303 sip_smc_handler 1304 ); 1305 1306 DECLARE_RT_SVC( 1307 socfpga_sip_svc_std, 1308 OEN_SIP_START, 1309 OEN_SIP_END, 1310 SMC_TYPE_YIELD, 1311 NULL, 1312 sip_smc_handler 1313 ); 1314