1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 233 intel_smmu_hps_remapper_init(0U); 234 #endif 235 236 mailbox_clear_response(); 237 238 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 239 CMD_CASUAL, NULL, NULL); 240 241 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 242 CMD_CASUAL, response, &resp_len); 243 244 if (status < 0) { 245 bridge_disable = false; 246 request_type = NO_REQUEST; 247 return INTEL_SIP_SMC_STATUS_ERROR; 248 } 249 250 max_blocks = response[0]; 251 bytes_per_block = response[1]; 252 253 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 254 fpga_config_buffers[i].size = 0; 255 fpga_config_buffers[i].size_written = 0; 256 fpga_config_buffers[i].addr = 0; 257 fpga_config_buffers[i].write_requested = 0; 258 fpga_config_buffers[i].block_number = 0; 259 fpga_config_buffers[i].subblocks_sent = 0; 260 } 261 262 blocks_submitted = 0; 263 current_block = 0; 264 read_block = 0; 265 current_buffer = 0; 266 267 /* Disable bridge on full reconfiguration */ 268 if (bridge_disable) { 269 socfpga_bridges_disable(~0); 270 } 271 272 return INTEL_SIP_SMC_STATUS_OK; 273 } 274 275 static bool is_fpga_config_buffer_full(void) 276 { 277 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 278 if (!fpga_config_buffers[i].write_requested) { 279 return false; 280 } 281 } 282 return true; 283 } 284 285 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 286 { 287 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 288 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 289 290 if (!addr && !size) { 291 return true; 292 } 293 if (size > (UINT64_MAX - addr)) { 294 return false; 295 } 296 if (addr < BL31_LIMIT) { 297 return false; 298 } 299 if (dram_region_end > dram_max_sz) { 300 return false; 301 } 302 303 return true; 304 } 305 306 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 307 { 308 int i; 309 310 intel_fpga_sdm_write_all(); 311 312 if (!is_address_in_ddr_range(mem, size) || 313 is_fpga_config_buffer_full()) { 314 return INTEL_SIP_SMC_STATUS_REJECTED; 315 } 316 317 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 318 intel_smmu_hps_remapper_init(&mem); 319 #endif 320 321 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 322 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 323 324 if (!fpga_config_buffers[j].write_requested) { 325 fpga_config_buffers[j].addr = mem; 326 fpga_config_buffers[j].size = size; 327 fpga_config_buffers[j].size_written = 0; 328 fpga_config_buffers[j].write_requested = 1; 329 fpga_config_buffers[j].block_number = 330 blocks_submitted++; 331 fpga_config_buffers[j].subblocks_sent = 0; 332 break; 333 } 334 } 335 336 if (is_fpga_config_buffer_full()) { 337 return INTEL_SIP_SMC_STATUS_BUSY; 338 } 339 340 return INTEL_SIP_SMC_STATUS_OK; 341 } 342 343 static int is_out_of_sec_range(uint64_t reg_addr) 344 { 345 #if DEBUG 346 return 0; 347 #endif 348 349 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 350 switch (reg_addr) { 351 case(0xF8011100): /* ECCCTRL1 */ 352 case(0xF8011104): /* ECCCTRL2 */ 353 case(0xF8011110): /* ERRINTEN */ 354 case(0xF8011114): /* ERRINTENS */ 355 case(0xF8011118): /* ERRINTENR */ 356 case(0xF801111C): /* INTMODE */ 357 case(0xF8011120): /* INTSTAT */ 358 case(0xF8011124): /* DIAGINTTEST */ 359 case(0xF801112C): /* DERRADDRA */ 360 case(0xFA000000): /* SMMU SCR0 */ 361 case(0xFA000004): /* SMMU SCR1 */ 362 case(0xFA000400): /* SMMU NSCR0 */ 363 case(0xFA004000): /* SMMU SSD0_REG */ 364 case(0xFA000820): /* SMMU SMR8 */ 365 case(0xFA000c20): /* SMMU SCR8 */ 366 case(0xFA028000): /* SMMU CB8_SCTRL */ 367 case(0xFA001020): /* SMMU CBAR8 */ 368 case(0xFA028030): /* SMMU TCR_LPAE */ 369 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 370 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 371 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 372 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 373 case(0xFA028010): /* SMMU_CB8)TCR2 */ 374 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 375 case(0xFA001820): /* SMMU_CBA2R8 */ 376 case(0xFA000074): /* SMMU_STLBGSTATUS */ 377 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 378 case(0xFA000060): /* SMMU_STLBIALL */ 379 case(0xFA000070): /* SMMU_STLBGSYNC */ 380 case(0xFA028618): /* CB8_TLBALL */ 381 case(0xFA0287F0): /* CB8_TLBSYNC */ 382 case(0xFFD12028): /* SDMMCGRP_CTRL */ 383 case(0xFFD12044): /* EMAC0 */ 384 case(0xFFD12048): /* EMAC1 */ 385 case(0xFFD1204C): /* EMAC2 */ 386 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 387 case(0xFFD12094): /* ECC_INT_MASK_SET */ 388 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 389 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 390 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 391 case(0xFFD120C0): /* NOC_TIMEOUT */ 392 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 393 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 394 case(0xFFD120D0): /* NOC_IDLEACK */ 395 case(0xFFD120D4): /* NOC_IDLESTATUS */ 396 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 397 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 398 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 399 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 400 return 0; 401 #else 402 switch (reg_addr) { 403 404 case(0xF8011104): /* ECCCTRL2 */ 405 case(0xFFD12028): /* SDMMCGRP_CTRL */ 406 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 407 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 408 case(0xFFD120D0): /* NOC_IDLEACK */ 409 410 411 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 412 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 413 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 414 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 415 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 416 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 417 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 418 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 419 420 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 421 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 422 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 423 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 424 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 425 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 426 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 427 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 428 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 429 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 430 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 431 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 432 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 433 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 434 return 0; 435 #endif 436 default: 437 break; 438 } 439 440 return -1; 441 } 442 443 /* Secure register access */ 444 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 445 { 446 if (is_out_of_sec_range(reg_addr)) { 447 return INTEL_SIP_SMC_STATUS_ERROR; 448 } 449 450 *retval = mmio_read_32(reg_addr); 451 452 return INTEL_SIP_SMC_STATUS_OK; 453 } 454 455 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 456 uint32_t *retval) 457 { 458 if (is_out_of_sec_range(reg_addr)) { 459 return INTEL_SIP_SMC_STATUS_ERROR; 460 } 461 462 mmio_write_32(reg_addr, val); 463 464 return intel_secure_reg_read(reg_addr, retval); 465 } 466 467 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 468 uint32_t val, uint32_t *retval) 469 { 470 if (!intel_secure_reg_read(reg_addr, retval)) { 471 *retval &= ~mask; 472 *retval |= val & mask; 473 return intel_secure_reg_write(reg_addr, *retval, retval); 474 } 475 476 return INTEL_SIP_SMC_STATUS_ERROR; 477 } 478 479 /* Intel Remote System Update (RSU) services */ 480 uint64_t intel_rsu_update_address; 481 482 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 483 { 484 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 485 return INTEL_SIP_SMC_RSU_ERROR; 486 } 487 488 return INTEL_SIP_SMC_STATUS_OK; 489 } 490 491 uint32_t intel_rsu_update(uint64_t update_address) 492 { 493 if (update_address > SIZE_MAX) { 494 return INTEL_SIP_SMC_STATUS_REJECTED; 495 } 496 497 intel_rsu_update_address = update_address; 498 return INTEL_SIP_SMC_STATUS_OK; 499 } 500 501 static uint32_t intel_rsu_notify(uint32_t execution_stage) 502 { 503 if (mailbox_hps_stage_notify(execution_stage) < 0) { 504 return INTEL_SIP_SMC_RSU_ERROR; 505 } 506 507 return INTEL_SIP_SMC_STATUS_OK; 508 } 509 510 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 511 uint32_t *ret_stat) 512 { 513 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 514 return INTEL_SIP_SMC_RSU_ERROR; 515 } 516 517 *ret_stat = respbuf[8]; 518 return INTEL_SIP_SMC_STATUS_OK; 519 } 520 521 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 522 uint64_t dcmf_ver_3_2) 523 { 524 rsu_dcmf_ver[0] = dcmf_ver_1_0; 525 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 526 rsu_dcmf_ver[2] = dcmf_ver_3_2; 527 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 528 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 533 { 534 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 535 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 536 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 537 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 538 539 return INTEL_SIP_SMC_STATUS_OK; 540 } 541 542 /* Intel HWMON services */ 543 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 544 { 545 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 546 return INTEL_SIP_SMC_STATUS_ERROR; 547 } 548 549 return INTEL_SIP_SMC_STATUS_OK; 550 } 551 552 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 553 { 554 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 555 return INTEL_SIP_SMC_STATUS_ERROR; 556 } 557 558 return INTEL_SIP_SMC_STATUS_OK; 559 } 560 561 /* Mailbox services */ 562 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 563 { 564 int status; 565 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 566 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 567 568 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 569 CMD_CASUAL, resp_data, &resp_len); 570 571 if (status < 0) { 572 return INTEL_SIP_SMC_STATUS_ERROR; 573 } 574 575 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 576 return INTEL_SIP_SMC_STATUS_ERROR; 577 } 578 579 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 580 581 return INTEL_SIP_SMC_STATUS_OK; 582 } 583 584 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 585 unsigned int len, uint32_t urgent, uint64_t response, 586 unsigned int resp_len, int *mbox_status, 587 unsigned int *len_in_resp) 588 { 589 *len_in_resp = 0; 590 *mbox_status = GENERIC_RESPONSE_ERROR; 591 592 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 593 return INTEL_SIP_SMC_STATUS_REJECTED; 594 } 595 596 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 597 (uint32_t *) response, &resp_len); 598 599 if (status < 0) { 600 *mbox_status = -status; 601 return INTEL_SIP_SMC_STATUS_ERROR; 602 } 603 604 *mbox_status = 0; 605 *len_in_resp = resp_len; 606 607 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 608 609 return INTEL_SIP_SMC_STATUS_OK; 610 } 611 612 static int intel_smc_get_usercode(uint32_t *user_code) 613 { 614 int status; 615 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 616 617 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 618 0U, CMD_CASUAL, user_code, &resp_len); 619 620 if (status < 0) { 621 return INTEL_SIP_SMC_STATUS_ERROR; 622 } 623 624 return INTEL_SIP_SMC_STATUS_OK; 625 } 626 627 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 628 uint32_t mode, uint32_t *job_id, 629 uint32_t *ret_size, uint32_t *mbox_error) 630 { 631 int status = 0; 632 uint32_t resp_len = size / MBOX_WORD_BYTE; 633 634 if (resp_len > MBOX_DATA_MAX_LEN) { 635 return INTEL_SIP_SMC_STATUS_REJECTED; 636 } 637 638 if (!is_address_in_ddr_range(addr, size)) { 639 return INTEL_SIP_SMC_STATUS_REJECTED; 640 } 641 642 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 643 status = mailbox_read_response_async(job_id, 644 NULL, (uint32_t *) addr, &resp_len, 0); 645 } else { 646 status = mailbox_read_response(job_id, 647 (uint32_t *) addr, &resp_len); 648 649 if (status == MBOX_NO_RESPONSE) { 650 status = MBOX_BUSY; 651 } 652 } 653 654 if (status == MBOX_NO_RESPONSE) { 655 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 656 } 657 658 if (status == MBOX_BUSY) { 659 return INTEL_SIP_SMC_STATUS_BUSY; 660 } 661 662 *ret_size = resp_len * MBOX_WORD_BYTE; 663 flush_dcache_range(addr, *ret_size); 664 665 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 666 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 667 *mbox_error = -status; 668 } else if (status != MBOX_RET_OK) { 669 *mbox_error = -status; 670 return INTEL_SIP_SMC_STATUS_ERROR; 671 } 672 673 return INTEL_SIP_SMC_STATUS_OK; 674 } 675 676 /* Miscellaneous HPS services */ 677 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 678 { 679 int status = 0; 680 681 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 682 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 683 status = socfpga_bridges_enable((uint32_t)mask); 684 } else { 685 status = socfpga_bridges_enable(~0); 686 } 687 } else { 688 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 689 status = socfpga_bridges_disable((uint32_t)mask); 690 } else { 691 status = socfpga_bridges_disable(~0); 692 } 693 } 694 695 if (status < 0) { 696 return INTEL_SIP_SMC_STATUS_ERROR; 697 } 698 699 return INTEL_SIP_SMC_STATUS_OK; 700 } 701 702 /* SDM SEU Error services */ 703 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 704 { 705 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 706 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 707 } 708 709 return INTEL_SIP_SMC_STATUS_OK; 710 } 711 712 /* SDM SAFE SEU Error inject services */ 713 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 714 { 715 if (mailbox_safe_inject_seu_err(command, len) < 0) { 716 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 717 } 718 719 return INTEL_SIP_SMC_STATUS_OK; 720 } 721 722 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 723 /* SMMU HPS Remapper */ 724 void intel_smmu_hps_remapper_init(uint64_t *mem) 725 { 726 /* Read out Bit 1 value */ 727 uint32_t remap = (mmio_read_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_POR_1)) & 0x02); 728 729 if (remap == 0x00) { 730 /* Update DRAM Base address for SDM SMMU */ 731 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_ARADDR_REMAP), DRAM_BASE); 732 mmio_write_32(SOCFPGA_SYSMGR(SDM_BE_AWADDR_REMAP), DRAM_BASE); 733 *mem = *mem - DRAM_BASE; 734 } else { 735 *mem = *mem - DRAM_BASE; 736 } 737 } 738 #endif 739 740 /* 741 * This function is responsible for handling all SiP calls from the NS world 742 */ 743 744 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 745 u_register_t x1, 746 u_register_t x2, 747 u_register_t x3, 748 u_register_t x4, 749 void *cookie, 750 void *handle, 751 u_register_t flags) 752 { 753 uint32_t retval = 0, completed_addr[3]; 754 uint32_t retval2 = 0; 755 uint32_t mbox_error = 0; 756 uint64_t retval64, rsu_respbuf[9]; 757 uint32_t seu_respbuf[3]; 758 int status = INTEL_SIP_SMC_STATUS_OK; 759 int mbox_status; 760 unsigned int len_in_resp; 761 u_register_t x5, x6, x7; 762 763 switch (smc_fid) { 764 case SIP_SVC_UID: 765 /* Return UID to the caller */ 766 SMC_UUID_RET(handle, intl_svc_uid); 767 768 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 769 status = intel_mailbox_fpga_config_isdone(); 770 SMC_RET4(handle, status, 0, 0, 0); 771 772 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 773 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 774 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 775 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 776 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 777 778 case INTEL_SIP_SMC_FPGA_CONFIG_START: 779 status = intel_fpga_config_start(x1); 780 SMC_RET4(handle, status, 0, 0, 0); 781 782 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 783 status = intel_fpga_config_write(x1, x2); 784 SMC_RET4(handle, status, 0, 0, 0); 785 786 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 787 status = intel_fpga_config_completed_write(completed_addr, 788 &retval, &rcv_id); 789 switch (retval) { 790 case 1: 791 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 792 completed_addr[0], 0, 0); 793 794 case 2: 795 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 796 completed_addr[0], 797 completed_addr[1], 0); 798 799 case 3: 800 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 801 completed_addr[0], 802 completed_addr[1], 803 completed_addr[2]); 804 805 case 0: 806 SMC_RET4(handle, status, 0, 0, 0); 807 808 default: 809 mailbox_clear_response(); 810 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 811 } 812 813 case INTEL_SIP_SMC_REG_READ: 814 status = intel_secure_reg_read(x1, &retval); 815 SMC_RET3(handle, status, retval, x1); 816 817 case INTEL_SIP_SMC_REG_WRITE: 818 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 819 SMC_RET3(handle, status, retval, x1); 820 821 case INTEL_SIP_SMC_REG_UPDATE: 822 status = intel_secure_reg_update(x1, (uint32_t)x2, 823 (uint32_t)x3, &retval); 824 SMC_RET3(handle, status, retval, x1); 825 826 case INTEL_SIP_SMC_RSU_STATUS: 827 status = intel_rsu_status(rsu_respbuf, 828 ARRAY_SIZE(rsu_respbuf)); 829 if (status) { 830 SMC_RET1(handle, status); 831 } else { 832 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 833 rsu_respbuf[2], rsu_respbuf[3]); 834 } 835 836 case INTEL_SIP_SMC_RSU_UPDATE: 837 status = intel_rsu_update(x1); 838 SMC_RET1(handle, status); 839 840 case INTEL_SIP_SMC_RSU_NOTIFY: 841 status = intel_rsu_notify(x1); 842 SMC_RET1(handle, status); 843 844 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 845 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 846 ARRAY_SIZE(rsu_respbuf), &retval); 847 if (status) { 848 SMC_RET1(handle, status); 849 } else { 850 SMC_RET2(handle, status, retval); 851 } 852 853 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 854 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 855 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 856 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 857 858 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 859 status = intel_rsu_copy_dcmf_version(x1, x2); 860 SMC_RET1(handle, status); 861 862 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 863 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 864 ((uint64_t)rsu_dcmf_stat[3] << 48) | 865 ((uint64_t)rsu_dcmf_stat[2] << 32) | 866 ((uint64_t)rsu_dcmf_stat[1] << 16) | 867 rsu_dcmf_stat[0]); 868 869 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 870 status = intel_rsu_copy_dcmf_status(x1); 871 SMC_RET1(handle, status); 872 873 case INTEL_SIP_SMC_RSU_MAX_RETRY: 874 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 875 876 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 877 rsu_max_retry = x1; 878 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 879 880 case INTEL_SIP_SMC_ECC_DBE: 881 status = intel_ecc_dbe_notification(x1); 882 SMC_RET1(handle, status); 883 884 case INTEL_SIP_SMC_SERVICE_COMPLETED: 885 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 886 &len_in_resp, &mbox_error); 887 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 888 889 case INTEL_SIP_SMC_FIRMWARE_VERSION: 890 status = intel_smc_fw_version(&retval); 891 SMC_RET2(handle, status, retval); 892 893 case INTEL_SIP_SMC_MBOX_SEND_CMD: 894 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 895 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 896 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 897 &mbox_status, &len_in_resp); 898 SMC_RET3(handle, status, mbox_status, len_in_resp); 899 900 case INTEL_SIP_SMC_GET_USERCODE: 901 status = intel_smc_get_usercode(&retval); 902 SMC_RET2(handle, status, retval); 903 904 case INTEL_SIP_SMC_FCS_CRYPTION: 905 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 906 907 if (x1 == FCS_MODE_DECRYPT) { 908 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 909 } else if (x1 == FCS_MODE_ENCRYPT) { 910 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 911 } else { 912 status = INTEL_SIP_SMC_STATUS_REJECTED; 913 } 914 915 SMC_RET3(handle, status, x4, x5); 916 917 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 918 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 919 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 920 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 921 922 if (x3 == FCS_MODE_DECRYPT) { 923 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 924 (uint32_t *) &x7, &mbox_error); 925 } else if (x3 == FCS_MODE_ENCRYPT) { 926 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 927 (uint32_t *) &x7, &mbox_error); 928 } else { 929 status = INTEL_SIP_SMC_STATUS_REJECTED; 930 } 931 932 SMC_RET4(handle, status, mbox_error, x6, x7); 933 934 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 935 status = intel_fcs_random_number_gen(x1, &retval64, 936 &mbox_error); 937 SMC_RET4(handle, status, mbox_error, x1, retval64); 938 939 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 940 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 941 &send_id); 942 SMC_RET1(handle, status); 943 944 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 945 status = intel_fcs_send_cert(x1, x2, &send_id); 946 SMC_RET1(handle, status); 947 948 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 949 status = intel_fcs_get_provision_data(&send_id); 950 SMC_RET1(handle, status); 951 952 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 953 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 954 &mbox_error); 955 SMC_RET2(handle, status, mbox_error); 956 957 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 958 status = intel_hps_set_bridges(x1, x2); 959 SMC_RET1(handle, status); 960 961 case INTEL_SIP_SMC_HWMON_READTEMP: 962 status = intel_hwmon_readtemp(x1, &retval); 963 SMC_RET2(handle, status, retval); 964 965 case INTEL_SIP_SMC_HWMON_READVOLT: 966 status = intel_hwmon_readvolt(x1, &retval); 967 SMC_RET2(handle, status, retval); 968 969 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 970 status = intel_fcs_sigma_teardown(x1, &mbox_error); 971 SMC_RET2(handle, status, mbox_error); 972 973 case INTEL_SIP_SMC_FCS_CHIP_ID: 974 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 975 SMC_RET4(handle, status, mbox_error, retval, retval2); 976 977 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 978 status = intel_fcs_attestation_subkey(x1, x2, x3, 979 (uint32_t *) &x4, &mbox_error); 980 SMC_RET4(handle, status, mbox_error, x3, x4); 981 982 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 983 status = intel_fcs_get_measurement(x1, x2, x3, 984 (uint32_t *) &x4, &mbox_error); 985 SMC_RET4(handle, status, mbox_error, x3, x4); 986 987 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 988 status = intel_fcs_get_attestation_cert(x1, x2, 989 (uint32_t *) &x3, &mbox_error); 990 SMC_RET4(handle, status, mbox_error, x2, x3); 991 992 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 993 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 994 SMC_RET2(handle, status, mbox_error); 995 996 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 997 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 998 SMC_RET3(handle, status, mbox_error, retval); 999 1000 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 1001 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 1002 SMC_RET2(handle, status, mbox_error); 1003 1004 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 1005 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 1006 SMC_RET1(handle, status); 1007 1008 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1009 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1010 (uint32_t *) &x4, &mbox_error); 1011 SMC_RET4(handle, status, mbox_error, x3, x4); 1012 1013 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1014 status = intel_fcs_remove_crypto_service_key(x1, x2, 1015 &mbox_error); 1016 SMC_RET2(handle, status, mbox_error); 1017 1018 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1019 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1020 (uint32_t *) &x4, &mbox_error); 1021 SMC_RET4(handle, status, mbox_error, x3, x4); 1022 1023 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1024 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1025 status = intel_fcs_get_digest_init(x1, x2, x3, 1026 x4, x5, &mbox_error); 1027 SMC_RET2(handle, status, mbox_error); 1028 1029 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1030 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1031 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1032 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1033 x4, x5, (uint32_t *) &x6, false, 1034 &mbox_error); 1035 SMC_RET4(handle, status, mbox_error, x5, x6); 1036 1037 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1038 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1039 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1040 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1041 x4, x5, (uint32_t *) &x6, true, 1042 &mbox_error); 1043 SMC_RET4(handle, status, mbox_error, x5, x6); 1044 1045 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1046 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1047 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1048 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1049 x4, x5, (uint32_t *) &x6, false, 1050 &mbox_error, &send_id); 1051 SMC_RET4(handle, status, mbox_error, x5, x6); 1052 1053 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1054 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1055 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1056 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1057 x4, x5, (uint32_t *) &x6, true, 1058 &mbox_error, &send_id); 1059 SMC_RET4(handle, status, mbox_error, x5, x6); 1060 1061 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1062 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1063 status = intel_fcs_mac_verify_init(x1, x2, x3, 1064 x4, x5, &mbox_error); 1065 SMC_RET2(handle, status, mbox_error); 1066 1067 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1068 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1069 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1070 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1071 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1072 x4, x5, (uint32_t *) &x6, x7, 1073 false, &mbox_error); 1074 SMC_RET4(handle, status, mbox_error, x5, x6); 1075 1076 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1077 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1078 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1079 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1080 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1081 x4, x5, (uint32_t *) &x6, x7, 1082 true, &mbox_error); 1083 SMC_RET4(handle, status, mbox_error, x5, x6); 1084 1085 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1086 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1087 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1088 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1089 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1090 x4, x5, (uint32_t *) &x6, x7, 1091 false, &mbox_error, &send_id); 1092 SMC_RET4(handle, status, mbox_error, x5, x6); 1093 1094 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1095 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1096 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1097 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1098 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1099 x4, x5, (uint32_t *) &x6, x7, 1100 true, &mbox_error, &send_id); 1101 SMC_RET4(handle, status, mbox_error, x5, x6); 1102 1103 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1105 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1106 x4, x5, &mbox_error); 1107 SMC_RET2(handle, status, mbox_error); 1108 1109 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1110 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1111 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1112 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1113 x3, x4, x5, (uint32_t *) &x6, false, 1114 &mbox_error); 1115 SMC_RET4(handle, status, mbox_error, x5, x6); 1116 1117 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1118 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1119 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1120 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1121 x3, x4, x5, (uint32_t *) &x6, true, 1122 &mbox_error); 1123 SMC_RET4(handle, status, mbox_error, x5, x6); 1124 1125 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1126 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1127 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1128 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1129 x2, x3, x4, x5, (uint32_t *) &x6, false, 1130 &mbox_error, &send_id); 1131 SMC_RET4(handle, status, mbox_error, x5, x6); 1132 1133 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1134 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1135 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1136 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1137 x2, x3, x4, x5, (uint32_t *) &x6, true, 1138 &mbox_error, &send_id); 1139 SMC_RET4(handle, status, mbox_error, x5, x6); 1140 1141 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1142 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1143 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1144 x4, x5, &mbox_error); 1145 SMC_RET2(handle, status, mbox_error); 1146 1147 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1148 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1149 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1150 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1151 x4, x5, (uint32_t *) &x6, &mbox_error); 1152 SMC_RET4(handle, status, mbox_error, x5, x6); 1153 1154 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1155 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1156 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1157 x4, x5, &mbox_error); 1158 SMC_RET2(handle, status, mbox_error); 1159 1160 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1161 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1162 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1163 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1164 x4, x5, (uint32_t *) &x6, &mbox_error); 1165 SMC_RET4(handle, status, mbox_error, x5, x6); 1166 1167 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1168 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1169 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1170 x4, x5, &mbox_error); 1171 SMC_RET2(handle, status, mbox_error); 1172 1173 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1174 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1175 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1176 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1177 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1178 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1179 x7, false, &mbox_error); 1180 SMC_RET4(handle, status, mbox_error, x5, x6); 1181 1182 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1183 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1184 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1185 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1186 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1187 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1188 x7, false, &mbox_error, &send_id); 1189 SMC_RET4(handle, status, mbox_error, x5, x6); 1190 1191 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1192 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1193 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1194 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1195 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1196 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1197 x7, true, &mbox_error, &send_id); 1198 SMC_RET4(handle, status, mbox_error, x5, x6); 1199 1200 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1201 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1202 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1203 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1204 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1205 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1206 x7, true, &mbox_error); 1207 SMC_RET4(handle, status, mbox_error, x5, x6); 1208 1209 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1210 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1211 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1212 x4, x5, &mbox_error); 1213 SMC_RET2(handle, status, mbox_error); 1214 1215 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1216 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1217 (uint32_t *) &x4, &mbox_error); 1218 SMC_RET4(handle, status, mbox_error, x3, x4); 1219 1220 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1221 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1222 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1223 x4, x5, &mbox_error); 1224 SMC_RET2(handle, status, mbox_error); 1225 1226 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1227 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1228 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1229 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1230 x4, x5, (uint32_t *) &x6, &mbox_error); 1231 SMC_RET4(handle, status, mbox_error, x5, x6); 1232 1233 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1234 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1235 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1236 &mbox_error); 1237 SMC_RET2(handle, status, mbox_error); 1238 1239 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1240 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1241 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1242 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1243 x5, x6, false, &send_id); 1244 SMC_RET1(handle, status); 1245 1246 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1247 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1248 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1249 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1250 x5, x6, true, &send_id); 1251 SMC_RET1(handle, status); 1252 1253 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1254 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1255 &mbox_error); 1256 SMC_RET4(handle, status, mbox_error, x1, retval64); 1257 1258 case INTEL_SIP_SMC_SVC_VERSION: 1259 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1260 SIP_SVC_VERSION_MAJOR, 1261 SIP_SVC_VERSION_MINOR); 1262 1263 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1264 status = intel_sdm_seu_err_read(seu_respbuf, 1265 ARRAY_SIZE(seu_respbuf)); 1266 if (status) { 1267 SMC_RET1(handle, status); 1268 } else { 1269 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1270 } 1271 1272 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1273 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1274 SMC_RET1(handle, status); 1275 1276 default: 1277 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1278 cookie, handle, flags); 1279 } 1280 } 1281 1282 uintptr_t sip_smc_handler(uint32_t smc_fid, 1283 u_register_t x1, 1284 u_register_t x2, 1285 u_register_t x3, 1286 u_register_t x4, 1287 void *cookie, 1288 void *handle, 1289 u_register_t flags) 1290 { 1291 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1292 1293 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1294 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1295 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1296 cookie, handle, flags); 1297 } else { 1298 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1299 cookie, handle, flags); 1300 } 1301 } 1302 1303 DECLARE_RT_SVC( 1304 socfpga_sip_svc, 1305 OEN_SIP_START, 1306 OEN_SIP_END, 1307 SMC_TYPE_FAST, 1308 NULL, 1309 sip_smc_handler 1310 ); 1311 1312 DECLARE_RT_SVC( 1313 socfpga_sip_svc_std, 1314 OEN_SIP_START, 1315 OEN_SIP_END, 1316 SMC_TYPE_YIELD, 1317 NULL, 1318 sip_smc_handler 1319 ); 1320