1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 mailbox_clear_response(); 233 234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 235 CMD_CASUAL, NULL, NULL); 236 237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 238 CMD_CASUAL, response, &resp_len); 239 240 if (status < 0) { 241 bridge_disable = false; 242 request_type = NO_REQUEST; 243 return INTEL_SIP_SMC_STATUS_ERROR; 244 } 245 246 max_blocks = response[0]; 247 bytes_per_block = response[1]; 248 249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 250 fpga_config_buffers[i].size = 0; 251 fpga_config_buffers[i].size_written = 0; 252 fpga_config_buffers[i].addr = 0; 253 fpga_config_buffers[i].write_requested = 0; 254 fpga_config_buffers[i].block_number = 0; 255 fpga_config_buffers[i].subblocks_sent = 0; 256 } 257 258 blocks_submitted = 0; 259 current_block = 0; 260 read_block = 0; 261 current_buffer = 0; 262 263 /* Disable bridge on full reconfiguration */ 264 if (bridge_disable) { 265 socfpga_bridges_disable(~0); 266 } 267 268 return INTEL_SIP_SMC_STATUS_OK; 269 } 270 271 static bool is_fpga_config_buffer_full(void) 272 { 273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 274 if (!fpga_config_buffers[i].write_requested) { 275 return false; 276 } 277 } 278 return true; 279 } 280 281 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 282 { 283 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 284 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 285 286 if (!addr && !size) { 287 return true; 288 } 289 if (size > (UINT64_MAX - addr)) { 290 return false; 291 } 292 if (addr < BL31_LIMIT) { 293 return false; 294 } 295 if (dram_region_end > dram_max_sz) { 296 return false; 297 } 298 299 return true; 300 } 301 302 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 303 { 304 int i; 305 306 intel_fpga_sdm_write_all(); 307 308 if (!is_address_in_ddr_range(mem, size) || 309 is_fpga_config_buffer_full()) { 310 return INTEL_SIP_SMC_STATUS_REJECTED; 311 } 312 313 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 314 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 315 316 if (!fpga_config_buffers[j].write_requested) { 317 fpga_config_buffers[j].addr = mem; 318 fpga_config_buffers[j].size = size; 319 fpga_config_buffers[j].size_written = 0; 320 fpga_config_buffers[j].write_requested = 1; 321 fpga_config_buffers[j].block_number = 322 blocks_submitted++; 323 fpga_config_buffers[j].subblocks_sent = 0; 324 break; 325 } 326 } 327 328 if (is_fpga_config_buffer_full()) { 329 return INTEL_SIP_SMC_STATUS_BUSY; 330 } 331 332 return INTEL_SIP_SMC_STATUS_OK; 333 } 334 335 static int is_out_of_sec_range(uint64_t reg_addr) 336 { 337 #if DEBUG 338 return 0; 339 #endif 340 341 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 342 switch (reg_addr) { 343 case(0xF8011100): /* ECCCTRL1 */ 344 case(0xF8011104): /* ECCCTRL2 */ 345 case(0xF8011110): /* ERRINTEN */ 346 case(0xF8011114): /* ERRINTENS */ 347 case(0xF8011118): /* ERRINTENR */ 348 case(0xF801111C): /* INTMODE */ 349 case(0xF8011120): /* INTSTAT */ 350 case(0xF8011124): /* DIAGINTTEST */ 351 case(0xF801112C): /* DERRADDRA */ 352 case(0xFA000000): /* SMMU SCR0 */ 353 case(0xFA000004): /* SMMU SCR1 */ 354 case(0xFA000400): /* SMMU NSCR0 */ 355 case(0xFA004000): /* SMMU SSD0_REG */ 356 case(0xFA000820): /* SMMU SMR8 */ 357 case(0xFA000c20): /* SMMU SCR8 */ 358 case(0xFA028000): /* SMMU CB8_SCTRL */ 359 case(0xFA001020): /* SMMU CBAR8 */ 360 case(0xFA028030): /* SMMU TCR_LPAE */ 361 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 362 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 363 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 364 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 365 case(0xFA028010): /* SMMU_CB8)TCR2 */ 366 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 367 case(0xFA001820): /* SMMU_CBA2R8 */ 368 case(0xFA000074): /* SMMU_STLBGSTATUS */ 369 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 370 case(0xFA000060): /* SMMU_STLBIALL */ 371 case(0xFA000070): /* SMMU_STLBGSYNC */ 372 case(0xFA028618): /* CB8_TLBALL */ 373 case(0xFA0287F0): /* CB8_TLBSYNC */ 374 case(0xFFD12028): /* SDMMCGRP_CTRL */ 375 case(0xFFD12044): /* EMAC0 */ 376 case(0xFFD12048): /* EMAC1 */ 377 case(0xFFD1204C): /* EMAC2 */ 378 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 379 case(0xFFD12094): /* ECC_INT_MASK_SET */ 380 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 381 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 382 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 383 case(0xFFD120C0): /* NOC_TIMEOUT */ 384 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 385 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 386 case(0xFFD120D0): /* NOC_IDLEACK */ 387 case(0xFFD120D4): /* NOC_IDLESTATUS */ 388 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 389 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 390 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 391 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 392 return 0; 393 #else 394 switch (reg_addr) { 395 396 case(0xF8011104): /* ECCCTRL2 */ 397 case(0xFFD12028): /* SDMMCGRP_CTRL */ 398 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 399 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 400 case(0xFFD120D0): /* NOC_IDLEACK */ 401 402 403 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 404 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 405 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 406 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 407 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 408 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 409 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 410 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 411 412 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 413 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 414 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 415 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 416 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 417 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 418 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 419 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 420 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 421 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 422 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 423 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 424 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 425 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 426 return 0; 427 #endif 428 default: 429 break; 430 } 431 432 return -1; 433 } 434 435 /* Secure register access */ 436 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 437 { 438 if (is_out_of_sec_range(reg_addr)) { 439 return INTEL_SIP_SMC_STATUS_ERROR; 440 } 441 442 *retval = mmio_read_32(reg_addr); 443 444 return INTEL_SIP_SMC_STATUS_OK; 445 } 446 447 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 448 uint32_t *retval) 449 { 450 if (is_out_of_sec_range(reg_addr)) { 451 return INTEL_SIP_SMC_STATUS_ERROR; 452 } 453 454 mmio_write_32(reg_addr, val); 455 456 return intel_secure_reg_read(reg_addr, retval); 457 } 458 459 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 460 uint32_t val, uint32_t *retval) 461 { 462 if (!intel_secure_reg_read(reg_addr, retval)) { 463 *retval &= ~mask; 464 *retval |= val & mask; 465 return intel_secure_reg_write(reg_addr, *retval, retval); 466 } 467 468 return INTEL_SIP_SMC_STATUS_ERROR; 469 } 470 471 /* Intel Remote System Update (RSU) services */ 472 uint64_t intel_rsu_update_address; 473 474 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 475 { 476 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 477 return INTEL_SIP_SMC_RSU_ERROR; 478 } 479 480 return INTEL_SIP_SMC_STATUS_OK; 481 } 482 483 uint32_t intel_rsu_update(uint64_t update_address) 484 { 485 if (update_address > SIZE_MAX) { 486 return INTEL_SIP_SMC_STATUS_REJECTED; 487 } 488 489 intel_rsu_update_address = update_address; 490 return INTEL_SIP_SMC_STATUS_OK; 491 } 492 493 static uint32_t intel_rsu_notify(uint32_t execution_stage) 494 { 495 if (mailbox_hps_stage_notify(execution_stage) < 0) { 496 return INTEL_SIP_SMC_RSU_ERROR; 497 } 498 499 return INTEL_SIP_SMC_STATUS_OK; 500 } 501 502 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 503 uint32_t *ret_stat) 504 { 505 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 506 return INTEL_SIP_SMC_RSU_ERROR; 507 } 508 509 *ret_stat = respbuf[8]; 510 return INTEL_SIP_SMC_STATUS_OK; 511 } 512 513 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 514 uint64_t dcmf_ver_3_2) 515 { 516 rsu_dcmf_ver[0] = dcmf_ver_1_0; 517 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 518 rsu_dcmf_ver[2] = dcmf_ver_3_2; 519 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 520 521 return INTEL_SIP_SMC_STATUS_OK; 522 } 523 524 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 525 { 526 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 527 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 528 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 529 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 530 531 return INTEL_SIP_SMC_STATUS_OK; 532 } 533 534 /* Intel HWMON services */ 535 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 536 { 537 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 538 return INTEL_SIP_SMC_STATUS_ERROR; 539 } 540 541 return INTEL_SIP_SMC_STATUS_OK; 542 } 543 544 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 545 { 546 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 547 return INTEL_SIP_SMC_STATUS_ERROR; 548 } 549 550 return INTEL_SIP_SMC_STATUS_OK; 551 } 552 553 /* Mailbox services */ 554 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 555 { 556 int status; 557 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 558 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 559 560 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 561 CMD_CASUAL, resp_data, &resp_len); 562 563 if (status < 0) { 564 return INTEL_SIP_SMC_STATUS_ERROR; 565 } 566 567 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 568 return INTEL_SIP_SMC_STATUS_ERROR; 569 } 570 571 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 572 573 return INTEL_SIP_SMC_STATUS_OK; 574 } 575 576 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 577 unsigned int len, uint32_t urgent, uint64_t response, 578 unsigned int resp_len, int *mbox_status, 579 unsigned int *len_in_resp) 580 { 581 *len_in_resp = 0; 582 *mbox_status = GENERIC_RESPONSE_ERROR; 583 584 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 585 return INTEL_SIP_SMC_STATUS_REJECTED; 586 } 587 588 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 589 (uint32_t *) response, &resp_len); 590 591 if (status < 0) { 592 *mbox_status = -status; 593 return INTEL_SIP_SMC_STATUS_ERROR; 594 } 595 596 *mbox_status = 0; 597 *len_in_resp = resp_len; 598 599 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 600 601 return INTEL_SIP_SMC_STATUS_OK; 602 } 603 604 static int intel_smc_get_usercode(uint32_t *user_code) 605 { 606 int status; 607 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 608 609 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 610 0U, CMD_CASUAL, user_code, &resp_len); 611 612 if (status < 0) { 613 return INTEL_SIP_SMC_STATUS_ERROR; 614 } 615 616 return INTEL_SIP_SMC_STATUS_OK; 617 } 618 619 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 620 uint32_t mode, uint32_t *job_id, 621 uint32_t *ret_size, uint32_t *mbox_error) 622 { 623 int status = 0; 624 uint32_t resp_len = size / MBOX_WORD_BYTE; 625 626 if (resp_len > MBOX_DATA_MAX_LEN) { 627 return INTEL_SIP_SMC_STATUS_REJECTED; 628 } 629 630 if (!is_address_in_ddr_range(addr, size)) { 631 return INTEL_SIP_SMC_STATUS_REJECTED; 632 } 633 634 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 635 status = mailbox_read_response_async(job_id, 636 NULL, (uint32_t *) addr, &resp_len, 0); 637 } else { 638 status = mailbox_read_response(job_id, 639 (uint32_t *) addr, &resp_len); 640 641 if (status == MBOX_NO_RESPONSE) { 642 status = MBOX_BUSY; 643 } 644 } 645 646 if (status == MBOX_NO_RESPONSE) { 647 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 648 } 649 650 if (status == MBOX_BUSY) { 651 return INTEL_SIP_SMC_STATUS_BUSY; 652 } 653 654 *ret_size = resp_len * MBOX_WORD_BYTE; 655 flush_dcache_range(addr, *ret_size); 656 657 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 658 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 659 *mbox_error = -status; 660 } else if (status != MBOX_RET_OK) { 661 *mbox_error = -status; 662 return INTEL_SIP_SMC_STATUS_ERROR; 663 } 664 665 return INTEL_SIP_SMC_STATUS_OK; 666 } 667 668 /* Miscellaneous HPS services */ 669 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 670 { 671 int status = 0; 672 673 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 674 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 675 status = socfpga_bridges_enable((uint32_t)mask); 676 } else { 677 status = socfpga_bridges_enable(~0); 678 } 679 } else { 680 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 681 status = socfpga_bridges_disable((uint32_t)mask); 682 } else { 683 status = socfpga_bridges_disable(~0); 684 } 685 } 686 687 if (status < 0) { 688 return INTEL_SIP_SMC_STATUS_ERROR; 689 } 690 691 return INTEL_SIP_SMC_STATUS_OK; 692 } 693 694 /* SDM SEU Error services */ 695 static uint32_t intel_sdm_seu_err_read(uint64_t *respbuf, unsigned int respbuf_sz) 696 { 697 if (mailbox_seu_err_status((uint32_t *)respbuf, respbuf_sz) < 0) { 698 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 699 } 700 701 return INTEL_SIP_SMC_STATUS_OK; 702 } 703 704 /* 705 * This function is responsible for handling all SiP calls from the NS world 706 */ 707 708 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 709 u_register_t x1, 710 u_register_t x2, 711 u_register_t x3, 712 u_register_t x4, 713 void *cookie, 714 void *handle, 715 u_register_t flags) 716 { 717 uint32_t retval = 0, completed_addr[3]; 718 uint32_t retval2 = 0; 719 uint32_t mbox_error = 0; 720 uint64_t retval64, rsu_respbuf[9], seu_respbuf[3]; 721 int status = INTEL_SIP_SMC_STATUS_OK; 722 int mbox_status; 723 unsigned int len_in_resp; 724 u_register_t x5, x6, x7; 725 726 switch (smc_fid) { 727 case SIP_SVC_UID: 728 /* Return UID to the caller */ 729 SMC_UUID_RET(handle, intl_svc_uid); 730 731 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 732 status = intel_mailbox_fpga_config_isdone(); 733 SMC_RET4(handle, status, 0, 0, 0); 734 735 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 736 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 737 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 738 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 739 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 740 741 case INTEL_SIP_SMC_FPGA_CONFIG_START: 742 status = intel_fpga_config_start(x1); 743 SMC_RET4(handle, status, 0, 0, 0); 744 745 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 746 status = intel_fpga_config_write(x1, x2); 747 SMC_RET4(handle, status, 0, 0, 0); 748 749 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 750 status = intel_fpga_config_completed_write(completed_addr, 751 &retval, &rcv_id); 752 switch (retval) { 753 case 1: 754 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 755 completed_addr[0], 0, 0); 756 757 case 2: 758 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 759 completed_addr[0], 760 completed_addr[1], 0); 761 762 case 3: 763 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 764 completed_addr[0], 765 completed_addr[1], 766 completed_addr[2]); 767 768 case 0: 769 SMC_RET4(handle, status, 0, 0, 0); 770 771 default: 772 mailbox_clear_response(); 773 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 774 } 775 776 case INTEL_SIP_SMC_REG_READ: 777 status = intel_secure_reg_read(x1, &retval); 778 SMC_RET3(handle, status, retval, x1); 779 780 case INTEL_SIP_SMC_REG_WRITE: 781 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 782 SMC_RET3(handle, status, retval, x1); 783 784 case INTEL_SIP_SMC_REG_UPDATE: 785 status = intel_secure_reg_update(x1, (uint32_t)x2, 786 (uint32_t)x3, &retval); 787 SMC_RET3(handle, status, retval, x1); 788 789 case INTEL_SIP_SMC_RSU_STATUS: 790 status = intel_rsu_status(rsu_respbuf, 791 ARRAY_SIZE(rsu_respbuf)); 792 if (status) { 793 SMC_RET1(handle, status); 794 } else { 795 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 796 rsu_respbuf[2], rsu_respbuf[3]); 797 } 798 799 case INTEL_SIP_SMC_RSU_UPDATE: 800 status = intel_rsu_update(x1); 801 SMC_RET1(handle, status); 802 803 case INTEL_SIP_SMC_RSU_NOTIFY: 804 status = intel_rsu_notify(x1); 805 SMC_RET1(handle, status); 806 807 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 808 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 809 ARRAY_SIZE(rsu_respbuf), &retval); 810 if (status) { 811 SMC_RET1(handle, status); 812 } else { 813 SMC_RET2(handle, status, retval); 814 } 815 816 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 817 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 818 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 819 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 820 821 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 822 status = intel_rsu_copy_dcmf_version(x1, x2); 823 SMC_RET1(handle, status); 824 825 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 826 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 827 ((uint64_t)rsu_dcmf_stat[3] << 48) | 828 ((uint64_t)rsu_dcmf_stat[2] << 32) | 829 ((uint64_t)rsu_dcmf_stat[1] << 16) | 830 rsu_dcmf_stat[0]); 831 832 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 833 status = intel_rsu_copy_dcmf_status(x1); 834 SMC_RET1(handle, status); 835 836 case INTEL_SIP_SMC_RSU_MAX_RETRY: 837 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 838 839 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 840 rsu_max_retry = x1; 841 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 842 843 case INTEL_SIP_SMC_ECC_DBE: 844 status = intel_ecc_dbe_notification(x1); 845 SMC_RET1(handle, status); 846 847 case INTEL_SIP_SMC_SERVICE_COMPLETED: 848 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 849 &len_in_resp, &mbox_error); 850 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 851 852 case INTEL_SIP_SMC_FIRMWARE_VERSION: 853 status = intel_smc_fw_version(&retval); 854 SMC_RET2(handle, status, retval); 855 856 case INTEL_SIP_SMC_MBOX_SEND_CMD: 857 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 858 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 859 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 860 &mbox_status, &len_in_resp); 861 SMC_RET3(handle, status, mbox_status, len_in_resp); 862 863 case INTEL_SIP_SMC_GET_USERCODE: 864 status = intel_smc_get_usercode(&retval); 865 SMC_RET2(handle, status, retval); 866 867 case INTEL_SIP_SMC_FCS_CRYPTION: 868 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 869 870 if (x1 == FCS_MODE_DECRYPT) { 871 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 872 } else if (x1 == FCS_MODE_ENCRYPT) { 873 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 874 } else { 875 status = INTEL_SIP_SMC_STATUS_REJECTED; 876 } 877 878 SMC_RET3(handle, status, x4, x5); 879 880 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 881 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 882 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 883 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 884 885 if (x3 == FCS_MODE_DECRYPT) { 886 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 887 (uint32_t *) &x7, &mbox_error); 888 } else if (x3 == FCS_MODE_ENCRYPT) { 889 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 890 (uint32_t *) &x7, &mbox_error); 891 } else { 892 status = INTEL_SIP_SMC_STATUS_REJECTED; 893 } 894 895 SMC_RET4(handle, status, mbox_error, x6, x7); 896 897 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 898 status = intel_fcs_random_number_gen(x1, &retval64, 899 &mbox_error); 900 SMC_RET4(handle, status, mbox_error, x1, retval64); 901 902 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 903 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 904 &send_id); 905 SMC_RET1(handle, status); 906 907 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 908 status = intel_fcs_send_cert(x1, x2, &send_id); 909 SMC_RET1(handle, status); 910 911 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 912 status = intel_fcs_get_provision_data(&send_id); 913 SMC_RET1(handle, status); 914 915 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 916 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 917 &mbox_error); 918 SMC_RET2(handle, status, mbox_error); 919 920 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 921 status = intel_hps_set_bridges(x1, x2); 922 SMC_RET1(handle, status); 923 924 case INTEL_SIP_SMC_HWMON_READTEMP: 925 status = intel_hwmon_readtemp(x1, &retval); 926 SMC_RET2(handle, status, retval); 927 928 case INTEL_SIP_SMC_HWMON_READVOLT: 929 status = intel_hwmon_readvolt(x1, &retval); 930 SMC_RET2(handle, status, retval); 931 932 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 933 status = intel_fcs_sigma_teardown(x1, &mbox_error); 934 SMC_RET2(handle, status, mbox_error); 935 936 case INTEL_SIP_SMC_FCS_CHIP_ID: 937 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 938 SMC_RET4(handle, status, mbox_error, retval, retval2); 939 940 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 941 status = intel_fcs_attestation_subkey(x1, x2, x3, 942 (uint32_t *) &x4, &mbox_error); 943 SMC_RET4(handle, status, mbox_error, x3, x4); 944 945 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 946 status = intel_fcs_get_measurement(x1, x2, x3, 947 (uint32_t *) &x4, &mbox_error); 948 SMC_RET4(handle, status, mbox_error, x3, x4); 949 950 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 951 status = intel_fcs_get_attestation_cert(x1, x2, 952 (uint32_t *) &x3, &mbox_error); 953 SMC_RET4(handle, status, mbox_error, x2, x3); 954 955 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 956 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 957 SMC_RET2(handle, status, mbox_error); 958 959 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 960 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 961 SMC_RET3(handle, status, mbox_error, retval); 962 963 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 964 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 965 SMC_RET2(handle, status, mbox_error); 966 967 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 968 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 969 SMC_RET1(handle, status); 970 971 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 972 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 973 (uint32_t *) &x4, &mbox_error); 974 SMC_RET4(handle, status, mbox_error, x3, x4); 975 976 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 977 status = intel_fcs_remove_crypto_service_key(x1, x2, 978 &mbox_error); 979 SMC_RET2(handle, status, mbox_error); 980 981 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 982 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 983 (uint32_t *) &x4, &mbox_error); 984 SMC_RET4(handle, status, mbox_error, x3, x4); 985 986 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 987 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 988 status = intel_fcs_get_digest_init(x1, x2, x3, 989 x4, x5, &mbox_error); 990 SMC_RET2(handle, status, mbox_error); 991 992 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 993 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 994 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 995 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 996 x4, x5, (uint32_t *) &x6, false, 997 &mbox_error); 998 SMC_RET4(handle, status, mbox_error, x5, x6); 999 1000 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1001 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1002 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1003 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1004 x4, x5, (uint32_t *) &x6, true, 1005 &mbox_error); 1006 SMC_RET4(handle, status, mbox_error, x5, x6); 1007 1008 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1009 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1010 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1011 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1012 x4, x5, (uint32_t *) &x6, false, 1013 &mbox_error, &send_id); 1014 SMC_RET4(handle, status, mbox_error, x5, x6); 1015 1016 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1018 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1019 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1020 x4, x5, (uint32_t *) &x6, true, 1021 &mbox_error, &send_id); 1022 SMC_RET4(handle, status, mbox_error, x5, x6); 1023 1024 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1025 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1026 status = intel_fcs_mac_verify_init(x1, x2, x3, 1027 x4, x5, &mbox_error); 1028 SMC_RET2(handle, status, mbox_error); 1029 1030 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1031 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1032 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1033 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1034 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1035 x4, x5, (uint32_t *) &x6, x7, 1036 false, &mbox_error); 1037 SMC_RET4(handle, status, mbox_error, x5, x6); 1038 1039 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1040 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1041 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1042 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1043 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1044 x4, x5, (uint32_t *) &x6, x7, 1045 true, &mbox_error); 1046 SMC_RET4(handle, status, mbox_error, x5, x6); 1047 1048 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1049 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1050 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1051 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1052 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1053 x4, x5, (uint32_t *) &x6, x7, 1054 false, &mbox_error, &send_id); 1055 SMC_RET4(handle, status, mbox_error, x5, x6); 1056 1057 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1058 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1059 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1060 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1061 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1062 x4, x5, (uint32_t *) &x6, x7, 1063 true, &mbox_error, &send_id); 1064 SMC_RET4(handle, status, mbox_error, x5, x6); 1065 1066 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1067 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1068 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1069 x4, x5, &mbox_error); 1070 SMC_RET2(handle, status, mbox_error); 1071 1072 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1073 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1074 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1075 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1076 x3, x4, x5, (uint32_t *) &x6, false, 1077 &mbox_error); 1078 SMC_RET4(handle, status, mbox_error, x5, x6); 1079 1080 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1081 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1082 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1083 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1084 x3, x4, x5, (uint32_t *) &x6, true, 1085 &mbox_error); 1086 SMC_RET4(handle, status, mbox_error, x5, x6); 1087 1088 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1089 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1090 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1091 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1092 x2, x3, x4, x5, (uint32_t *) &x6, false, 1093 &mbox_error, &send_id); 1094 SMC_RET4(handle, status, mbox_error, x5, x6); 1095 1096 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1097 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1098 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1099 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1100 x2, x3, x4, x5, (uint32_t *) &x6, true, 1101 &mbox_error, &send_id); 1102 SMC_RET4(handle, status, mbox_error, x5, x6); 1103 1104 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1105 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1106 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1107 x4, x5, &mbox_error); 1108 SMC_RET2(handle, status, mbox_error); 1109 1110 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1111 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1112 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1113 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1114 x4, x5, (uint32_t *) &x6, &mbox_error); 1115 SMC_RET4(handle, status, mbox_error, x5, x6); 1116 1117 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1118 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1119 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1120 x4, x5, &mbox_error); 1121 SMC_RET2(handle, status, mbox_error); 1122 1123 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1124 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1125 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1126 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1127 x4, x5, (uint32_t *) &x6, &mbox_error); 1128 SMC_RET4(handle, status, mbox_error, x5, x6); 1129 1130 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1131 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1132 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1133 x4, x5, &mbox_error); 1134 SMC_RET2(handle, status, mbox_error); 1135 1136 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1137 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1138 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1139 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1140 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1141 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1142 x7, false, &mbox_error); 1143 SMC_RET4(handle, status, mbox_error, x5, x6); 1144 1145 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1146 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1147 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1148 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1149 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1150 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1151 x7, false, &mbox_error, &send_id); 1152 SMC_RET4(handle, status, mbox_error, x5, x6); 1153 1154 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1155 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1156 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1157 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1158 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1159 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1160 x7, true, &mbox_error, &send_id); 1161 SMC_RET4(handle, status, mbox_error, x5, x6); 1162 1163 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1164 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1165 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1166 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1167 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1168 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1169 x7, true, &mbox_error); 1170 SMC_RET4(handle, status, mbox_error, x5, x6); 1171 1172 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1173 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1174 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1175 x4, x5, &mbox_error); 1176 SMC_RET2(handle, status, mbox_error); 1177 1178 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1179 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1180 (uint32_t *) &x4, &mbox_error); 1181 SMC_RET4(handle, status, mbox_error, x3, x4); 1182 1183 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1184 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1185 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1186 x4, x5, &mbox_error); 1187 SMC_RET2(handle, status, mbox_error); 1188 1189 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1190 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1191 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1192 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1193 x4, x5, (uint32_t *) &x6, &mbox_error); 1194 SMC_RET4(handle, status, mbox_error, x5, x6); 1195 1196 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1197 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1198 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1199 &mbox_error); 1200 SMC_RET2(handle, status, mbox_error); 1201 1202 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1203 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1204 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1205 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1206 x5, x6, false, &send_id); 1207 SMC_RET1(handle, status); 1208 1209 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1210 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1211 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1212 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1213 x5, x6, true, &send_id); 1214 SMC_RET1(handle, status); 1215 1216 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1217 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1218 &mbox_error); 1219 SMC_RET4(handle, status, mbox_error, x1, retval64); 1220 1221 case INTEL_SIP_SMC_SVC_VERSION: 1222 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1223 SIP_SVC_VERSION_MAJOR, 1224 SIP_SVC_VERSION_MINOR); 1225 1226 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1227 status = intel_sdm_seu_err_read(seu_respbuf, 1228 ARRAY_SIZE(seu_respbuf)); 1229 if (status) { 1230 SMC_RET1(handle, status); 1231 } else { 1232 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1233 } 1234 1235 default: 1236 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1237 cookie, handle, flags); 1238 } 1239 } 1240 1241 uintptr_t sip_smc_handler(uint32_t smc_fid, 1242 u_register_t x1, 1243 u_register_t x2, 1244 u_register_t x3, 1245 u_register_t x4, 1246 void *cookie, 1247 void *handle, 1248 u_register_t flags) 1249 { 1250 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1251 1252 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1253 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1254 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1255 cookie, handle, flags); 1256 } else { 1257 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1258 cookie, handle, flags); 1259 } 1260 } 1261 1262 DECLARE_RT_SVC( 1263 socfpga_sip_svc, 1264 OEN_SIP_START, 1265 OEN_SIP_END, 1266 SMC_TYPE_FAST, 1267 NULL, 1268 sip_smc_handler 1269 ); 1270 1271 DECLARE_RT_SVC( 1272 socfpga_sip_svc_std, 1273 OEN_SIP_START, 1274 OEN_SIP_END, 1275 SMC_TYPE_YIELD, 1276 NULL, 1277 sip_smc_handler 1278 ); 1279