| 8eb6a1da | 08-Nov-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(xilinx): update correct return types
Refactor the return types to ensure code correctness and compliance for DT console.
Change-Id: I11dc3afbe168a78ddc03427df3f5f8d10fe40d40 Signed-off-by: Pras
fix(xilinx): update correct return types
Refactor the return types to ensure code correctness and compliance for DT console.
Change-Id: I11dc3afbe168a78ddc03427df3f5f8d10fe40d40 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
show more ...
|
| e2d9dfe2 | 03-Nov-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(xilinx): add FIT image check in DT console
With this change, the 'is_valid_dtb()' function has been added, which checks for the presence of the FDT header, FDT open, and the '/configurations' pr
fix(xilinx): add FIT image check in DT console
With this change, the 'is_valid_dtb()' function has been added, which checks for the presence of the FDT header, FDT open, and the '/configurations' property in the DTB. This property is only available in FIT images. If the property is present, a warning message is printed, and the code skips reading console information from the FIT image. Memory mapping is not necessary because it is called in the early setup function to collect UART information from the DTB.
Change-Id: I91335a180e7ece2cc0ec9fac4026556c48dd8cc8 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
show more ...
|
| 046e1304 | 20-Oct-2023 |
Prasad Kummari <prasad.kummari@amd.com> |
fix(xilinx): add FIT image check in prepare_dtb
Introduce two new functions: 'is_valid_image()' and 'is_fit_image()' to enhance the functionality of the system. 'is_valid_image()' will verify the pr
fix(xilinx): add FIT image check in prepare_dtb
Introduce two new functions: 'is_valid_image()' and 'is_fit_image()' to enhance the functionality of the system. 'is_valid_image()' will verify the presence of the FDT header and ensure that the FDT is open. Meanwhile, 'is_fit_image()' will be responsible for detecting FIT images. When TF-A is built with a DTB address during compilation and later executed from DDR memory, TF-A will dynamically reserve a memory location in the DTB during runtime.
This approach is effective when a raw DTB is present at the specified address location. With this change, the "is_fit_image()" function has been introduced to verify the existence of the "/configurations" property within the DTB.
The presence of this property is exclusive to FIT images. In case the property is found, a warning message is displayed, and memory space reservation for its address space in DDR is not performed by TF-A. However, if the property is not present, TF-A continues its usual procedure of updating the raw DTB.
Additionally, dynamic mapping has been refactored and separated into distinct functions: "add_mmap_dynamic_region ()" and "remove_dynamic_mmap()". This separation enhances compatibility and maintains better code organization.
Change-Id: I9cd3f09863b44483445e58c802dee34d58dfe2e9 Signed-off-by: Prasad Kummari <prasad.kummari@amd.com>
show more ...
|
| 2f17ac01 | 12-Oct-2023 |
Girisha Dengi <girisha.dengi@intel.com> |
fix(intel): read QSPI bank buffer data in bytes
Read QSPI bank buffer data in bytes to avoid inter-bank read failures.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Change-Id: If768d7cdd36
fix(intel): read QSPI bank buffer data in bytes
Read QSPI bank buffer data in bytes to avoid inter-bank read failures.
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Change-Id: If768d7cdd362694df3f3c86c959afad01a523f21
show more ...
|
| e7781c84 | 08-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(arm): correct the SPMC_AT_EL3 condition" into integration |
| 9c473d88 | 08-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge "fix(intel): update boot scratch cold register to use cold 8" into integration |
| 31a815db | 08-Nov-2023 |
Manish Pandey <manish.pandey2@arm.com> |
Merge changes from topic "sb/remove-cryptocell" into integration
* changes: chore(npcm845x): remove CryptoCell-712/713 support chore(auth)!: remove CryptoCell-712/713 support |
| 03baf340 | 08-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "docs(qemu): mention a55 in list of v8.2 cores" into integration |
| 7f267777 | 08-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "build(qemu): use xlat tables v2 directly" into integration |
| 0c5aafc6 | 07-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(npcm845x): remove CryptoCell-712/713 support
CryptoCell-712 and CryptoCell-713 drivers have been deprecated. Remove their usage on Nuvoton npcm845x platform (maintainers confirmed that this re
chore(npcm845x): remove CryptoCell-712/713 support
CryptoCell-712 and CryptoCell-713 drivers have been deprecated. Remove their usage on Nuvoton npcm845x platform (maintainers confirmed that this removal is fine with them).
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: I0e3f3431558aaea1e0f2740e7088cdc155d06af2
show more ...
|
| 70524d3d | 08-Nov-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
build(qemu): use xlat tables v2 directly
Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it in common/common.mk) so there is no need to include compat headers.
Change-Id
build(qemu): use xlat tables v2 directly
Both qemu and qemu-sbsa use xlat tables v2 already (activated by including it in common/common.mk) so there is no need to include compat headers.
Change-Id: I353a6f77f5916862e54b883a9adbba027ac81359 Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
show more ...
|
| c41b16ea | 08-Nov-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
docs(qemu): mention a55 in list of v8.2 cores
Change-Id: Ib3a1711be323023cf111373111f39038fa23fb6f Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
| a0ef1c0e | 08-Nov-2023 |
Manish V Badarkhe <Manish.Badarkhe@arm.com> |
fix(arm): correct the SPMC_AT_EL3 condition
Addressed the SPMC_AT_EL3 condition by using '#if' instead of '#if defined'. This change is warranted because the SPMC_AT_EL3 option is always defined.
C
fix(arm): correct the SPMC_AT_EL3 condition
Addressed the SPMC_AT_EL3 condition by using '#if' instead of '#if defined'. This change is warranted because the SPMC_AT_EL3 option is always defined.
Change-Id: I76d9b8d502f452c58bc0040745d642cbe11dc8eb Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
show more ...
|
| b65dfe40 | 26-Oct-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
chore(auth)!: remove CryptoCell-712/713 support
CryptoCell-712 and CryptoCell-713 drivers have been deprecated since TF-A v2.9 and their removal was announced for TF-A v2.10 release. See [1].
As th
chore(auth)!: remove CryptoCell-712/713 support
CryptoCell-712 and CryptoCell-713 drivers have been deprecated since TF-A v2.9 and their removal was announced for TF-A v2.10 release. See [1].
As the release is approaching, this patch deletes these drivers' code as well as all references to them in the documentation and Arm platforms code (Nuvoton platform is taken care in a subsequent patch). Associated build options (ARM_CRYPTOCELL_INTEG and PLAT_CRYPTOCELL_BASE) have also been removed and thus will have no effect if defined.
This is a breaking change for downstream platforms which use these drivers.
[1] https://trustedfirmware-a.readthedocs.io/en/v2.9/about/release-information.html#removal-of-deprecated-drivers Note that TF-A v3.0 release later got renumbered into v2.10.
Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Change-Id: Idabbc9115f6732ac1a0e52b273d3380677a39813
show more ...
|
| dde37f2d | 08-Nov-2023 |
Sandrine Bailleux <sandrine.bailleux@arm.com> |
Merge "build(qemu-sbsa): it is GICv3 platform" into integration |
| 7c33bcab | 29-Mar-2022 |
Nishant Sharma <nishant.sharma@arm.com> |
feat(sgi): increase sp memmap size
With FF-A enabled on SP at SEL0 enabled, SPMC at EL3 needs more entries to map newly added regions(SP, Rx/Tx buffer and Manifest).
Increase the PLAT_SP_IMAGE_MMAP
feat(sgi): increase sp memmap size
With FF-A enabled on SP at SEL0 enabled, SPMC at EL3 needs more entries to map newly added regions(SP, Rx/Tx buffer and Manifest).
Increase the PLAT_SP_IMAGE_MMAP_REGIONS to 14 and MAX_XLAT_TABLES to 9.
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Signed-off-by: Nishant Sharma <nishant.sharma@arm.com> Change-Id: I96fd291db8eb178f7aa73b5a9e38cfc67c66fa91
show more ...
|
| 821b01fa | 13-Oct-2023 |
Nishant Sharma <nishant.sharma@arm.com> |
feat(arm): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code. Populate the BL32 image base, size and max limit in arg2, arg3 an
feat(arm): save BL32 image base and size in entry point info
There is no platform function to retrieve the info in the generic code. Populate the BL32 image base, size and max limit in arg2, arg3 and arg4.
Signed-off-by: Achin Gupta <achin.gupta@arm.com> Signed-off-by: Nishant Sharma <nishant.sharma@arm.com> Change-Id: Id41cedd790ca1713787e5516fb84666d1ccb0b03
show more ...
|
| b54dfb5d | 06-Nov-2023 |
Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> |
build(qemu-sbsa): it is GICv3 platform
GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Change-Id: Ibf9376caabbc05ceef4f870d8
build(qemu-sbsa): it is GICv3 platform
GICV2_G0_FOR_EL3 variable is only for GICv2 platforms.
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org> Change-Id: Ibf9376caabbc05ceef4f870d816e6c60a344f895
show more ...
|
| 1684c8d6 | 06-Nov-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "enable_assertion" into integration
* changes: feat(zynqmp): enable assertion feat(versal-net): enable assertion feat(versal): enable assertion |
| 9ac3bcdd | 06-Nov-2023 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "fix(ti): release lock in all TI-SCI xfer return paths" into integration |
| bfb8d8eb | 06-Nov-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(xilinx): switch boot console to runtime" into integration |
| d5fe7088 | 06-Nov-2023 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(zynqmp): remove pm_ioctl_set_sgmii_mode api" into integration |
| e92375e0 | 31-Oct-2023 |
Andrew Davis <afd@ti.com> |
fix(ti): release lock in all TI-SCI xfer return paths
Failing to send a message is often not fatal and we will end up trying to send again. This would fail as some exit paths do not release the secu
fix(ti): release lock in all TI-SCI xfer return paths
Failing to send a message is often not fatal and we will end up trying to send again. This would fail as some exit paths do not release the secure proxy xfer lock. Release this lock on all return paths.
Signed-off-by: Andrew Davis <afd@ti.com> Change-Id: I3939015774f819572dbd26720b2c105fba7574cb
show more ...
|
| cfbac595 | 19-Oct-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): bl31 overwrite OCRAM configuration
U-boot is allowed to configure OCRAM access. However ATF BL31 will overwrite it. Thus removing this function to allow for proper configuration.
Change
fix(intel): bl31 overwrite OCRAM configuration
U-boot is allowed to configure OCRAM access. However ATF BL31 will overwrite it. Thus removing this function to allow for proper configuration.
Change-Id: I45173ef8f472c3620486de0cbf6452ba5f78be01 Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
show more ...
|
| 82752c41 | 15-Oct-2023 |
Jit Loon Lim <jit.loon.lim@intel.com> |
fix(intel): update individual return result for hps and fpga bridges
The code is designed to execute SOC2FPGA and LWSOC2FPGA first then to F2SOC and both sharing the same result "return". Thus when
fix(intel): update individual return result for hps and fpga bridges
The code is designed to execute SOC2FPGA and LWSOC2FPGA first then to F2SOC and both sharing the same result "return". Thus when F2SOC is executed, the "return" result will overwrite SOC2FPGA "return" result even though it is not enabled. Using 2 different "return" result to for each bridges and return both of them at the end of the function to avoid being overwritten.
Change-Id: Id9de3f416fe3020db35bc946135b175be2a7dc1e Signed-off-by: Jit Loon Lim <jit.loon.lim@intel.com>
show more ...
|