1 /* 2 * Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <common/debug.h> 9 #include <common/runtime_svc.h> 10 #include <lib/mmio.h> 11 #include <tools_share/uuid.h> 12 13 #include "socfpga_fcs.h" 14 #include "socfpga_mailbox.h" 15 #include "socfpga_plat_def.h" 16 #include "socfpga_reset_manager.h" 17 #include "socfpga_sip_svc.h" 18 #include "socfpga_system_manager.h" 19 20 /* Total buffer the driver can hold */ 21 #define FPGA_CONFIG_BUFFER_SIZE 4 22 23 static config_type request_type = NO_REQUEST; 24 static int current_block, current_buffer; 25 static int read_block, max_blocks; 26 static uint32_t send_id, rcv_id; 27 static uint32_t bytes_per_block, blocks_submitted; 28 static bool bridge_disable; 29 30 /* RSU static variables */ 31 static uint32_t rsu_dcmf_ver[4] = {0}; 32 static uint16_t rsu_dcmf_stat[4] = {0}; 33 static uint32_t rsu_max_retry; 34 35 /* SiP Service UUID */ 36 DEFINE_SVC_UUID2(intl_svc_uid, 37 0xa85273b0, 0xe85a, 0x4862, 0xa6, 0x2a, 38 0xfa, 0x88, 0x88, 0x17, 0x68, 0x81); 39 40 static uint64_t socfpga_sip_handler(uint32_t smc_fid, 41 uint64_t x1, 42 uint64_t x2, 43 uint64_t x3, 44 uint64_t x4, 45 void *cookie, 46 void *handle, 47 uint64_t flags) 48 { 49 ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid); 50 SMC_RET1(handle, SMC_UNK); 51 } 52 53 struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE]; 54 55 static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer) 56 { 57 uint32_t args[3]; 58 59 while (max_blocks > 0 && buffer->size > buffer->size_written) { 60 args[0] = (1<<8); 61 args[1] = buffer->addr + buffer->size_written; 62 if (buffer->size - buffer->size_written <= bytes_per_block) { 63 args[2] = buffer->size - buffer->size_written; 64 current_buffer++; 65 current_buffer %= FPGA_CONFIG_BUFFER_SIZE; 66 } else { 67 args[2] = bytes_per_block; 68 } 69 70 buffer->size_written += args[2]; 71 mailbox_send_cmd_async(&send_id, MBOX_RECONFIG_DATA, args, 72 3U, CMD_INDIRECT); 73 74 buffer->subblocks_sent++; 75 max_blocks--; 76 } 77 78 return !max_blocks; 79 } 80 81 static int intel_fpga_sdm_write_all(void) 82 { 83 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 84 if (intel_fpga_sdm_write_buffer( 85 &fpga_config_buffers[current_buffer])) { 86 break; 87 } 88 } 89 return 0; 90 } 91 92 static uint32_t intel_mailbox_fpga_config_isdone(void) 93 { 94 uint32_t ret; 95 96 switch (request_type) { 97 case RECONFIGURATION: 98 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 99 true); 100 break; 101 case BITSTREAM_AUTH: 102 ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, 103 false); 104 break; 105 default: 106 ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, 107 false); 108 break; 109 } 110 111 if (ret != 0U) { 112 if (ret == MBOX_CFGSTAT_STATE_CONFIG) { 113 return INTEL_SIP_SMC_STATUS_BUSY; 114 } else { 115 request_type = NO_REQUEST; 116 return INTEL_SIP_SMC_STATUS_ERROR; 117 } 118 } 119 120 if (bridge_disable != 0U) { 121 socfpga_bridges_enable(~0); /* Enable bridge */ 122 bridge_disable = false; 123 } 124 request_type = NO_REQUEST; 125 126 return INTEL_SIP_SMC_STATUS_OK; 127 } 128 129 static int mark_last_buffer_xfer_completed(uint32_t *buffer_addr_completed) 130 { 131 int i; 132 133 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 134 if (fpga_config_buffers[i].block_number == current_block) { 135 fpga_config_buffers[i].subblocks_sent--; 136 if (fpga_config_buffers[i].subblocks_sent == 0 137 && fpga_config_buffers[i].size <= 138 fpga_config_buffers[i].size_written) { 139 fpga_config_buffers[i].write_requested = 0; 140 current_block++; 141 *buffer_addr_completed = 142 fpga_config_buffers[i].addr; 143 return 0; 144 } 145 } 146 } 147 148 return -1; 149 } 150 151 static int intel_fpga_config_completed_write(uint32_t *completed_addr, 152 uint32_t *count, uint32_t *job_id) 153 { 154 uint32_t resp[5]; 155 unsigned int resp_len = ARRAY_SIZE(resp); 156 int status = INTEL_SIP_SMC_STATUS_OK; 157 int all_completed = 1; 158 *count = 0; 159 160 while (*count < 3) { 161 162 status = mailbox_read_response(job_id, 163 resp, &resp_len); 164 165 if (status < 0) { 166 break; 167 } 168 169 max_blocks++; 170 171 if (mark_last_buffer_xfer_completed( 172 &completed_addr[*count]) == 0) { 173 *count = *count + 1; 174 } else { 175 break; 176 } 177 } 178 179 if (*count <= 0) { 180 if (status != MBOX_NO_RESPONSE && 181 status != MBOX_TIMEOUT && resp_len != 0) { 182 mailbox_clear_response(); 183 request_type = NO_REQUEST; 184 return INTEL_SIP_SMC_STATUS_ERROR; 185 } 186 187 *count = 0; 188 } 189 190 intel_fpga_sdm_write_all(); 191 192 if (*count > 0) { 193 status = INTEL_SIP_SMC_STATUS_OK; 194 } else if (*count == 0) { 195 status = INTEL_SIP_SMC_STATUS_BUSY; 196 } 197 198 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 199 if (fpga_config_buffers[i].write_requested != 0) { 200 all_completed = 0; 201 break; 202 } 203 } 204 205 if (all_completed == 1) { 206 return INTEL_SIP_SMC_STATUS_OK; 207 } 208 209 return status; 210 } 211 212 static int intel_fpga_config_start(uint32_t flag) 213 { 214 uint32_t argument = 0x1; 215 uint32_t response[3]; 216 int status = 0; 217 unsigned int size = 0; 218 unsigned int resp_len = ARRAY_SIZE(response); 219 220 request_type = RECONFIGURATION; 221 222 if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { 223 bridge_disable = true; 224 } 225 226 if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { 227 size = 1; 228 bridge_disable = false; 229 request_type = BITSTREAM_AUTH; 230 } 231 232 mailbox_clear_response(); 233 234 mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_CANCEL, NULL, 0U, 235 CMD_CASUAL, NULL, NULL); 236 237 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_RECONFIG, &argument, size, 238 CMD_CASUAL, response, &resp_len); 239 240 if (status < 0) { 241 bridge_disable = false; 242 request_type = NO_REQUEST; 243 return INTEL_SIP_SMC_STATUS_ERROR; 244 } 245 246 max_blocks = response[0]; 247 bytes_per_block = response[1]; 248 249 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 250 fpga_config_buffers[i].size = 0; 251 fpga_config_buffers[i].size_written = 0; 252 fpga_config_buffers[i].addr = 0; 253 fpga_config_buffers[i].write_requested = 0; 254 fpga_config_buffers[i].block_number = 0; 255 fpga_config_buffers[i].subblocks_sent = 0; 256 } 257 258 blocks_submitted = 0; 259 current_block = 0; 260 read_block = 0; 261 current_buffer = 0; 262 263 /* Disable bridge on full reconfiguration */ 264 if (bridge_disable) { 265 socfpga_bridges_disable(~0); 266 } 267 268 return INTEL_SIP_SMC_STATUS_OK; 269 } 270 271 static bool is_fpga_config_buffer_full(void) 272 { 273 for (int i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 274 if (!fpga_config_buffers[i].write_requested) { 275 return false; 276 } 277 } 278 return true; 279 } 280 281 bool is_address_in_ddr_range(uint64_t addr, uint64_t size) 282 { 283 uint128_t dram_max_sz = (uint128_t)DRAM_BASE + (uint128_t)DRAM_SIZE; 284 uint128_t dram_region_end = (uint128_t)addr + (uint128_t)size; 285 286 if (!addr && !size) { 287 return true; 288 } 289 if (size > (UINT64_MAX - addr)) { 290 return false; 291 } 292 if (addr < BL31_LIMIT) { 293 return false; 294 } 295 if (dram_region_end > dram_max_sz) { 296 return false; 297 } 298 299 return true; 300 } 301 302 static uint32_t intel_fpga_config_write(uint64_t mem, uint64_t size) 303 { 304 int i; 305 306 intel_fpga_sdm_write_all(); 307 308 if (!is_address_in_ddr_range(mem, size) || 309 is_fpga_config_buffer_full()) { 310 return INTEL_SIP_SMC_STATUS_REJECTED; 311 } 312 313 for (i = 0; i < FPGA_CONFIG_BUFFER_SIZE; i++) { 314 int j = (i + current_buffer) % FPGA_CONFIG_BUFFER_SIZE; 315 316 if (!fpga_config_buffers[j].write_requested) { 317 fpga_config_buffers[j].addr = mem; 318 fpga_config_buffers[j].size = size; 319 fpga_config_buffers[j].size_written = 0; 320 fpga_config_buffers[j].write_requested = 1; 321 fpga_config_buffers[j].block_number = 322 blocks_submitted++; 323 fpga_config_buffers[j].subblocks_sent = 0; 324 break; 325 } 326 } 327 328 if (is_fpga_config_buffer_full()) { 329 return INTEL_SIP_SMC_STATUS_BUSY; 330 } 331 332 return INTEL_SIP_SMC_STATUS_OK; 333 } 334 335 static int is_out_of_sec_range(uint64_t reg_addr) 336 { 337 #if DEBUG 338 return 0; 339 #endif 340 341 #if PLATFORM_MODEL != PLAT_SOCFPGA_AGILEX5 342 switch (reg_addr) { 343 case(0xF8011100): /* ECCCTRL1 */ 344 case(0xF8011104): /* ECCCTRL2 */ 345 case(0xF8011110): /* ERRINTEN */ 346 case(0xF8011114): /* ERRINTENS */ 347 case(0xF8011118): /* ERRINTENR */ 348 case(0xF801111C): /* INTMODE */ 349 case(0xF8011120): /* INTSTAT */ 350 case(0xF8011124): /* DIAGINTTEST */ 351 case(0xF801112C): /* DERRADDRA */ 352 case(0xFA000000): /* SMMU SCR0 */ 353 case(0xFA000004): /* SMMU SCR1 */ 354 case(0xFA000400): /* SMMU NSCR0 */ 355 case(0xFA004000): /* SMMU SSD0_REG */ 356 case(0xFA000820): /* SMMU SMR8 */ 357 case(0xFA000c20): /* SMMU SCR8 */ 358 case(0xFA028000): /* SMMU CB8_SCTRL */ 359 case(0xFA001020): /* SMMU CBAR8 */ 360 case(0xFA028030): /* SMMU TCR_LPAE */ 361 case(0xFA028020): /* SMMU CB8_TTBR0_LOW */ 362 case(0xFA028024): /* SMMU CB8_PRRR_HIGH */ 363 case(0xFA028038): /* SMMU CB8_PRRR_MIR0 */ 364 case(0xFA02803C): /* SMMU CB8_PRRR_MIR1 */ 365 case(0xFA028010): /* SMMU_CB8)TCR2 */ 366 case(0xFFD080A4): /* SDM SMMU STREAM ID REG */ 367 case(0xFA001820): /* SMMU_CBA2R8 */ 368 case(0xFA000074): /* SMMU_STLBGSTATUS */ 369 case(0xFA0287F4): /* SMMU_CB8_TLBSTATUS */ 370 case(0xFA000060): /* SMMU_STLBIALL */ 371 case(0xFA000070): /* SMMU_STLBGSYNC */ 372 case(0xFA028618): /* CB8_TLBALL */ 373 case(0xFA0287F0): /* CB8_TLBSYNC */ 374 case(0xFFD12028): /* SDMMCGRP_CTRL */ 375 case(0xFFD12044): /* EMAC0 */ 376 case(0xFFD12048): /* EMAC1 */ 377 case(0xFFD1204C): /* EMAC2 */ 378 case(0xFFD12090): /* ECC_INT_MASK_VALUE */ 379 case(0xFFD12094): /* ECC_INT_MASK_SET */ 380 case(0xFFD12098): /* ECC_INT_MASK_CLEAR */ 381 case(0xFFD1209C): /* ECC_INTSTATUS_SERR */ 382 case(0xFFD120A0): /* ECC_INTSTATUS_DERR */ 383 case(0xFFD120C0): /* NOC_TIMEOUT */ 384 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 385 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 386 case(0xFFD120D0): /* NOC_IDLEACK */ 387 case(0xFFD120D4): /* NOC_IDLESTATUS */ 388 case(0xFFD12200): /* BOOT_SCRATCH_COLD0 */ 389 case(0xFFD12204): /* BOOT_SCRATCH_COLD1 */ 390 case(0xFFD12220): /* BOOT_SCRATCH_COLD8 */ 391 case(0xFFD12224): /* BOOT_SCRATCH_COLD9 */ 392 return 0; 393 #else 394 switch (reg_addr) { 395 396 case(0xF8011104): /* ECCCTRL2 */ 397 case(0xFFD12028): /* SDMMCGRP_CTRL */ 398 case(0xFFD120C4): /* NOC_IDLEREQ_SET */ 399 case(0xFFD120C8): /* NOC_IDLEREQ_CLR */ 400 case(0xFFD120D0): /* NOC_IDLEACK */ 401 402 403 case(SOCFPGA_MEMCTRL(ECCCTRL1)): /* ECCCTRL1 */ 404 case(SOCFPGA_MEMCTRL(ERRINTEN)): /* ERRINTEN */ 405 case(SOCFPGA_MEMCTRL(ERRINTENS)): /* ERRINTENS */ 406 case(SOCFPGA_MEMCTRL(ERRINTENR)): /* ERRINTENR */ 407 case(SOCFPGA_MEMCTRL(INTMODE)): /* INTMODE */ 408 case(SOCFPGA_MEMCTRL(INTSTAT)): /* INTSTAT */ 409 case(SOCFPGA_MEMCTRL(DIAGINTTEST)): /* DIAGINTTEST */ 410 case(SOCFPGA_MEMCTRL(DERRADDRA)): /* DERRADDRA */ 411 412 case(SOCFPGA_SYSMGR(EMAC_0)): /* EMAC0 */ 413 case(SOCFPGA_SYSMGR(EMAC_1)): /* EMAC1 */ 414 case(SOCFPGA_SYSMGR(EMAC_2)): /* EMAC2 */ 415 case(SOCFPGA_SYSMGR(ECC_INTMASK_VALUE)): /* ECC_INT_MASK_VALUE */ 416 case(SOCFPGA_SYSMGR(ECC_INTMASK_SET)): /* ECC_INT_MASK_SET */ 417 case(SOCFPGA_SYSMGR(ECC_INTMASK_CLR)): /* ECC_INT_MASK_CLEAR */ 418 case(SOCFPGA_SYSMGR(ECC_INTMASK_SERR)): /* ECC_INTSTATUS_SERR */ 419 case(SOCFPGA_SYSMGR(ECC_INTMASK_DERR)): /* ECC_INTSTATUS_DERR */ 420 case(SOCFPGA_SYSMGR(NOC_TIMEOUT)): /* NOC_TIMEOUT */ 421 case(SOCFPGA_SYSMGR(NOC_IDLESTATUS)): /* NOC_IDLESTATUS */ 422 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_0)): /* BOOT_SCRATCH_COLD0 */ 423 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1)): /* BOOT_SCRATCH_COLD1 */ 424 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_8)): /* BOOT_SCRATCH_COLD8 */ 425 case(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_9)): /* BOOT_SCRATCH_COLD9 */ 426 #endif 427 case(SOCFPGA_ECC_QSPI(CTRL)): /* ECC_QSPI_CTRL */ 428 case(SOCFPGA_ECC_QSPI(ERRINTEN)): /* ECC_QSPI_ERRINTEN */ 429 case(SOCFPGA_ECC_QSPI(ERRINTENS)): /* ECC_QSPI_ERRINTENS */ 430 case(SOCFPGA_ECC_QSPI(ERRINTENR)): /* ECC_QSPI_ERRINTENR */ 431 case(SOCFPGA_ECC_QSPI(INTMODE)): /* ECC_QSPI_INTMODE */ 432 case(SOCFPGA_ECC_QSPI(ECC_ACCCTRL)): /* ECC_QSPI_ECC_ACCCTRL */ 433 case(SOCFPGA_ECC_QSPI(ECC_STARTACC)): /* ECC_QSPI_ECC_STARTACC */ 434 case(SOCFPGA_ECC_QSPI(ECC_WDCTRL)): /* ECC_QSPI_ECC_WDCTRL */ 435 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 436 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 437 return 0; 438 439 default: 440 break; 441 } 442 443 return -1; 444 } 445 446 /* Secure register access */ 447 uint32_t intel_secure_reg_read(uint64_t reg_addr, uint32_t *retval) 448 { 449 if (is_out_of_sec_range(reg_addr)) { 450 return INTEL_SIP_SMC_STATUS_ERROR; 451 } 452 453 *retval = mmio_read_32(reg_addr); 454 455 return INTEL_SIP_SMC_STATUS_OK; 456 } 457 458 uint32_t intel_secure_reg_write(uint64_t reg_addr, uint32_t val, 459 uint32_t *retval) 460 { 461 if (is_out_of_sec_range(reg_addr)) { 462 return INTEL_SIP_SMC_STATUS_ERROR; 463 } 464 465 switch (reg_addr) { 466 case(SOCFPGA_ECC_QSPI(INTSTAT)): /* ECC_QSPI_INTSTAT */ 467 case(SOCFPGA_ECC_QSPI(INTTEST)): /* ECC_QSPI_INTMODE */ 468 mmio_write_16(reg_addr, val); 469 break; 470 default: 471 mmio_write_32(reg_addr, val); 472 break; 473 } 474 475 return intel_secure_reg_read(reg_addr, retval); 476 } 477 478 uint32_t intel_secure_reg_update(uint64_t reg_addr, uint32_t mask, 479 uint32_t val, uint32_t *retval) 480 { 481 if (!intel_secure_reg_read(reg_addr, retval)) { 482 *retval &= ~mask; 483 *retval |= val & mask; 484 return intel_secure_reg_write(reg_addr, *retval, retval); 485 } 486 487 return INTEL_SIP_SMC_STATUS_ERROR; 488 } 489 490 /* Intel Remote System Update (RSU) services */ 491 uint64_t intel_rsu_update_address; 492 493 static uint32_t intel_rsu_status(uint64_t *respbuf, unsigned int respbuf_sz) 494 { 495 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 496 return INTEL_SIP_SMC_RSU_ERROR; 497 } 498 499 return INTEL_SIP_SMC_STATUS_OK; 500 } 501 502 uint32_t intel_rsu_update(uint64_t update_address) 503 { 504 if (update_address > SIZE_MAX) { 505 return INTEL_SIP_SMC_STATUS_REJECTED; 506 } 507 508 intel_rsu_update_address = update_address; 509 return INTEL_SIP_SMC_STATUS_OK; 510 } 511 512 static uint32_t intel_rsu_notify(uint32_t execution_stage) 513 { 514 if (mailbox_hps_stage_notify(execution_stage) < 0) { 515 return INTEL_SIP_SMC_RSU_ERROR; 516 } 517 518 return INTEL_SIP_SMC_STATUS_OK; 519 } 520 521 static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz, 522 uint32_t *ret_stat) 523 { 524 if (mailbox_rsu_status((uint32_t *)respbuf, respbuf_sz) < 0) { 525 return INTEL_SIP_SMC_RSU_ERROR; 526 } 527 528 *ret_stat = respbuf[8]; 529 return INTEL_SIP_SMC_STATUS_OK; 530 } 531 532 static uint32_t intel_rsu_copy_dcmf_version(uint64_t dcmf_ver_1_0, 533 uint64_t dcmf_ver_3_2) 534 { 535 rsu_dcmf_ver[0] = dcmf_ver_1_0; 536 rsu_dcmf_ver[1] = dcmf_ver_1_0 >> 32; 537 rsu_dcmf_ver[2] = dcmf_ver_3_2; 538 rsu_dcmf_ver[3] = dcmf_ver_3_2 >> 32; 539 540 return INTEL_SIP_SMC_STATUS_OK; 541 } 542 543 static uint32_t intel_rsu_copy_dcmf_status(uint64_t dcmf_stat) 544 { 545 rsu_dcmf_stat[0] = 0xFFFF & (dcmf_stat >> (0 * 16)); 546 rsu_dcmf_stat[1] = 0xFFFF & (dcmf_stat >> (1 * 16)); 547 rsu_dcmf_stat[2] = 0xFFFF & (dcmf_stat >> (2 * 16)); 548 rsu_dcmf_stat[3] = 0xFFFF & (dcmf_stat >> (3 * 16)); 549 550 return INTEL_SIP_SMC_STATUS_OK; 551 } 552 553 /* Intel HWMON services */ 554 static uint32_t intel_hwmon_readtemp(uint32_t chan, uint32_t *retval) 555 { 556 if (mailbox_hwmon_readtemp(chan, retval) < 0) { 557 return INTEL_SIP_SMC_STATUS_ERROR; 558 } 559 560 return INTEL_SIP_SMC_STATUS_OK; 561 } 562 563 static uint32_t intel_hwmon_readvolt(uint32_t chan, uint32_t *retval) 564 { 565 if (mailbox_hwmon_readvolt(chan, retval) < 0) { 566 return INTEL_SIP_SMC_STATUS_ERROR; 567 } 568 569 return INTEL_SIP_SMC_STATUS_OK; 570 } 571 572 /* Mailbox services */ 573 static uint32_t intel_smc_fw_version(uint32_t *fw_version) 574 { 575 int status; 576 unsigned int resp_len = CONFIG_STATUS_WORD_SIZE; 577 uint32_t resp_data[CONFIG_STATUS_WORD_SIZE] = {0U}; 578 579 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CONFIG_STATUS, NULL, 0U, 580 CMD_CASUAL, resp_data, &resp_len); 581 582 if (status < 0) { 583 return INTEL_SIP_SMC_STATUS_ERROR; 584 } 585 586 if (resp_len <= CONFIG_STATUS_FW_VER_OFFSET) { 587 return INTEL_SIP_SMC_STATUS_ERROR; 588 } 589 590 *fw_version = resp_data[CONFIG_STATUS_FW_VER_OFFSET] & CONFIG_STATUS_FW_VER_MASK; 591 592 return INTEL_SIP_SMC_STATUS_OK; 593 } 594 595 static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, 596 unsigned int len, uint32_t urgent, uint64_t response, 597 unsigned int resp_len, int *mbox_status, 598 unsigned int *len_in_resp) 599 { 600 *len_in_resp = 0; 601 *mbox_status = GENERIC_RESPONSE_ERROR; 602 603 if (!is_address_in_ddr_range((uint64_t)args, sizeof(uint32_t) * len)) { 604 return INTEL_SIP_SMC_STATUS_REJECTED; 605 } 606 607 int status = mailbox_send_cmd(MBOX_JOB_ID, cmd, args, len, urgent, 608 (uint32_t *) response, &resp_len); 609 610 if (status < 0) { 611 *mbox_status = -status; 612 return INTEL_SIP_SMC_STATUS_ERROR; 613 } 614 615 *mbox_status = 0; 616 *len_in_resp = resp_len; 617 618 flush_dcache_range(response, resp_len * MBOX_WORD_BYTE); 619 620 return INTEL_SIP_SMC_STATUS_OK; 621 } 622 623 static int intel_smc_get_usercode(uint32_t *user_code) 624 { 625 int status; 626 unsigned int resp_len = sizeof(user_code) / MBOX_WORD_BYTE; 627 628 status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_CMD_GET_USERCODE, NULL, 629 0U, CMD_CASUAL, user_code, &resp_len); 630 631 if (status < 0) { 632 return INTEL_SIP_SMC_STATUS_ERROR; 633 } 634 635 return INTEL_SIP_SMC_STATUS_OK; 636 } 637 638 uint32_t intel_smc_service_completed(uint64_t addr, uint32_t size, 639 uint32_t mode, uint32_t *job_id, 640 uint32_t *ret_size, uint32_t *mbox_error) 641 { 642 int status = 0; 643 uint32_t resp_len = size / MBOX_WORD_BYTE; 644 645 if (resp_len > MBOX_DATA_MAX_LEN) { 646 return INTEL_SIP_SMC_STATUS_REJECTED; 647 } 648 649 if (!is_address_in_ddr_range(addr, size)) { 650 return INTEL_SIP_SMC_STATUS_REJECTED; 651 } 652 653 if (mode == SERVICE_COMPLETED_MODE_ASYNC) { 654 status = mailbox_read_response_async(job_id, 655 NULL, (uint32_t *) addr, &resp_len, 0); 656 } else { 657 status = mailbox_read_response(job_id, 658 (uint32_t *) addr, &resp_len); 659 660 if (status == MBOX_NO_RESPONSE) { 661 status = MBOX_BUSY; 662 } 663 } 664 665 if (status == MBOX_NO_RESPONSE) { 666 return INTEL_SIP_SMC_STATUS_NO_RESPONSE; 667 } 668 669 if (status == MBOX_BUSY) { 670 return INTEL_SIP_SMC_STATUS_BUSY; 671 } 672 673 *ret_size = resp_len * MBOX_WORD_BYTE; 674 flush_dcache_range(addr, *ret_size); 675 676 if (status == MBOX_RET_SDOS_DECRYPTION_ERROR_102 || 677 status == MBOX_RET_SDOS_DECRYPTION_ERROR_103) { 678 *mbox_error = -status; 679 } else if (status != MBOX_RET_OK) { 680 *mbox_error = -status; 681 return INTEL_SIP_SMC_STATUS_ERROR; 682 } 683 684 return INTEL_SIP_SMC_STATUS_OK; 685 } 686 687 /* Miscellaneous HPS services */ 688 uint32_t intel_hps_set_bridges(uint64_t enable, uint64_t mask) 689 { 690 int status = 0; 691 692 if ((enable & SOCFPGA_BRIDGE_ENABLE) != 0U) { 693 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 694 status = socfpga_bridges_enable((uint32_t)mask); 695 } else { 696 status = socfpga_bridges_enable(~0); 697 } 698 } else { 699 if ((enable & SOCFPGA_BRIDGE_HAS_MASK) != 0U) { 700 status = socfpga_bridges_disable((uint32_t)mask); 701 } else { 702 status = socfpga_bridges_disable(~0); 703 } 704 } 705 706 if (status < 0) { 707 return INTEL_SIP_SMC_STATUS_ERROR; 708 } 709 710 return INTEL_SIP_SMC_STATUS_OK; 711 } 712 713 /* SDM SEU Error services */ 714 static uint32_t intel_sdm_seu_err_read(uint32_t *respbuf, unsigned int respbuf_sz) 715 { 716 if (mailbox_seu_err_status(respbuf, respbuf_sz) < 0) { 717 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 718 } 719 720 return INTEL_SIP_SMC_STATUS_OK; 721 } 722 723 /* SDM SAFE SEU Error inject services */ 724 static uint32_t intel_sdm_safe_inject_seu_err(uint32_t *command, uint32_t len) 725 { 726 if (mailbox_safe_inject_seu_err(command, len) < 0) { 727 return INTEL_SIP_SMC_SEU_ERR_READ_ERROR; 728 } 729 730 return INTEL_SIP_SMC_STATUS_OK; 731 } 732 733 /* 734 * This function is responsible for handling all SiP calls from the NS world 735 */ 736 737 uintptr_t sip_smc_handler_v1(uint32_t smc_fid, 738 u_register_t x1, 739 u_register_t x2, 740 u_register_t x3, 741 u_register_t x4, 742 void *cookie, 743 void *handle, 744 u_register_t flags) 745 { 746 uint32_t retval = 0, completed_addr[3]; 747 uint32_t retval2 = 0; 748 uint32_t mbox_error = 0; 749 uint64_t retval64, rsu_respbuf[9]; 750 uint32_t seu_respbuf[3]; 751 int status = INTEL_SIP_SMC_STATUS_OK; 752 int mbox_status; 753 unsigned int len_in_resp; 754 u_register_t x5, x6, x7; 755 756 switch (smc_fid) { 757 case SIP_SVC_UID: 758 /* Return UID to the caller */ 759 SMC_UUID_RET(handle, intl_svc_uid); 760 761 case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: 762 status = intel_mailbox_fpga_config_isdone(); 763 SMC_RET4(handle, status, 0, 0, 0); 764 765 case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: 766 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 767 INTEL_SIP_SMC_FPGA_CONFIG_ADDR, 768 INTEL_SIP_SMC_FPGA_CONFIG_SIZE - 769 INTEL_SIP_SMC_FPGA_CONFIG_ADDR); 770 771 case INTEL_SIP_SMC_FPGA_CONFIG_START: 772 status = intel_fpga_config_start(x1); 773 SMC_RET4(handle, status, 0, 0, 0); 774 775 case INTEL_SIP_SMC_FPGA_CONFIG_WRITE: 776 status = intel_fpga_config_write(x1, x2); 777 SMC_RET4(handle, status, 0, 0, 0); 778 779 case INTEL_SIP_SMC_FPGA_CONFIG_COMPLETED_WRITE: 780 status = intel_fpga_config_completed_write(completed_addr, 781 &retval, &rcv_id); 782 switch (retval) { 783 case 1: 784 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 785 completed_addr[0], 0, 0); 786 787 case 2: 788 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 789 completed_addr[0], 790 completed_addr[1], 0); 791 792 case 3: 793 SMC_RET4(handle, INTEL_SIP_SMC_STATUS_OK, 794 completed_addr[0], 795 completed_addr[1], 796 completed_addr[2]); 797 798 case 0: 799 SMC_RET4(handle, status, 0, 0, 0); 800 801 default: 802 mailbox_clear_response(); 803 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_ERROR); 804 } 805 806 case INTEL_SIP_SMC_REG_READ: 807 status = intel_secure_reg_read(x1, &retval); 808 SMC_RET3(handle, status, retval, x1); 809 810 case INTEL_SIP_SMC_REG_WRITE: 811 status = intel_secure_reg_write(x1, (uint32_t)x2, &retval); 812 SMC_RET3(handle, status, retval, x1); 813 814 case INTEL_SIP_SMC_REG_UPDATE: 815 status = intel_secure_reg_update(x1, (uint32_t)x2, 816 (uint32_t)x3, &retval); 817 SMC_RET3(handle, status, retval, x1); 818 819 case INTEL_SIP_SMC_RSU_STATUS: 820 status = intel_rsu_status(rsu_respbuf, 821 ARRAY_SIZE(rsu_respbuf)); 822 if (status) { 823 SMC_RET1(handle, status); 824 } else { 825 SMC_RET4(handle, rsu_respbuf[0], rsu_respbuf[1], 826 rsu_respbuf[2], rsu_respbuf[3]); 827 } 828 829 case INTEL_SIP_SMC_RSU_UPDATE: 830 status = intel_rsu_update(x1); 831 SMC_RET1(handle, status); 832 833 case INTEL_SIP_SMC_RSU_NOTIFY: 834 status = intel_rsu_notify(x1); 835 SMC_RET1(handle, status); 836 837 case INTEL_SIP_SMC_RSU_RETRY_COUNTER: 838 status = intel_rsu_retry_counter((uint32_t *)rsu_respbuf, 839 ARRAY_SIZE(rsu_respbuf), &retval); 840 if (status) { 841 SMC_RET1(handle, status); 842 } else { 843 SMC_RET2(handle, status, retval); 844 } 845 846 case INTEL_SIP_SMC_RSU_DCMF_VERSION: 847 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 848 ((uint64_t)rsu_dcmf_ver[1] << 32) | rsu_dcmf_ver[0], 849 ((uint64_t)rsu_dcmf_ver[3] << 32) | rsu_dcmf_ver[2]); 850 851 case INTEL_SIP_SMC_RSU_COPY_DCMF_VERSION: 852 status = intel_rsu_copy_dcmf_version(x1, x2); 853 SMC_RET1(handle, status); 854 855 case INTEL_SIP_SMC_RSU_DCMF_STATUS: 856 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, 857 ((uint64_t)rsu_dcmf_stat[3] << 48) | 858 ((uint64_t)rsu_dcmf_stat[2] << 32) | 859 ((uint64_t)rsu_dcmf_stat[1] << 16) | 860 rsu_dcmf_stat[0]); 861 862 case INTEL_SIP_SMC_RSU_COPY_DCMF_STATUS: 863 status = intel_rsu_copy_dcmf_status(x1); 864 SMC_RET1(handle, status); 865 866 case INTEL_SIP_SMC_RSU_MAX_RETRY: 867 SMC_RET2(handle, INTEL_SIP_SMC_STATUS_OK, rsu_max_retry); 868 869 case INTEL_SIP_SMC_RSU_COPY_MAX_RETRY: 870 rsu_max_retry = x1; 871 SMC_RET1(handle, INTEL_SIP_SMC_STATUS_OK); 872 873 case INTEL_SIP_SMC_ECC_DBE: 874 status = intel_ecc_dbe_notification(x1); 875 SMC_RET1(handle, status); 876 877 case INTEL_SIP_SMC_SERVICE_COMPLETED: 878 status = intel_smc_service_completed(x1, x2, x3, &rcv_id, 879 &len_in_resp, &mbox_error); 880 SMC_RET4(handle, status, mbox_error, x1, len_in_resp); 881 882 case INTEL_SIP_SMC_FIRMWARE_VERSION: 883 status = intel_smc_fw_version(&retval); 884 SMC_RET2(handle, status, retval); 885 886 case INTEL_SIP_SMC_MBOX_SEND_CMD: 887 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 888 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 889 status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4, x5, x6, 890 &mbox_status, &len_in_resp); 891 SMC_RET3(handle, status, mbox_status, len_in_resp); 892 893 case INTEL_SIP_SMC_GET_USERCODE: 894 status = intel_smc_get_usercode(&retval); 895 SMC_RET2(handle, status, retval); 896 897 case INTEL_SIP_SMC_FCS_CRYPTION: 898 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 899 900 if (x1 == FCS_MODE_DECRYPT) { 901 status = intel_fcs_decryption(x2, x3, x4, x5, &send_id); 902 } else if (x1 == FCS_MODE_ENCRYPT) { 903 status = intel_fcs_encryption(x2, x3, x4, x5, &send_id); 904 } else { 905 status = INTEL_SIP_SMC_STATUS_REJECTED; 906 } 907 908 SMC_RET3(handle, status, x4, x5); 909 910 case INTEL_SIP_SMC_FCS_CRYPTION_EXT: 911 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 912 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 913 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 914 915 if (x3 == FCS_MODE_DECRYPT) { 916 status = intel_fcs_decryption_ext(x1, x2, x4, x5, x6, 917 (uint32_t *) &x7, &mbox_error); 918 } else if (x3 == FCS_MODE_ENCRYPT) { 919 status = intel_fcs_encryption_ext(x1, x2, x4, x5, x6, 920 (uint32_t *) &x7, &mbox_error); 921 } else { 922 status = INTEL_SIP_SMC_STATUS_REJECTED; 923 } 924 925 SMC_RET4(handle, status, mbox_error, x6, x7); 926 927 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER: 928 status = intel_fcs_random_number_gen(x1, &retval64, 929 &mbox_error); 930 SMC_RET4(handle, status, mbox_error, x1, retval64); 931 932 case INTEL_SIP_SMC_FCS_RANDOM_NUMBER_EXT: 933 status = intel_fcs_random_number_gen_ext(x1, x2, x3, 934 &send_id); 935 SMC_RET1(handle, status); 936 937 case INTEL_SIP_SMC_FCS_SEND_CERTIFICATE: 938 status = intel_fcs_send_cert(x1, x2, &send_id); 939 SMC_RET1(handle, status); 940 941 case INTEL_SIP_SMC_FCS_GET_PROVISION_DATA: 942 status = intel_fcs_get_provision_data(&send_id); 943 SMC_RET1(handle, status); 944 945 case INTEL_SIP_SMC_FCS_CNTR_SET_PREAUTH: 946 status = intel_fcs_cntr_set_preauth(x1, x2, x3, 947 &mbox_error); 948 SMC_RET2(handle, status, mbox_error); 949 950 case INTEL_SIP_SMC_HPS_SET_BRIDGES: 951 status = intel_hps_set_bridges(x1, x2); 952 SMC_RET1(handle, status); 953 954 case INTEL_SIP_SMC_HWMON_READTEMP: 955 status = intel_hwmon_readtemp(x1, &retval); 956 SMC_RET2(handle, status, retval); 957 958 case INTEL_SIP_SMC_HWMON_READVOLT: 959 status = intel_hwmon_readvolt(x1, &retval); 960 SMC_RET2(handle, status, retval); 961 962 case INTEL_SIP_SMC_FCS_PSGSIGMA_TEARDOWN: 963 status = intel_fcs_sigma_teardown(x1, &mbox_error); 964 SMC_RET2(handle, status, mbox_error); 965 966 case INTEL_SIP_SMC_FCS_CHIP_ID: 967 status = intel_fcs_chip_id(&retval, &retval2, &mbox_error); 968 SMC_RET4(handle, status, mbox_error, retval, retval2); 969 970 case INTEL_SIP_SMC_FCS_ATTESTATION_SUBKEY: 971 status = intel_fcs_attestation_subkey(x1, x2, x3, 972 (uint32_t *) &x4, &mbox_error); 973 SMC_RET4(handle, status, mbox_error, x3, x4); 974 975 case INTEL_SIP_SMC_FCS_ATTESTATION_MEASUREMENTS: 976 status = intel_fcs_get_measurement(x1, x2, x3, 977 (uint32_t *) &x4, &mbox_error); 978 SMC_RET4(handle, status, mbox_error, x3, x4); 979 980 case INTEL_SIP_SMC_FCS_GET_ATTESTATION_CERT: 981 status = intel_fcs_get_attestation_cert(x1, x2, 982 (uint32_t *) &x3, &mbox_error); 983 SMC_RET4(handle, status, mbox_error, x2, x3); 984 985 case INTEL_SIP_SMC_FCS_CREATE_CERT_ON_RELOAD: 986 status = intel_fcs_create_cert_on_reload(x1, &mbox_error); 987 SMC_RET2(handle, status, mbox_error); 988 989 case INTEL_SIP_SMC_FCS_OPEN_CS_SESSION: 990 status = intel_fcs_open_crypto_service_session(&retval, &mbox_error); 991 SMC_RET3(handle, status, mbox_error, retval); 992 993 case INTEL_SIP_SMC_FCS_CLOSE_CS_SESSION: 994 status = intel_fcs_close_crypto_service_session(x1, &mbox_error); 995 SMC_RET2(handle, status, mbox_error); 996 997 case INTEL_SIP_SMC_FCS_IMPORT_CS_KEY: 998 status = intel_fcs_import_crypto_service_key(x1, x2, &send_id); 999 SMC_RET1(handle, status); 1000 1001 case INTEL_SIP_SMC_FCS_EXPORT_CS_KEY: 1002 status = intel_fcs_export_crypto_service_key(x1, x2, x3, 1003 (uint32_t *) &x4, &mbox_error); 1004 SMC_RET4(handle, status, mbox_error, x3, x4); 1005 1006 case INTEL_SIP_SMC_FCS_REMOVE_CS_KEY: 1007 status = intel_fcs_remove_crypto_service_key(x1, x2, 1008 &mbox_error); 1009 SMC_RET2(handle, status, mbox_error); 1010 1011 case INTEL_SIP_SMC_FCS_GET_CS_KEY_INFO: 1012 status = intel_fcs_get_crypto_service_key_info(x1, x2, x3, 1013 (uint32_t *) &x4, &mbox_error); 1014 SMC_RET4(handle, status, mbox_error, x3, x4); 1015 1016 case INTEL_SIP_SMC_FCS_GET_DIGEST_INIT: 1017 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1018 status = intel_fcs_get_digest_init(x1, x2, x3, 1019 x4, x5, &mbox_error); 1020 SMC_RET2(handle, status, mbox_error); 1021 1022 case INTEL_SIP_SMC_FCS_GET_DIGEST_UPDATE: 1023 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1024 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1025 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1026 x4, x5, (uint32_t *) &x6, false, 1027 &mbox_error); 1028 SMC_RET4(handle, status, mbox_error, x5, x6); 1029 1030 case INTEL_SIP_SMC_FCS_GET_DIGEST_FINALIZE: 1031 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1032 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1033 status = intel_fcs_get_digest_update_finalize(x1, x2, x3, 1034 x4, x5, (uint32_t *) &x6, true, 1035 &mbox_error); 1036 SMC_RET4(handle, status, mbox_error, x5, x6); 1037 1038 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_UPDATE: 1039 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1040 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1041 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1042 x4, x5, (uint32_t *) &x6, false, 1043 &mbox_error, &send_id); 1044 SMC_RET4(handle, status, mbox_error, x5, x6); 1045 1046 case INTEL_SIP_SMC_FCS_GET_DIGEST_SMMU_FINALIZE: 1047 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1048 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1049 status = intel_fcs_get_digest_smmu_update_finalize(x1, x2, x3, 1050 x4, x5, (uint32_t *) &x6, true, 1051 &mbox_error, &send_id); 1052 SMC_RET4(handle, status, mbox_error, x5, x6); 1053 1054 case INTEL_SIP_SMC_FCS_MAC_VERIFY_INIT: 1055 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1056 status = intel_fcs_mac_verify_init(x1, x2, x3, 1057 x4, x5, &mbox_error); 1058 SMC_RET2(handle, status, mbox_error); 1059 1060 case INTEL_SIP_SMC_FCS_MAC_VERIFY_UPDATE: 1061 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1062 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1063 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1064 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1065 x4, x5, (uint32_t *) &x6, x7, 1066 false, &mbox_error); 1067 SMC_RET4(handle, status, mbox_error, x5, x6); 1068 1069 case INTEL_SIP_SMC_FCS_MAC_VERIFY_FINALIZE: 1070 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1071 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1072 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1073 status = intel_fcs_mac_verify_update_finalize(x1, x2, x3, 1074 x4, x5, (uint32_t *) &x6, x7, 1075 true, &mbox_error); 1076 SMC_RET4(handle, status, mbox_error, x5, x6); 1077 1078 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_UPDATE: 1079 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1080 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1081 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1082 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1083 x4, x5, (uint32_t *) &x6, x7, 1084 false, &mbox_error, &send_id); 1085 SMC_RET4(handle, status, mbox_error, x5, x6); 1086 1087 case INTEL_SIP_SMC_FCS_MAC_VERIFY_SMMU_FINALIZE: 1088 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1089 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1090 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1091 status = intel_fcs_mac_verify_smmu_update_finalize(x1, x2, x3, 1092 x4, x5, (uint32_t *) &x6, x7, 1093 true, &mbox_error, &send_id); 1094 SMC_RET4(handle, status, mbox_error, x5, x6); 1095 1096 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_INIT: 1097 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1098 status = intel_fcs_ecdsa_sha2_data_sign_init(x1, x2, x3, 1099 x4, x5, &mbox_error); 1100 SMC_RET2(handle, status, mbox_error); 1101 1102 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_UPDATE: 1103 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1104 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1105 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1106 x3, x4, x5, (uint32_t *) &x6, false, 1107 &mbox_error); 1108 SMC_RET4(handle, status, mbox_error, x5, x6); 1109 1110 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_FINALIZE: 1111 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1112 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1113 status = intel_fcs_ecdsa_sha2_data_sign_update_finalize(x1, x2, 1114 x3, x4, x5, (uint32_t *) &x6, true, 1115 &mbox_error); 1116 SMC_RET4(handle, status, mbox_error, x5, x6); 1117 1118 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_UPDATE: 1119 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1120 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1121 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1122 x2, x3, x4, x5, (uint32_t *) &x6, false, 1123 &mbox_error, &send_id); 1124 SMC_RET4(handle, status, mbox_error, x5, x6); 1125 1126 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIGN_SMMU_FINALIZE: 1127 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1128 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1129 status = intel_fcs_ecdsa_sha2_data_sign_smmu_update_finalize(x1, 1130 x2, x3, x4, x5, (uint32_t *) &x6, true, 1131 &mbox_error, &send_id); 1132 SMC_RET4(handle, status, mbox_error, x5, x6); 1133 1134 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_INIT: 1135 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1136 status = intel_fcs_ecdsa_hash_sign_init(x1, x2, x3, 1137 x4, x5, &mbox_error); 1138 SMC_RET2(handle, status, mbox_error); 1139 1140 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIGN_FINALIZE: 1141 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1142 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1143 status = intel_fcs_ecdsa_hash_sign_finalize(x1, x2, x3, 1144 x4, x5, (uint32_t *) &x6, &mbox_error); 1145 SMC_RET4(handle, status, mbox_error, x5, x6); 1146 1147 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_INIT: 1148 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1149 status = intel_fcs_ecdsa_hash_sig_verify_init(x1, x2, x3, 1150 x4, x5, &mbox_error); 1151 SMC_RET2(handle, status, mbox_error); 1152 1153 case INTEL_SIP_SMC_FCS_ECDSA_HASH_SIG_VERIFY_FINALIZE: 1154 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1155 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1156 status = intel_fcs_ecdsa_hash_sig_verify_finalize(x1, x2, x3, 1157 x4, x5, (uint32_t *) &x6, &mbox_error); 1158 SMC_RET4(handle, status, mbox_error, x5, x6); 1159 1160 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_INIT: 1161 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1162 status = intel_fcs_ecdsa_sha2_data_sig_verify_init(x1, x2, x3, 1163 x4, x5, &mbox_error); 1164 SMC_RET2(handle, status, mbox_error); 1165 1166 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_UPDATE: 1167 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1168 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1169 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1170 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1171 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1172 x7, false, &mbox_error); 1173 SMC_RET4(handle, status, mbox_error, x5, x6); 1174 1175 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_UPDATE: 1176 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1177 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1178 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1179 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1180 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1181 x7, false, &mbox_error, &send_id); 1182 SMC_RET4(handle, status, mbox_error, x5, x6); 1183 1184 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_SMMU_FINALIZE: 1185 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1186 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1187 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1188 status = intel_fcs_ecdsa_sha2_data_sig_verify_smmu_update_finalize( 1189 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1190 x7, true, &mbox_error, &send_id); 1191 SMC_RET4(handle, status, mbox_error, x5, x6); 1192 1193 case INTEL_SIP_SMC_FCS_ECDSA_SHA2_DATA_SIG_VERIFY_FINALIZE: 1194 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1195 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1196 x7 = SMC_GET_GP(handle, CTX_GPREG_X7); 1197 status = intel_fcs_ecdsa_sha2_data_sig_verify_update_finalize( 1198 x1, x2, x3, x4, x5, (uint32_t *) &x6, 1199 x7, true, &mbox_error); 1200 SMC_RET4(handle, status, mbox_error, x5, x6); 1201 1202 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_INIT: 1203 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1204 status = intel_fcs_ecdsa_get_pubkey_init(x1, x2, x3, 1205 x4, x5, &mbox_error); 1206 SMC_RET2(handle, status, mbox_error); 1207 1208 case INTEL_SIP_SMC_FCS_ECDSA_GET_PUBKEY_FINALIZE: 1209 status = intel_fcs_ecdsa_get_pubkey_finalize(x1, x2, x3, 1210 (uint32_t *) &x4, &mbox_error); 1211 SMC_RET4(handle, status, mbox_error, x3, x4); 1212 1213 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_INIT: 1214 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1215 status = intel_fcs_ecdh_request_init(x1, x2, x3, 1216 x4, x5, &mbox_error); 1217 SMC_RET2(handle, status, mbox_error); 1218 1219 case INTEL_SIP_SMC_FCS_ECDH_REQUEST_FINALIZE: 1220 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1221 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1222 status = intel_fcs_ecdh_request_finalize(x1, x2, x3, 1223 x4, x5, (uint32_t *) &x6, &mbox_error); 1224 SMC_RET4(handle, status, mbox_error, x5, x6); 1225 1226 case INTEL_SIP_SMC_FCS_AES_CRYPT_INIT: 1227 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1228 status = intel_fcs_aes_crypt_init(x1, x2, x3, x4, x5, 1229 &mbox_error); 1230 SMC_RET2(handle, status, mbox_error); 1231 1232 case INTEL_SIP_SMC_FCS_AES_CRYPT_UPDATE: 1233 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1234 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1235 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1236 x5, x6, false, &send_id); 1237 SMC_RET1(handle, status); 1238 1239 case INTEL_SIP_SMC_FCS_AES_CRYPT_FINALIZE: 1240 x5 = SMC_GET_GP(handle, CTX_GPREG_X5); 1241 x6 = SMC_GET_GP(handle, CTX_GPREG_X6); 1242 status = intel_fcs_aes_crypt_update_finalize(x1, x2, x3, x4, 1243 x5, x6, true, &send_id); 1244 SMC_RET1(handle, status); 1245 1246 case INTEL_SIP_SMC_GET_ROM_PATCH_SHA384: 1247 status = intel_fcs_get_rom_patch_sha384(x1, &retval64, 1248 &mbox_error); 1249 SMC_RET4(handle, status, mbox_error, x1, retval64); 1250 1251 case INTEL_SIP_SMC_SVC_VERSION: 1252 SMC_RET3(handle, INTEL_SIP_SMC_STATUS_OK, 1253 SIP_SVC_VERSION_MAJOR, 1254 SIP_SVC_VERSION_MINOR); 1255 1256 case INTEL_SIP_SMC_SEU_ERR_STATUS: 1257 status = intel_sdm_seu_err_read(seu_respbuf, 1258 ARRAY_SIZE(seu_respbuf)); 1259 if (status) { 1260 SMC_RET1(handle, status); 1261 } else { 1262 SMC_RET3(handle, seu_respbuf[0], seu_respbuf[1], seu_respbuf[2]); 1263 } 1264 1265 case INTEL_SIP_SMC_SAFE_INJECT_SEU_ERR: 1266 status = intel_sdm_safe_inject_seu_err((uint32_t *)&x1, (uint32_t)x2); 1267 SMC_RET1(handle, status); 1268 1269 default: 1270 return socfpga_sip_handler(smc_fid, x1, x2, x3, x4, 1271 cookie, handle, flags); 1272 } 1273 } 1274 1275 uintptr_t sip_smc_handler(uint32_t smc_fid, 1276 u_register_t x1, 1277 u_register_t x2, 1278 u_register_t x3, 1279 u_register_t x4, 1280 void *cookie, 1281 void *handle, 1282 u_register_t flags) 1283 { 1284 uint32_t cmd = smc_fid & INTEL_SIP_SMC_CMD_MASK; 1285 1286 if (cmd >= INTEL_SIP_SMC_CMD_V2_RANGE_BEGIN && 1287 cmd <= INTEL_SIP_SMC_CMD_V2_RANGE_END) { 1288 return sip_smc_handler_v2(smc_fid, x1, x2, x3, x4, 1289 cookie, handle, flags); 1290 } else { 1291 return sip_smc_handler_v1(smc_fid, x1, x2, x3, x4, 1292 cookie, handle, flags); 1293 } 1294 } 1295 1296 DECLARE_RT_SVC( 1297 socfpga_sip_svc, 1298 OEN_SIP_START, 1299 OEN_SIP_END, 1300 SMC_TYPE_FAST, 1301 NULL, 1302 sip_smc_handler 1303 ); 1304 1305 DECLARE_RT_SVC( 1306 socfpga_sip_svc_std, 1307 OEN_SIP_START, 1308 OEN_SIP_END, 1309 SMC_TYPE_YIELD, 1310 NULL, 1311 sip_smc_handler 1312 ); 1313