1 /* 2 * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <common/bl_common.h> 10 #include <drivers/arm/pl061_gpio.h> 11 #include <lib/gpt_rme/gpt_rme.h> 12 #include <plat/common/platform.h> 13 14 #include "qemu_private.h" 15 16 #define MAP_BL31_TOTAL MAP_REGION_FLAT( \ 17 BL31_BASE, \ 18 BL31_END - BL31_BASE, \ 19 MT_MEMORY | MT_RW | EL3_PAS) 20 #define MAP_BL31_RO MAP_REGION_FLAT( \ 21 BL_CODE_BASE, \ 22 BL_CODE_END - BL_CODE_BASE, \ 23 MT_CODE | EL3_PAS), \ 24 MAP_REGION_FLAT( \ 25 BL_RO_DATA_BASE, \ 26 BL_RO_DATA_END \ 27 - BL_RO_DATA_BASE, \ 28 MT_RO_DATA | EL3_PAS) 29 30 #if USE_COHERENT_MEM 31 #define MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ 32 BL_COHERENT_RAM_BASE, \ 33 BL_COHERENT_RAM_END \ 34 - BL_COHERENT_RAM_BASE, \ 35 MT_DEVICE | MT_RW | EL3_PAS) 36 #endif 37 38 /* 39 * Placeholder variables for copying the arguments that have been passed to 40 * BL3-1 from BL2. 41 */ 42 static entry_point_info_t bl32_image_ep_info; 43 static entry_point_info_t bl33_image_ep_info; 44 #if ENABLE_RME 45 static entry_point_info_t rmm_image_ep_info; 46 #endif 47 48 /******************************************************************************* 49 * Perform any BL3-1 early platform setup. Here is an opportunity to copy 50 * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before 51 * they are lost (potentially). This needs to be done before the MMU is 52 * initialized so that the memory layout can be used while creating page 53 * tables. BL2 has flushed this information to memory, so we are guaranteed 54 * to pick up good data. 55 ******************************************************************************/ 56 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 57 u_register_t arg2, u_register_t arg3) 58 { 59 /* Initialize the console to provide early debug support */ 60 qemu_console_init(); 61 62 /* Platform names have to be lowercase. */ 63 #ifdef PLAT_qemu_sbsa 64 sip_svc_init(); 65 #endif 66 67 /* 68 * Check params passed from BL2 69 */ 70 bl_params_t *params_from_bl2 = (bl_params_t *)arg0; 71 72 assert(params_from_bl2); 73 assert(params_from_bl2->h.type == PARAM_BL_PARAMS); 74 assert(params_from_bl2->h.version >= VERSION_2); 75 76 bl_params_node_t *bl_params = params_from_bl2->head; 77 78 /* 79 * Copy BL33, BL32 and RMM (if present), entry point information. 80 * They are stored in Secure RAM, in BL2's address space. 81 */ 82 while (bl_params) { 83 if (bl_params->image_id == BL32_IMAGE_ID) 84 bl32_image_ep_info = *bl_params->ep_info; 85 86 #if ENABLE_RME 87 if (bl_params->image_id == RMM_IMAGE_ID) 88 rmm_image_ep_info = *bl_params->ep_info; 89 #endif 90 91 if (bl_params->image_id == BL33_IMAGE_ID) 92 bl33_image_ep_info = *bl_params->ep_info; 93 94 bl_params = bl_params->next_params_info; 95 } 96 97 if (!bl33_image_ep_info.pc) 98 panic(); 99 #if ENABLE_RME 100 if (!rmm_image_ep_info.pc) 101 panic(); 102 #endif 103 } 104 105 void bl31_plat_arch_setup(void) 106 { 107 const mmap_region_t bl_regions[] = { 108 MAP_BL31_TOTAL, 109 MAP_BL31_RO, 110 #if USE_COHERENT_MEM 111 MAP_BL_COHERENT_RAM, 112 #endif 113 #if ENABLE_RME 114 MAP_GPT_L0_REGION, 115 MAP_GPT_L1_REGION, 116 MAP_RMM_SHARED_MEM, 117 #endif 118 {0} 119 }; 120 121 setup_page_tables(bl_regions, plat_qemu_get_mmap()); 122 123 enable_mmu_el3(0); 124 125 #if ENABLE_RME 126 /* 127 * Initialise Granule Protection library and enable GPC for the primary 128 * processor. The tables have already been initialized by a previous BL 129 * stage, so there is no need to provide any PAS here. This function 130 * sets up pointers to those tables. 131 */ 132 if (gpt_runtime_init() < 0) { 133 ERROR("gpt_runtime_init() failed!\n"); 134 panic(); 135 } 136 #endif /* ENABLE_RME */ 137 138 } 139 140 static void qemu_gpio_init(void) 141 { 142 #ifdef SECURE_GPIO_BASE 143 pl061_gpio_init(); 144 pl061_gpio_register(SECURE_GPIO_BASE, 0); 145 #endif 146 } 147 148 void bl31_platform_setup(void) 149 { 150 plat_qemu_gic_init(); 151 qemu_gpio_init(); 152 } 153 154 unsigned int plat_get_syscnt_freq2(void) 155 { 156 return SYS_COUNTER_FREQ_IN_TICKS; 157 } 158 159 /******************************************************************************* 160 * Return a pointer to the 'entry_point_info' structure of the next image 161 * for the security state specified. BL3-3 corresponds to the non-secure 162 * image type while BL3-2 corresponds to the secure image type. A NULL 163 * pointer is returned if the image does not exist. 164 ******************************************************************************/ 165 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) 166 { 167 entry_point_info_t *next_image_info; 168 169 assert(sec_state_is_valid(type)); 170 if (type == NON_SECURE) { 171 next_image_info = &bl33_image_ep_info; 172 } 173 #if ENABLE_RME 174 else if (type == REALM) { 175 next_image_info = &rmm_image_ep_info; 176 } 177 #endif 178 else { 179 next_image_info = &bl32_image_ep_info; 180 } 181 182 /* 183 * None of the images on the ARM development platforms can have 0x0 184 * as the entrypoint 185 */ 186 if (next_image_info->pc) 187 return next_image_info; 188 else 189 return NULL; 190 } 191