xref: /rk3399_ARM-atf/plat/qemu/common/qemu_bl31_setup.c (revision 6cd113fe06fdaa67a8457391eb6bcffd295f87fd)
1 /*
2  * Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <assert.h>
8 
9 #include <common/bl_common.h>
10 #include <drivers/arm/pl061_gpio.h>
11 #include <lib/gpt_rme/gpt_rme.h>
12 #include <plat/common/platform.h>
13 
14 #include "qemu_private.h"
15 
16 #define MAP_BL31_TOTAL		MAP_REGION_FLAT(			\
17 					BL31_BASE,			\
18 					BL31_END - BL31_BASE,		\
19 					MT_MEMORY | MT_RW | EL3_PAS)
20 #define MAP_BL31_RO		MAP_REGION_FLAT(			\
21 					BL_CODE_BASE,			\
22 					BL_CODE_END - BL_CODE_BASE,	\
23 					MT_CODE | EL3_PAS),		\
24 				MAP_REGION_FLAT(			\
25 					BL_RO_DATA_BASE,		\
26 					BL_RO_DATA_END			\
27 						- BL_RO_DATA_BASE,	\
28 					MT_RO_DATA | EL3_PAS)
29 
30 #if USE_COHERENT_MEM
31 #define MAP_BL_COHERENT_RAM	MAP_REGION_FLAT(			\
32 					BL_COHERENT_RAM_BASE,		\
33 					BL_COHERENT_RAM_END		\
34 						- BL_COHERENT_RAM_BASE,	\
35 					MT_DEVICE | MT_RW | EL3_PAS)
36 #endif
37 
38 /*
39  * Placeholder variables for copying the arguments that have been passed to
40  * BL3-1 from BL2.
41  */
42 static entry_point_info_t bl32_image_ep_info;
43 static entry_point_info_t bl33_image_ep_info;
44 
45 /*******************************************************************************
46  * Perform any BL3-1 early platform setup.  Here is an opportunity to copy
47  * parameters passed by the calling EL (S-EL1 in BL2 & EL3 in BL1) before
48  * they are lost (potentially). This needs to be done before the MMU is
49  * initialized so that the memory layout can be used while creating page
50  * tables. BL2 has flushed this information to memory, so we are guaranteed
51  * to pick up good data.
52  ******************************************************************************/
53 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
54 				u_register_t arg2, u_register_t arg3)
55 {
56 	/* Initialize the console to provide early debug support */
57 	qemu_console_init();
58 
59 /* Platform names have to be lowercase. */
60 #ifdef PLAT_qemu_sbsa
61 	sip_svc_init();
62 #endif
63 
64 	/*
65 	 * Check params passed from BL2
66 	 */
67 	bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
68 
69 	assert(params_from_bl2);
70 	assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
71 	assert(params_from_bl2->h.version >= VERSION_2);
72 
73 	bl_params_node_t *bl_params = params_from_bl2->head;
74 
75 	/*
76 	 * Copy BL33 and BL32 (if present), entry point information.
77 	 * They are stored in Secure RAM, in BL2's address space.
78 	 */
79 	while (bl_params) {
80 		if (bl_params->image_id == BL32_IMAGE_ID)
81 			bl32_image_ep_info = *bl_params->ep_info;
82 
83 		if (bl_params->image_id == BL33_IMAGE_ID)
84 			bl33_image_ep_info = *bl_params->ep_info;
85 
86 		bl_params = bl_params->next_params_info;
87 	}
88 
89 	if (!bl33_image_ep_info.pc)
90 		panic();
91 }
92 
93 void bl31_plat_arch_setup(void)
94 {
95 	const mmap_region_t bl_regions[] = {
96 		MAP_BL31_TOTAL,
97 		MAP_BL31_RO,
98 #if USE_COHERENT_MEM
99 		MAP_BL_COHERENT_RAM,
100 #endif
101 #if ENABLE_RME
102 		MAP_GPT_L0_REGION,
103 		MAP_GPT_L1_REGION,
104 		MAP_RMM_SHARED_MEM,
105 #endif
106 		{0}
107 	};
108 
109 	setup_page_tables(bl_regions, plat_qemu_get_mmap());
110 
111 	enable_mmu_el3(0);
112 
113 #if ENABLE_RME
114 	/*
115 	 * Initialise Granule Protection library and enable GPC for the primary
116 	 * processor. The tables have already been initialized by a previous BL
117 	 * stage, so there is no need to provide any PAS here. This function
118 	 * sets up pointers to those tables.
119 	 */
120 	if (gpt_runtime_init() < 0) {
121 		ERROR("gpt_runtime_init() failed!\n");
122 		panic();
123 	}
124 #endif /* ENABLE_RME */
125 
126 }
127 
128 static void qemu_gpio_init(void)
129 {
130 #ifdef SECURE_GPIO_BASE
131 	pl061_gpio_init();
132 	pl061_gpio_register(SECURE_GPIO_BASE, 0);
133 #endif
134 }
135 
136 void bl31_platform_setup(void)
137 {
138 	plat_qemu_gic_init();
139 	qemu_gpio_init();
140 }
141 
142 unsigned int plat_get_syscnt_freq2(void)
143 {
144 	return SYS_COUNTER_FREQ_IN_TICKS;
145 }
146 
147 /*******************************************************************************
148  * Return a pointer to the 'entry_point_info' structure of the next image
149  * for the security state specified. BL3-3 corresponds to the non-secure
150  * image type while BL3-2 corresponds to the secure image type. A NULL
151  * pointer is returned if the image does not exist.
152  ******************************************************************************/
153 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
154 {
155 	entry_point_info_t *next_image_info;
156 
157 	assert(sec_state_is_valid(type));
158 	next_image_info = (type == NON_SECURE)
159 			? &bl33_image_ep_info : &bl32_image_ep_info;
160 	/*
161 	 * None of the images on the ARM development platforms can have 0x0
162 	 * as the entrypoint
163 	 */
164 	if (next_image_info->pc)
165 		return next_image_info;
166 	else
167 		return NULL;
168 }
169