Merge "feat(fvp): remove left-over RSS usage" into integration

feat(fvp): remove left-over RSS usage

Remove any residual RSS usage in the FVP platform, complementing the
changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.

Signed-off-by: Manish V B

feat(fvp): remove left-over RSS usage

Remove any residual RSS usage in the FVP platform, complementing the
changes made in commit dea307fd6cca2dad56867e757804224a8654bc38.

Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>
Change-Id: I9ced272503456361610ec0c7783d270349233926

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fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything poss

fix(qemu): disable FEAT_SB

qemu/qemu_sbsa platforms support wide selection of cpu cores. From
Cortex-A57 (v8.0) to Neoverse-N2 (v9.0) one. Only the last one (and
'max' which supports everything possible) supports FEAT_SB.

Runtime check for ENABLE_FEAT_SB does not work in our case and we want
to have working platform.

Change-Id: Ic27d5af20ad76ae44c4211d28694e91ec62bddc1
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>

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Merge changes from topic "ADD_DELAY_IN_POLLING_SCMI" into integration

* changes:
fix(scmi): induce a delay in monitoring SCMI channel status
feat(css): initialise generic timer early in the boot

Merge changes from topic "stm32mp2-usb" into integration

* changes:
feat(stm32mp2): add STM32MP_USB_PROGRAMMER compilation
refactor(st): move macros to common folder
refactor(stm32mp1): remove

Merge changes from topic "stm32mp2-usb" into integration

* changes:
feat(stm32mp2): add STM32MP_USB_PROGRAMMER compilation
refactor(st): move macros to common folder
refactor(stm32mp1): remove unused macros
fix(usb): add missing include

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Merge changes from topic "od/sme" into integration

* changes:
fix(fvp): permit enabling SME for SPD=spmd
feat(spmd): pass SMCCCv1.3 SVE hint to lower EL

fix(fvp): permit enabling SME for SPD=spmd

Essentially revert [1] to permit specifying SME support along with
SPD=spmd on FVP platform.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmwar

fix(fvp): permit enabling SME for SPD=spmd

Essentially revert [1] to permit specifying SME support along with
SPD=spmd on FVP platform.

[1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20764

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Change-Id: Iab15d5a4c966b9f5b265ccde6711765e242abeaa

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Merge changes from topic "ja/spm_rme" into integration

* changes:
docs: change FVP argument in RME configuration
feat(fvp): added calls to unprotect/protect memory

Merge changes from topic "jc/psci_spe" into integration

* changes:
fix(spe): invoke spe_disable during power domain off/suspend
feat(psci): add psci_do_manage_extensions API
fix(arm_fpga): hal

Merge changes from topic "jc/psci_spe" into integration

* changes:
fix(spe): invoke spe_disable during power domain off/suspend
feat(psci): add psci_do_manage_extensions API
fix(arm_fpga): halve number of PEs per core

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build: use toolchain identifiers in conditions

The toolchain refactor change introduces the `${toolchain}-${tool}-id`
variables, which provide identifiers for all of the toolchain tools used
by the

build: use toolchain identifiers in conditions

The toolchain refactor change introduces the `${toolchain}-${tool}-id`
variables, which provide identifiers for all of the toolchain tools used
by the build system. This change replaces the various conditions that
are in use to identify these tools based on the path with a standard set
of comparisons against these new identifier variables.

Change-Id: Ib60e592359fa6e415c19a012e68d660f87436ca7
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: use new toolchain variables for tools

This change migrates the values of `CC`, `CPP`, `AS` and other toolchain
variables to the new `$(toolchain)-$(tool)` variables, which were
introduced by

build: use new toolchain variables for tools

This change migrates the values of `CC`, `CPP`, `AS` and other toolchain
variables to the new `$(toolchain)-$(tool)` variables, which were
introduced by the toolchain refactor patch. These variables should be
equivalent to the values that they're replacing.

Change-Id: I644fe4ce82ef1894bed129ddb4b6ab94fb04985d
Signed-off-by: Chris Kay <chris.kay@arm.com>

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build: refactor toolchain detection

This change refactors how we identify the toolchain, with the ultimate
aim of eventually cleaning up the various mechanisms that we employ to
configure default to

build: refactor toolchain detection

This change refactors how we identify the toolchain, with the ultimate
aim of eventually cleaning up the various mechanisms that we employ to
configure default tools, identify the tools in use, and configure
toolchain flags.

To do this, we introduce three new concepts in this change:

- Toolchain identifiers,
- Tool class identifiers, and
- Tool identifiers.

Toolchain identifiers identify a configurable chain of tools targeting
one platform/machine/architecture. Today, these are:

- The host machine, which receives the `host` identifier,
- The AArch32 architecture, which receives the `aarch32` identifier, and
- The AArch64 architecture, which receivs the `aarch64` identifier.

The tools in a toolchain may come from different vendors, and are not
necessarily expected to come from one single toolchain distribution. In
most cases it is perfectly valid to mix tools from different toolchain
distributions, with some exceptions (notably, link-time optimization
generally requires the compiler and the linker to be aligned).

Tool class identifiers identify a class (or "role") of a tool. C
compilers, assemblers and linkers are all examples of tool classes.

Tool identifiers identify a specific tool recognized and supported by
the build system. Every tool that can make up a part of a toolchain must
receive a tool identifier.

These new identifiers can be used to retrieve information about the
toolchain in a more standardized fashion.

For example, logic in a Makefile that should only execute when the C
compiler is GNU GCC can now check the tool identifier for the C compiler
in the relevant toolchain:

ifeq ($($(ARCH)-cc-id),gnu-gcc)
...
endif

Change-Id: Icc23e43aaa32f4fd01d8187c5202f5012a634e7c
Signed-off-by: Chris Kay <chris.kay@arm.com>

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feat(fvp): added calls to unprotect/protect memory

Added SiP calls to FVP platform to protect/unprotect a
memory range.
These leverage rme features to change the PAS of a given
memory range from non

feat(fvp): added calls to unprotect/protect memory

Added SiP calls to FVP platform to protect/unprotect a
memory range.
These leverage rme features to change the PAS of a given
memory range from non-secure to secure.

The mentioned call is leveraged by the SPMC in the memory
sharing flow, when memory is shared from the normal world
onto the secure world.

More details in the SPM related patches.

Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: J-Alves <joao.alves@arm.com>
Change-Id: Iaf15d8603a549d247ffb1fc14c16bfb94d0e178a

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feat(stm32mp2): add STM32MP_USB_PROGRAMMER compilation

Add minimal compilation step when enabling STM32MP_USB_PROGRAMMER flag
on STM32MP2. Add DWL_BUFFER_BASE in platform.mk and the compilation
of t

feat(stm32mp2): add STM32MP_USB_PROGRAMMER compilation

Add minimal compilation step when enabling STM32MP_USB_PROGRAMMER flag
on STM32MP2. Add DWL_BUFFER_BASE in platform.mk and the compilation
of the new file plat/st/stm32mp2/stm32mp2_usb_dfu.c (just stubs for
the moment).

Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I8891ff23ddc3d40d7477ada3e49e439dd8af8316

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refactor(st): move macros to common folder

As these definitions will be the same for STM32MP1 and STM32MP2, move
PLATFORM_MTD_MAX_PAGE_SIZE and DWL_BUFFER_SIZE macro definition to the
file: plat/st/

refactor(st): move macros to common folder

As these definitions will be the same for STM32MP1 and STM32MP2, move
PLATFORM_MTD_MAX_PAGE_SIZE and DWL_BUFFER_SIZE macro definition to the
file: plat/st/common/include/stm32mp_common.h

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I480669d009d15fec753298f47b136e34fa240132

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refactor(stm32mp1): remove unused macros

PLAT_STM32MP_NS_IMAGE_OFFSET and PLAT_EMMC_BOOT_SSBL_OFFSET macros should
have been removed with patch [1].

[1] 981b9dcb87 ("refactor(stm32mp1): remove STM3

refactor(stm32mp1): remove unused macros

PLAT_STM32MP_NS_IMAGE_OFFSET and PLAT_EMMC_BOOT_SSBL_OFFSET macros should
have been removed with patch [1].

[1] 981b9dcb87 ("refactor(stm32mp1): remove STM32MP_USE_STM32IMAGE")

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: Ice98c43c0257041226525199be06134fde8466c5

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Revert "fix(ti): do not take system power reference in bl31_platform_setup()"

The workaround that we required to get over the timing issue with our
Device Manager is fixed in [0], revert the workaro

Revert "fix(ti): do not take system power reference in bl31_platform_setup()"

The workaround that we required to get over the timing issue with our
Device Manager is fixed in [0], revert the workaround as it is no longer
required.

[0]: https://git.ti.com/cgit/processor-firmware/ti-linux-firmware/commit?id=9ad862b528112f7bc26d80668fbb9b38521cddf9

This reverts commit 9977948112d732935362a3fe8518e3b2e4b7f6b7. It also
adds a check to make this backward compatible.

Change-Id: Icf10f9df9558de1ae7ba6f5f586485111aac4f8d
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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refactor(ti): remove ti_sci_init function

ti_sci_get_revision handles getting the firmware version and ti_sci_init
is just a wrapper around it with no added benefit.

Refactor the ti_sci_get_revisio

refactor(ti): remove ti_sci_init function

ti_sci_get_revision handles getting the firmware version and ti_sci_init
is just a wrapper around it with no added benefit.

Refactor the ti_sci_get_revision to give the version information and
remove ti_sci_init wrapper.

Change-Id: I39184af5b00bedc8b9220533f1ddac3b6672d2f1
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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fix(spe): invoke spe_disable during power domain off/suspend

spe_disable function, disables profiling and flushes all the buffers and
hence needs to be called on power-off/suspend path.
It needs to

fix(spe): invoke spe_disable during power domain off/suspend

spe_disable function, disables profiling and flushes all the buffers and
hence needs to be called on power-off/suspend path.
It needs to be invoked as SPE feature writes to memory as part of
regular operation and not disabling before exiting coherency
could potentially cause issues.

Currently, this is handled only for the FVP. Other platforms need
to replicate this behaviour and is covered as part of this patch.

Calling it from generic psci library code, before the platform specific
actions to turn off the CPUs, will make it applicable for all the
platforms which have ported the PSCI library.

Change-Id: I90b24c59480357e2ebfa3dfc356c719ca935c13d
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>

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fix(arm_fpga): halve number of PEs per core

When creating the Arm FPGA platform, we had plenty of memory available,
so assigned a generous four PEs per core for the potential CPU topology.
In realit

fix(arm_fpga): halve number of PEs per core

When creating the Arm FPGA platform, we had plenty of memory available,
so assigned a generous four PEs per core for the potential CPU topology.
In reality we barely see implementations with two PEs per core, and
didn't have four at all so far.

With some design changes we now include more data per CPU type, and
since the Arm FPGA build supports many cores (and determines the correct
one at runtime), we run out of memory with certain build options.

Since we don't really need four PEs per core, just halve that number, to
reduce our memory footprint without sacrificing functionality.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Change-Id: Ieb37ccc9f362b10ff0ce038f72efca21512a71cb

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feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detaile

feat(fvp): delegate FFH RAS handling to SP

This setup helps to mimic an end-to-end RAS handling flow inspired
by real world design with a dedicated RAS secure partition managed
by SPMC.

The detailed steps are documented as comments in the relevant source
files introduced in this patch.

Change-Id: I97737c66649f6e49840fa0bdf2e0af4fb6b08fc7
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

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feat(css): initialise generic timer early in the boot

Initialize generic delay timer to enable its use to insert delays
in execution paths as required.

Change-Id: I52232796f20d9692f0115d5e5395451a5

feat(css): initialise generic timer early in the boot

Initialize generic delay timer to enable its use to insert delays
in execution paths as required.

Change-Id: I52232796f20d9692f0115d5e5395451a54b489c6
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>

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fix(k3): increment while reading trail bytes

The trail bytes from the secure proxy driver were being overwritten,
increase the count each time to not overwrite the existing data and not
get the end

fix(k3): increment while reading trail bytes

The trail bytes from the secure proxy driver were being overwritten,
increase the count each time to not overwrite the existing data and not
get the end data corrupted from secure proxy.

Fixes: d76fdd33e011 ("ti: k3: drivers: Add Secure Proxy driver")

Change-Id: I8e23f8b6959da886d6ab43049746f78765ae1766
Signed-off-by: Manorit Chawdhry <m-chawdhry@ti.com>

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Merge changes I509b7bc5,Ibd36ea5c into integration

* changes:
fix(fconf): boot fails using ARM_ARCH_MINOR=8
fix(libc): add memcpy_s source file to libc_asm mk

Merge "feat(stm32mp1): only fuse monotonic counter on closed devices" into integration