1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 12 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 13 #define PLATFORM_LINKER_ARCH aarch64 14 15 #define PLATFORM_STACK_SIZE 0x400 16 #define CACHE_WRITEBACK_GRANULE 64 17 18 #define PLAT_PRIMARY_CPU 0x0 19 #define PLATFORM_MAX_CPU_PER_CLUSTER 2 20 #define PLATFORM_CLUSTER_COUNT 1 21 #define PLATFORM_CORE_COUNT 2 22 #define PLATFORM_CLUSTER0_CORE_COUNT 2 23 #define PLATFORM_CLUSTER1_CORE_COUNT 0 24 25 #define IMX_PWR_LVL0 MPIDR_AFFLVL0 26 #define IMX_PWR_LVL1 MPIDR_AFFLVL1 27 #define IMX_PWR_LVL2 MPIDR_AFFLVL2 28 29 #define PWR_DOMAIN_AT_MAX_LVL U(1) 30 #define PLAT_MAX_PWR_LVL U(2) 31 32 #define PLAT_SLEEP_RET_STATE U(1) 33 #define PLAT_DEEP_SLEEP_RET_STATE U(2) 34 #define PLAT_MAX_RET_STATE U(3) 35 36 #define PLAT_POWER_DOWN_OFF_STATE U(4) 37 #define PLAT_DEEP_POWER_DOWN_STATE U(5) 38 #define PLAT_MAX_OFF_STATE U(6) 39 40 #define BL31_BASE 0x20040000 41 #define BL31_LIMIT 0x20070000 42 43 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32) 44 #define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32) 45 46 #define MAX_XLAT_TABLES 8 47 #define MAX_MMAP_REGIONS 9 48 49 #define PLAT_GICD_BASE U(0x2d400000) 50 #define PLAT_GICR_BASE U(0x2d440000) 51 #define DEVICE0_BASE U(0x20000000) 52 #define DEVICE0_SIZE U(0x10000000) 53 #define DEVICE1_BASE U(0x30000000) 54 #define DEVICE1_SIZE U(0x10000000) 55 #define DEVICE2_BASE U(0x80000000) 56 #define DEVICE2_SIZE U(0x01000000) 57 #define IMX_LPUART4_BASE U(0x29390000) 58 #define IMX_LPUART5_BASE U(0x293a0000) 59 #define IMX_LPUART_BASE IMX_LPUART5_BASE 60 #define IMX_CAAM_BASE U(0x292e0000) 61 #define IMX_BOOT_UART_CLK_IN_HZ 24000000 62 #define IMX_CONSOLE_BAUDRATE 115200 63 64 #define IMX_CGC1_BASE U(0x292c0000) 65 #define IMX_PCC3_BASE U(0x292d0000) 66 #define IMX_PCC4_BASE U(0x29800000) 67 #define IMX_SIM2_BASE U(0x2da50000) 68 #define IMX_CGC2_BASE U(0x2da60000) 69 #define IMX_PCC5_BASE U(0x2da70000) 70 #define IMX_MU0B_BASE U(0x29220000) 71 #define IMX_CMC1_BASE U(0x29240000) 72 #define IMX_WUU1_BASE U(0x29260000) 73 #define IMX_SIM1_BASE U(0x29290000) 74 #define IMX_GPIOD_BASE U(0x2e200000) 75 #define IMX_GPIOE_BASE U(0x2d000000) 76 #define IMX_GPIOF_BASE U(0x2d010000) 77 #define IMX_WDOG3_BASE U(0x292a0000) 78 #define IMX_TPM5_BASE U(0x29340000) 79 80 #define SRAM0_BASE U(0x2201F000) 81 82 #define IOMUXC_PTD_PCR_BASE U(0x298c0000) 83 #define IOMUXC_PTE_PCR_BASE U(0x298c0080) 84 #define IOMUXC_PTF_PCR_BASE U(0x298c0100) 85 #define IOMUXC_PSMI_BASE0 U(0x298c0800) 86 #define IOMUXC_PSMI_BASE1 U(0x298c0838) 87 #define IOMUXC_PSMI_BASE2 U(0x298c0954) 88 #define IOMUXC_PSMI_BASE3 U(0x298c0994) 89 #define IOMUXC_PSMI_BASE4 U(0x298c0a58) 90 91 #define IMX_ROM_ENTRY U(0x1000) 92 #define COUNTER_FREQUENCY 1000000 93 94 #define PLAT_NS_IMAGE_OFFSET 0x80200000 95 96 #define BL31_NOBITS_BASE 0x20058000 97 #define BL31_NOBITS_LIMIT 0x2006d000 98 99 #define BL31_RWDATA_BASE 0x2006d000 100 #define BL31_RWDATA_LIMIT 0x20070000 101 102 #define BL32_FDT_OVERLAY_ADDR 0x9d000000 103 104 #ifdef SPD_trusty 105 #define IMX_TRUSTY_STACK_SIZE 0x100 106 #endif 107 108 /* system memory map define */ 109 #define DEVICE0_MAP MAP_REGION_FLAT(DEVICE0_BASE, DEVICE0_SIZE, MT_DEVICE | MT_RW) 110 #define DEVICE1_MAP MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, MT_DEVICE | MT_RW) 111 /* Map partial DRAM space for DRAM low-power mode control */ 112 #define DEVICE2_MAP MAP_REGION_FLAT(DEVICE2_BASE, DEVICE2_SIZE, MT_DEVICE | MT_RW) 113 /* MU and FSB */ 114 #define ELE_MAP MAP_REGION_FLAT(0x27010000, 0x20000, MT_DEVICE | MT_RW | MT_NS) 115 #define SEC_SIM_MAP MAP_REGION_FLAT(0x2802B000, 0x1000, MT_DEVICE | MT_RW | MT_NS) /* SEC SIM */ 116 /* For SCMI shared memory region */ 117 #define SRAM0_MAP MAP_REGION_FLAT(SRAM0_BASE, 0x1000, MT_RW | MT_DEVICE) 118 119 #endif /* PLATFORM_DEF_H */ 120