1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <drivers/delay_timer.h> 11 #include <lib/mmio.h> 12 13 #include <plat_imx8.h> 14 #include <xrdc.h> 15 16 #define PCC_PR BIT(31) 17 #define PFD_VALID_MASK U(0x40404040) 18 19 #define S400_MU_BASE U(0x27020000) 20 #define S400_MU_RSR (S400_MU_BASE + 0x12c) 21 #define S400_MU_TRx(i) (S400_MU_BASE + 0x200 + (i) * 4) 22 #define S400_MU_RRx(i) (S400_MU_BASE + 0x280 + (i) * 4) 23 24 /* 25 * need to re-init the PLL, CGC1, PCC, CMC, XRDC, SIM, GPIO etc. 26 * init the PLL &PFD first, then switch the CA35 clock to PLL for 27 * performance consideration, restore other bus fabric clock. 28 */ 29 30 extern void imx8ulp_caam_init(void); 31 extern void upower_wait_resp(void); 32 extern void dram_enter_retention(void); 33 extern void dram_exit_retention(void); 34 35 struct plat_gic_ctx imx_gicv3_ctx; 36 static uint32_t cmc1_pmprot; 37 static uint32_t cmc1_srie; 38 39 /* TPM5: global timer */ 40 static uint32_t tpm5[3]; 41 42 static uint32_t wdog3[2]; 43 44 /* CGC1 PLL2 */ 45 uint32_t pll2[][2] = { 46 {0x292c0510, 0x0}, {0x292c0518, 0x0}, {0x292c051c, 0x0}, 47 {0x292c0520, 0x0}, {0x292c0500, 0x0}, 48 }; 49 50 /* CGC1 PLL3 */ 51 uint32_t pll3[][2] = { 52 {0x292c0604, 0x0}, {0x292c0608, 0x0}, {0x292c060c, 0x0}, 53 {0x292c0610, 0x0}, {0x292c0618, 0x0}, {0x292c061c, 0x0}, 54 {0x292c0620, 0x0}, {0x292c0624, 0x0}, {0x292c0600, 0x0}, 55 {0x292c0614, 0x0}, 56 }; 57 58 /* CGC1 others */ 59 uint32_t cgc1[][2] = { 60 {0x292c0014, 0x0}, {0x292c0034, 0x0}, {0x292c0038, 0x0}, 61 {0x292c0108, 0x0}, {0x292c0208, 0x0}, {0x292c0700, 0x0}, 62 {0x292c0810, 0x0}, {0x292c0900, 0x0}, {0x292c0904, 0x0}, 63 {0x292c0908, 0x0}, {0x292c090c, 0x0}, {0x292c0a00, 0x0}, 64 }; 65 66 static uint32_t pcc3[61]; 67 static uint32_t pcc4[32]; 68 69 static uint32_t pcc5_0[33]; 70 static uint32_t pcc5_1[][2] = { 71 {0x2da70084, 0x0}, {0x2da70088, 0x0}, {0x2da7008c, 0x0}, 72 {0x2da700a0, 0x0}, {0x2da700a4, 0x0}, {0x2da700a8, 0x0}, 73 {0x2da700ac, 0x0}, {0x2da700b0, 0x0}, {0x2da700b4, 0x0}, 74 {0x2da700bc, 0x0}, {0x2da700c0, 0x0}, {0x2da700c8, 0x0}, 75 {0x2da700cc, 0x0}, {0x2da700d0, 0x0}, {0x2da700f0, 0x0}, 76 {0x2da700f4, 0x0}, {0x2da700f8, 0x0}, {0x2da70108, 0x0}, 77 {0x2da7010c, 0x0}, {0x2da70110, 0x0}, {0x2da70114, 0x0}, 78 }; 79 80 static uint32_t cgc2[][2] = { 81 {0x2da60014, 0x0}, {0x2da60020, 0x0}, {0x2da6003c, 0x0}, 82 {0x2da60040, 0x0}, {0x2da60108, 0x0}, {0x2da60208, 0x0}, 83 {0x2da60900, 0x0}, {0x2da60904, 0x0}, {0x2da60908, 0x0}, 84 {0x2da60910, 0x0}, {0x2da60a00, 0x0}, 85 }; 86 87 static uint32_t pll4[][2] = { 88 {0x2da60604, 0x0}, {0x2da60608, 0x0}, {0x2da6060c, 0x0}, 89 {0x2da60610, 0x0}, {0x2da60618, 0x0}, {0x2da6061c, 0x0}, 90 {0x2da60620, 0x0}, {0x2da60624, 0x0}, {0x2da60600, 0x0}, 91 {0x2da60614, 0x0}, 92 }; 93 94 static uint32_t lpav_sim[][2] = { 95 {0x2da50000, 0x0}, {0x2da50004, 0x0}, {0x2da50008, 0x0}, 96 {0x2da5001c, 0x0}, {0x2da50020, 0x0}, {0x2da50024, 0x0}, 97 {0x2da50034, 0x0}, 98 }; 99 100 #define APD_GPIO_CTRL_NUM 2 101 #define LPAV_GPIO_CTRL_NUM 1 102 #define GPIO_CTRL_REG_NUM 8 103 #define GPIO_PIN_MAX_NUM 32 104 #define GPIO_CTX(addr, num) \ 105 {.base = (addr), .pin_num = (num), } 106 107 struct gpio_ctx { 108 /* gpio base */ 109 uintptr_t base; 110 /* port control */ 111 uint32_t port_ctrl[GPIO_CTRL_REG_NUM]; 112 /* GPIO ICR, Max 32 */ 113 uint32_t pin_num; 114 uint32_t gpio_icr[GPIO_PIN_MAX_NUM]; 115 }; 116 117 static uint32_t gpio_ctrl_offset[GPIO_CTRL_REG_NUM] = { 118 0xc, 0x10, 0x14, 0x18, 0x1c, 0x40, 0x54, 0x58 119 }; 120 static struct gpio_ctx apd_gpio_ctx[APD_GPIO_CTRL_NUM] = { 121 GPIO_CTX(IMX_GPIOE_BASE, 24), 122 GPIO_CTX(IMX_GPIOF_BASE, 32), 123 }; 124 125 static struct gpio_ctx lpav_gpio_ctx = GPIO_CTX(IMX_GPIOD_BASE, 24); 126 /* iomuxc setting */ 127 #define IOMUXC_SECTION_NUM 8 128 struct iomuxc_section { 129 uint32_t offset; 130 uint32_t reg_num; 131 }; 132 133 struct iomuxc_section iomuxc_sections[IOMUXC_SECTION_NUM] = { 134 {.offset = IOMUXC_PTD_PCR_BASE, .reg_num = 24}, 135 {.offset = IOMUXC_PTE_PCR_BASE, .reg_num = 24}, 136 {.offset = IOMUXC_PTF_PCR_BASE, .reg_num = 32}, 137 {.offset = IOMUXC_PSMI_BASE0, .reg_num = 10}, 138 {.offset = IOMUXC_PSMI_BASE1, .reg_num = 61}, 139 {.offset = IOMUXC_PSMI_BASE2, .reg_num = 12}, 140 {.offset = IOMUXC_PSMI_BASE3, .reg_num = 20}, 141 {.offset = IOMUXC_PSMI_BASE4, .reg_num = 75}, 142 }; 143 static uint32_t iomuxc_ctx[258]; 144 145 void iomuxc_save(void) 146 { 147 unsigned int i, j; 148 unsigned int index = 0U; 149 150 for (i = 0U; i < IOMUXC_SECTION_NUM; i++) { 151 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { 152 iomuxc_ctx[index++] = mmio_read_32(iomuxc_sections[i].offset + j * 4); 153 } 154 } 155 } 156 157 void iomuxc_restore(void) 158 { 159 unsigned int i, j; 160 unsigned int index = 0U; 161 162 for (i = 0U; i < IOMUXC_SECTION_NUM; i++) { 163 for (j = 0U; j < iomuxc_sections[i].reg_num; j++) { 164 mmio_write_32(iomuxc_sections[i].offset + j * 4, iomuxc_ctx[index++]); 165 } 166 } 167 } 168 169 void gpio_save(struct gpio_ctx *ctx, int port_num) 170 { 171 unsigned int i, j; 172 173 for (i = 0U; i < port_num; i++) { 174 /* save the port control setting */ 175 for (j = 0U; j < GPIO_CTRL_REG_NUM; j++) { 176 if (j < 4U) { 177 ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]); 178 /* 179 * clear the permission setting to read the GPIO 180 * non-secure world setting. 181 */ 182 mmio_write_32(ctx->base + gpio_ctrl_offset[j], 0x0); 183 } else { 184 ctx->port_ctrl[j] = mmio_read_32(ctx->base + gpio_ctrl_offset[j]); 185 } 186 } 187 /* save the gpio icr setting */ 188 for (j = 0U; j < ctx->pin_num; j++) { 189 ctx->gpio_icr[j] = mmio_read_32(ctx->base + 0x80 + j * 4); 190 } 191 192 ctx++; 193 } 194 } 195 196 void gpio_restore(struct gpio_ctx *ctx, int port_num) 197 { 198 unsigned int i, j; 199 200 for (i = 0U; i < port_num; i++) { 201 for (j = 0U; j < ctx->pin_num; j++) 202 mmio_write_32(ctx->base + 0x80 + j * 4, ctx->gpio_icr[j]); 203 204 for (j = 4U; j < GPIO_CTRL_REG_NUM; j++) { 205 mmio_write_32(ctx->base + gpio_ctrl_offset[j], ctx->port_ctrl[j]); 206 } 207 208 /* permission config retore last */ 209 for (j = 0U; j < 4; j++) { 210 mmio_write_32(ctx->base + gpio_ctrl_offset[j], ctx->port_ctrl[j]); 211 } 212 213 ctx++; 214 } 215 } 216 217 void cgc1_save(void) 218 { 219 unsigned int i; 220 221 /* PLL2 */ 222 for (i = 0U; i < ARRAY_SIZE(pll2); i++) { 223 pll2[i][1] = mmio_read_32(pll2[i][0]); 224 } 225 226 /* PLL3 */ 227 for (i = 0U; i < ARRAY_SIZE(pll3); i++) { 228 pll3[i][1] = mmio_read_32(pll3[i][0]); 229 } 230 231 /* CGC1 others */ 232 for (i = 0U; i < ARRAY_SIZE(cgc1); i++) { 233 cgc1[i][1] = mmio_read_32(cgc1[i][0]); 234 } 235 } 236 237 void cgc1_restore(void) 238 { 239 unsigned int i; 240 241 /* PLL2 */ 242 for (i = 0U; i < ARRAY_SIZE(pll2); i++) { 243 mmio_write_32(pll2[i][0], pll2[i][1]); 244 } 245 /* wait for PLL2 lock */ 246 while (!(mmio_read_32(pll2[4][0]) & BIT(24))) { 247 ; 248 } 249 250 /* PLL3 */ 251 for (i = 0U; i < 9U; i++) { 252 mmio_write_32(pll3[i][0], pll3[i][1]); 253 } 254 255 /* wait for PLL3 lock */ 256 while (!(mmio_read_32(pll3[4][0]) & BIT(24))) { 257 ; 258 } 259 260 /* restore the PFDs */ 261 mmio_write_32(pll3[9][0], pll3[9][1] & ~(BIT(31) | BIT(23) | BIT(15) | BIT(7))); 262 mmio_write_32(pll3[9][0], pll3[9][1]); 263 264 /* wait for the PFD is stable, only need to check the enabled PFDs */ 265 while (!(mmio_read_32(pll3[9][0]) & PFD_VALID_MASK)) { 266 ; 267 } 268 269 /* CGC1 others */ 270 for (i = 0U; i < ARRAY_SIZE(cgc1); i++) { 271 mmio_write_32(cgc1[i][0], cgc1[i][1]); 272 } 273 } 274 275 void tpm5_save(void) 276 { 277 tpm5[0] = mmio_read_32(IMX_TPM5_BASE + 0x10); 278 tpm5[1] = mmio_read_32(IMX_TPM5_BASE + 0x18); 279 tpm5[2] = mmio_read_32(IMX_TPM5_BASE + 0x20); 280 } 281 282 void tpm5_restore(void) 283 { 284 mmio_write_32(IMX_TPM5_BASE + 0x10, tpm5[0]); 285 mmio_write_32(IMX_TPM5_BASE + 0x18, tpm5[1]); 286 mmio_write_32(IMX_TPM5_BASE + 0x20, tpm5[2]); 287 } 288 289 void wdog3_save(void) 290 { 291 /* enable wdog3 clock */ 292 mmio_write_32(IMX_PCC3_BASE + 0xa8, 0xd2800000); 293 294 /* save the CS & TOVAL regiter */ 295 wdog3[0] = mmio_read_32(IMX_WDOG3_BASE); 296 wdog3[1] = mmio_read_32(IMX_WDOG3_BASE + 0x8); 297 } 298 299 void wdog3_restore(void) 300 { 301 /* enable wdog3 clock */ 302 mmio_write_32(IMX_PCC3_BASE + 0xa8, 0xd2800000); 303 304 /* reconfig the CS */ 305 mmio_write_32(IMX_WDOG3_BASE, wdog3[0]); 306 /* set the tiemout value */ 307 mmio_write_32(IMX_WDOG3_BASE + 0x8, wdog3[1]); 308 309 /* wait for the lock status */ 310 while ((mmio_read_32(IMX_WDOG3_BASE) & BIT(11))) { 311 ; 312 } 313 314 /* wait for the config done */ 315 while (!(mmio_read_32(IMX_WDOG3_BASE) & BIT(10))) { 316 ; 317 } 318 } 319 320 static uint32_t lpuart_regs[4]; 321 #define LPUART_BAUD 0x10 322 #define LPUART_CTRL 0x18 323 #define LPUART_FIFO 0x28 324 #define LPUART_WATER 0x2c 325 326 void lpuart_save(void) 327 { 328 lpuart_regs[0] = mmio_read_32(IMX_LPUART5_BASE + LPUART_BAUD); 329 lpuart_regs[1] = mmio_read_32(IMX_LPUART5_BASE + LPUART_FIFO); 330 lpuart_regs[2] = mmio_read_32(IMX_LPUART5_BASE + LPUART_WATER); 331 lpuart_regs[3] = mmio_read_32(IMX_LPUART5_BASE + LPUART_CTRL); 332 } 333 334 void lpuart_restore(void) 335 { 336 mmio_write_32(IMX_LPUART5_BASE + LPUART_BAUD, lpuart_regs[0]); 337 mmio_write_32(IMX_LPUART5_BASE + LPUART_FIFO, lpuart_regs[1]); 338 mmio_write_32(IMX_LPUART5_BASE + LPUART_WATER, lpuart_regs[2]); 339 mmio_write_32(IMX_LPUART5_BASE + LPUART_CTRL, lpuart_regs[3]); 340 } 341 342 bool is_lpav_owned_by_apd(void) 343 { 344 return (mmio_read_32(0x2802b044) & BIT(7)) ? true : false; 345 } 346 347 void lpav_ctx_save(void) 348 { 349 unsigned int i; 350 uint32_t val; 351 352 /* CGC2 save */ 353 for (i = 0U; i < ARRAY_SIZE(cgc2); i++) { 354 cgc2[i][1] = mmio_read_32(cgc2[i][0]); 355 } 356 357 /* PLL4 */ 358 for (i = 0U; i < ARRAY_SIZE(pll4); i++) { 359 pll4[i][1] = mmio_read_32(pll4[i][0]); 360 } 361 362 /* PCC5 save */ 363 for (i = 0U; i < ARRAY_SIZE(pcc5_0); i++) { 364 val = mmio_read_32(IMX_PCC5_BASE + i * 4); 365 if (val & PCC_PR) { 366 pcc5_0[i] = val; 367 } 368 } 369 370 for (i = 0U; i < ARRAY_SIZE(pcc5_1); i++) { 371 val = mmio_read_32(pcc5_1[i][0]); 372 if (val & PCC_PR) { 373 pcc5_1[i][1] = val; 374 } 375 } 376 377 /* LPAV SIM save */ 378 for (i = 0U; i < ARRAY_SIZE(lpav_sim); i++) { 379 lpav_sim[i][1] = mmio_read_32(lpav_sim[i][0]); 380 } 381 382 /* Save GPIO port D */ 383 gpio_save(&lpav_gpio_ctx, LPAV_GPIO_CTRL_NUM); 384 385 /* put DDR into retention */ 386 dram_enter_retention(); 387 } 388 389 void lpav_ctx_restore(void) 390 { 391 unsigned int i; 392 393 /* PLL4 */ 394 for (i = 0U; i < 9U; i++) { 395 mmio_write_32(pll4[i][0], pll4[i][1]); 396 } 397 398 /* wait for PLL4 lock */ 399 while (!(mmio_read_32(pll4[8][0]) & BIT(24))) { 400 ; 401 } 402 403 /* restore the PLL4 PFDs */ 404 mmio_write_32(pll4[9][0], pll4[9][1] & ~(BIT(31) | BIT(23) | BIT(15) | BIT(7))); 405 mmio_write_32(pll4[9][0], pll4[9][1]); 406 407 /* wait for the PFD is stable */ 408 while (!(mmio_read_32(pll4[9][0]) & PFD_VALID_MASK)) { 409 ; 410 } 411 412 /* CGC2 restore */ 413 for (i = 0U; i < ARRAY_SIZE(cgc2); i++) { 414 mmio_write_32(cgc2[i][0], cgc2[i][1]); 415 } 416 417 /* PCC5 restore */ 418 for (i = 0U; i < ARRAY_SIZE(pcc5_0); i++) { 419 if (pcc5_0[i] & PCC_PR) { 420 mmio_write_32(IMX_PCC5_BASE + i * 4, pcc5_0[i]); 421 } 422 } 423 424 for (i = 0U; i < ARRAY_SIZE(pcc5_1); i++) { 425 if (pcc5_1[i][1] & PCC_PR) { 426 mmio_write_32(pcc5_1[i][0], pcc5_1[i][1]); 427 } 428 } 429 430 /* LPAV_SIM */ 431 for (i = 0U; i < ARRAY_SIZE(lpav_sim); i++) { 432 mmio_write_32(lpav_sim[i][0], lpav_sim[i][1]); 433 } 434 435 gpio_restore(&lpav_gpio_ctx, LPAV_GPIO_CTRL_NUM); 436 /* DDR retention exit */ 437 dram_exit_retention(); 438 } 439 440 void imx_apd_ctx_save(unsigned int proc_num) 441 { 442 unsigned int i; 443 uint32_t val; 444 445 /* enable LPUART5's clock by default */ 446 mmio_setbits_32(IMX_PCC3_BASE + 0xe8, BIT(30)); 447 448 /* save the gic config */ 449 plat_gic_save(proc_num, &imx_gicv3_ctx); 450 451 cmc1_pmprot = mmio_read_32(IMX_CMC1_BASE + 0x18); 452 cmc1_srie = mmio_read_32(IMX_CMC1_BASE + 0x8c); 453 454 /* save the PCC3 */ 455 for (i = 0U; i < ARRAY_SIZE(pcc3); i++) { 456 /* save the pcc if it is exist */ 457 val = mmio_read_32(IMX_PCC3_BASE + i * 4); 458 if (val & PCC_PR) { 459 pcc3[i] = val; 460 } 461 } 462 463 /* save the PCC4 */ 464 for (i = 0U; i < ARRAY_SIZE(pcc4); i++) { 465 /* save the pcc if it is exist */ 466 val = mmio_read_32(IMX_PCC4_BASE + i * 4); 467 if (val & PCC_PR) { 468 pcc4[i] = val; 469 } 470 } 471 472 /* save the CGC1 */ 473 cgc1_save(); 474 475 wdog3_save(); 476 477 gpio_save(apd_gpio_ctx, APD_GPIO_CTRL_NUM); 478 479 iomuxc_save(); 480 481 tpm5_save(); 482 483 lpuart_save(); 484 485 /* 486 * save the lpav ctx & put the ddr into retention 487 * if lpav master is assigned to APD domain. 488 */ 489 if (is_lpav_owned_by_apd()) { 490 lpav_ctx_save(); 491 } 492 } 493 494 void xrdc_reinit(void) 495 { 496 xrdc_apply_apd_config(); 497 xrdc_apply_lpav_config(); 498 499 xrdc_enable(); 500 } 501 502 void s400_release_caam(void) 503 { 504 uint32_t msg, resp; 505 506 mmio_write_32(S400_MU_TRx(0), 0x17d70206); 507 mmio_write_32(S400_MU_TRx(1), 0x7); 508 509 do { 510 resp = mmio_read_32(S400_MU_RSR); 511 } while ((resp & 0x3) != 0x3); 512 513 msg = mmio_read_32(S400_MU_RRx(0)); 514 resp = mmio_read_32(S400_MU_RRx(1)); 515 516 VERBOSE("resp %x; %x", msg, resp); 517 } 518 519 void imx_apd_ctx_restore(unsigned int proc_num) 520 { 521 unsigned int i; 522 523 /* restore the CCG1 */ 524 cgc1_restore(); 525 526 for (i = 0U; i < ARRAY_SIZE(pcc3); i++) { 527 /* save the pcc if it is exist */ 528 if (pcc3[i] & PCC_PR) { 529 mmio_write_32(IMX_PCC3_BASE + i * 4, pcc3[i]); 530 } 531 } 532 533 for (i = 0U; i < ARRAY_SIZE(pcc4); i++) { 534 if (pcc4[i] & PCC_PR) { 535 mmio_write_32(IMX_PCC4_BASE + i * 4, pcc4[i]); 536 } 537 } 538 539 wdog3_restore(); 540 541 iomuxc_restore(); 542 543 gpio_restore(apd_gpio_ctx, APD_GPIO_CTRL_NUM); 544 545 tpm5_restore(); 546 547 xrdc_reinit(); 548 549 /* restore the gic config */ 550 plat_gic_restore(proc_num, &imx_gicv3_ctx); 551 552 mmio_write_32(IMX_CMC1_BASE + 0x18, cmc1_pmprot); 553 mmio_write_32(IMX_CMC1_BASE + 0x8c, cmc1_srie); 554 555 /* enable LPUART5's clock by default */ 556 mmio_setbits_32(IMX_PCC3_BASE + 0xe8, BIT(30)); 557 558 /* restore the console lpuart */ 559 lpuart_restore(); 560 561 /* FIXME: make uart work for ATF */ 562 mmio_write_32(IMX_LPUART_BASE + 0x18, 0xc0000); 563 564 /* Allow M core to reset A core */ 565 mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2)); 566 /* 567 * Ask S400 to release caam to APD as it is owned by s400 568 */ 569 s400_release_caam(); 570 571 /* re-init the caam */ 572 imx8ulp_caam_init(); 573 574 /* 575 * ack the upower, seems a necessary steps, otherwise the upower can 576 * not response to the new API service call. put this just before the 577 * ddr retention exit because that the dram retention exit flow need to 578 * communicate with upower. 579 */ 580 upower_wait_resp(); 581 582 /* 583 * restore the lpav ctx & make ddr out of retention 584 * if lpav master is assigned to APD domain. 585 */ 586 if (is_lpav_owned_by_apd()) { 587 lpav_ctx_restore(); 588 } 589 } 590 591 #define DGO_CTRL1 U(0xc) 592 #define USB_WAKEUP U(0x44) 593 #define USB1_PHY_DPD_WAKEUP_EN BIT_32(5) 594 #define USB0_PHY_DPD_WAKEUP_EN BIT_32(4) 595 #define USB1_PHY_WAKEUP_ISO_DISABLE BIT_32(1) 596 #define USB0_PHY_WAKEUP_ISO_DISABLE BIT_32(0) 597 598 void usb_wakeup_enable(bool enable) 599 { 600 if (enable) { 601 mmio_setbits_32(IMX_SIM1_BASE + USB_WAKEUP, 602 USB1_PHY_WAKEUP_ISO_DISABLE | USB0_PHY_WAKEUP_ISO_DISABLE); 603 mmio_setbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 604 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { 605 ; 606 } 607 608 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 609 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); 610 611 /* Need to delay for a while to make sure the wakeup logic can work */ 612 udelay(500); 613 614 mmio_setbits_32(IMX_SIM1_BASE + USB_WAKEUP, 615 USB1_PHY_DPD_WAKEUP_EN | USB0_PHY_DPD_WAKEUP_EN); 616 mmio_setbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 617 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { 618 ; 619 } 620 621 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 622 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); 623 } else { 624 /* 625 * USBx_PHY_DPD_WAKEUP_EN should be cleared before USB0_PHY_WAKEUP_ISO_DISABLE 626 * to provide the correct the wake-up functionality. 627 */ 628 mmio_write_32(IMX_SIM1_BASE + USB_WAKEUP, USB1_PHY_WAKEUP_ISO_DISABLE | 629 USB0_PHY_WAKEUP_ISO_DISABLE); 630 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 631 while (!(mmio_read_32(IMX_SIM1_BASE + DGO_CTRL1) & BIT(1))) { 632 ; 633 } 634 635 mmio_clrbits_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(0)); 636 mmio_write_32(IMX_SIM1_BASE + DGO_CTRL1, BIT(1)); 637 } 638 } 639