1 /* 2 * Copyright 2021-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <stdbool.h> 9 10 #include <arch_helpers.h> 11 #include <common/bl_common.h> 12 #include <common/debug.h> 13 #include <context.h> 14 #include <drivers/console.h> 15 #include <drivers/generic_delay_timer.h> 16 #include <lib/el3_runtime/context_mgmt.h> 17 #include <lib/mmio.h> 18 #include <lib/xlat_tables/xlat_tables_v2.h> 19 #include <plat/common/platform.h> 20 #include <platform_def.h> 21 22 #include <imx8_lpuart.h> 23 #include <imx8ulp_caam.h> 24 #include <imx_plat_common.h> 25 #include <plat_imx8.h> 26 #include <upower_api.h> 27 #include <xrdc.h> 28 29 #define MAP_BL31_TOTAL \ 30 MAP_REGION_FLAT(BL31_BASE, BL31_LIMIT - BL31_BASE, MT_MEMORY | MT_RW | MT_SECURE) 31 #define MAP_BL31_RO \ 32 MAP_REGION_FLAT(BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_MEMORY | MT_RO | MT_SECURE) 33 #define MAP_BL32_TOTAL MAP_REGION_FLAT(BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW) 34 #define MAP_COHERENT_MEM \ 35 MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), \ 36 MT_DEVICE | MT_RW | MT_SECURE) 37 38 #define TRUSTY_PARAMS_LEN_BYTES (4096*2) 39 40 static const mmap_region_t imx_mmap[] = { 41 DEVICE0_MAP, DEVICE1_MAP, ELE_MAP, 42 SEC_SIM_MAP, SRAM0_MAP, 43 {0} 44 }; 45 46 extern uint32_t upower_init(void); 47 extern void imx8ulp_init_scmi_server(void); 48 49 static entry_point_info_t bl32_image_ep_info; 50 static entry_point_info_t bl33_image_ep_info; 51 52 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, 53 u_register_t arg2, u_register_t arg3) 54 { 55 static console_t console; 56 57 /* config the TPM5 clock */ 58 mmio_write_32(IMX_PCC3_BASE + 0xd0, 0x92000000); 59 mmio_write_32(IMX_PCC3_BASE + 0xd0, 0xd2000000); 60 61 /* enable the GPIO D,E,F non-secure access by default */ 62 mmio_write_32(IMX_PCC4_BASE + 0x78, 0xc0000000); 63 mmio_write_32(IMX_PCC4_BASE + 0x7c, 0xc0000000); 64 mmio_write_32(IMX_PCC5_BASE + 0x114, 0xc0000000); 65 66 mmio_write_32(IMX_GPIOE_BASE + 0x10, 0xffffffff); 67 mmio_write_32(IMX_GPIOE_BASE + 0x14, 0x3); 68 mmio_write_32(IMX_GPIOE_BASE + 0x18, 0xffffffff); 69 mmio_write_32(IMX_GPIOE_BASE + 0x1c, 0x3); 70 71 mmio_write_32(IMX_GPIOF_BASE + 0x10, 0xffffffff); 72 mmio_write_32(IMX_GPIOF_BASE + 0x14, 0x3); 73 mmio_write_32(IMX_GPIOF_BASE + 0x18, 0xffffffff); 74 mmio_write_32(IMX_GPIOF_BASE + 0x1c, 0x3); 75 76 mmio_write_32(IMX_GPIOD_BASE + 0x10, 0xffffffff); 77 mmio_write_32(IMX_GPIOD_BASE + 0x14, 0x3); 78 mmio_write_32(IMX_GPIOD_BASE + 0x18, 0xffffffff); 79 mmio_write_32(IMX_GPIOD_BASE + 0x1c, 0x3); 80 81 console_lpuart_register(IMX_LPUART_BASE, IMX_BOOT_UART_CLK_IN_HZ, 82 IMX_CONSOLE_BAUDRATE, &console); 83 84 /* This console is only used for boot stage */ 85 console_set_scope(&console, CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME); 86 87 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET; 88 bl33_image_ep_info.spsr = plat_get_spsr_for_bl33_entry(); 89 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE); 90 91 #if defined(SPD_opteed) || defined(SPD_trusty) 92 /* Populate entry point information for BL32 */ 93 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0); 94 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE); 95 bl32_image_ep_info.pc = BL32_BASE; 96 bl32_image_ep_info.spsr = 0; 97 98 /* Pass TEE base and size to bl33 */ 99 bl33_image_ep_info.args.arg1 = BL32_BASE; 100 bl33_image_ep_info.args.arg2 = BL32_SIZE; 101 102 #ifdef SPD_trusty 103 bl32_image_ep_info.args.arg0 = BL32_SIZE; 104 bl32_image_ep_info.args.arg1 = BL32_BASE; 105 #else 106 /* Make sure memory is clean */ 107 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0); 108 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 109 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR; 110 #endif 111 #endif 112 } 113 114 void bl31_plat_arch_setup(void) 115 { 116 const mmap_region_t bl_regions[] = { 117 MAP_BL31_TOTAL, 118 MAP_BL31_RO, 119 #if USE_COHERENT_MEM 120 MAP_COHERENT_MEM, 121 #endif 122 #if defined(SPD_opteed) || defined(SPD_trusty) 123 MAP_BL32_TOTAL, 124 #endif 125 {0}, 126 }; 127 128 setup_page_tables(bl_regions, imx_mmap); 129 enable_mmu_el3(0); 130 131 /* TODO: Hack, refine this piece, scmi channel free */ 132 mmio_write_32(SRAM0_BASE + 0x4, 1); 133 134 /* Allow M core to reset A core */ 135 mmio_clrbits_32(IMX_MU0B_BASE + 0x10, BIT(2)); 136 } 137 138 void bl31_platform_setup(void) 139 { 140 /* select the arch timer source */ 141 mmio_setbits_32(IMX_SIM1_BASE + 0x30, 0x8000000); 142 143 generic_delay_timer_init(); 144 145 plat_gic_driver_init(); 146 plat_gic_init(); 147 148 imx8ulp_init_scmi_server(); 149 upower_init(); 150 151 xrdc_apply_apd_config(); 152 xrdc_apply_lpav_config(); 153 xrdc_enable(); 154 155 imx8ulp_caam_init(); 156 } 157 158 entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type) 159 { 160 if (type == NON_SECURE) { 161 return &bl33_image_ep_info; 162 } else { 163 return &bl32_image_ep_info; 164 } 165 } 166 167 unsigned int plat_get_syscnt_freq2(void) 168 { 169 return COUNTER_FREQUENCY; 170 } 171 172 void bl31_plat_runtime_setup(void) 173 { 174 } 175 176 #ifdef SPD_trusty 177 void plat_trusty_set_boot_args(aapcs64_params_t *args) 178 { 179 args->arg0 = BL32_SIZE; 180 args->arg1 = BL32_BASE; 181 args->arg2 = TRUSTY_PARAMS_LEN_BYTES; 182 } 183 #endif 184