1 /* 2 * Copyright 2020-2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <xrdc.h> 8 9 #define SP(X) ((X) << 9) 10 #define SU(X) ((X) << 6) 11 #define NP(X) ((X) << 3) 12 #define NU(X) ((X) << 0) 13 14 #define RWX 7 15 #define RW 6 16 #define R 4 17 #define X 1 18 19 struct xrdc_mda_config imx8ulp_mda[] = { 20 { 0, 7, MDA_SA_PT }, /* A core */ 21 { 1, 1, MDA_SA_NS }, /* DMA1 */ 22 { 2, 1, MDA_SA_NS }, /* USB */ 23 { 3, 1, MDA_SA_NS }, /* PXP-> .M10 */ 24 { 4, 1, MDA_SA_NS }, /* ENET */ 25 { 5, 1, MDA_SA_PT }, /* CAAM */ 26 { 6, 1, MDA_SA_NS }, /* USDHC0 */ 27 { 7, 1, MDA_SA_NS }, /* USDHC1 */ 28 { 8, 1, MDA_SA_NS }, /* USDHC2 */ 29 { 9, 2, MDA_SA_NS }, /* HIFI4 */ 30 { 10, 3, MDA_SA_NS }, /* GPU3D */ 31 { 11, 3, MDA_SA_NS }, /* GPU2D */ 32 { 12, 3, MDA_SA_NS }, /* EPDC */ 33 { 13, 3, MDA_SA_NS }, /* DCNano */ 34 { 14, 3, MDA_SA_NS }, /* ISI */ 35 { 15, 3, MDA_SA_NS }, /* PXP->NIC_LPAV.M0 */ 36 { 16, 3, MDA_SA_NS }, /* DMA2 */ 37 }; 38 39 #ifdef SPD_opteed 40 #define TEE_SHM_SIZE 0x400000 41 #else 42 #define TEE_SHM_SIZE 0x0 43 #endif 44 45 #if defined(SPD_opteed) || defined(SPD_trusty) 46 #define DRAM_MEM_0_START (0x80000000) 47 #define DRAM_MEM_0_SIZE (BL32_BASE - 0x80000000) 48 49 #define DRAM_MEM_1_START (BL32_BASE) 50 #define DRAM_MEM_1_SIZE (BL32_SIZE - TEE_SHM_SIZE) 51 52 #define DRAM_MEM_2_START (DRAM_MEM_1_START + DRAM_MEM_1_SIZE) 53 #define DRAM_MEM_2_SIZE (0x80000000 - DRAM_MEM_1_SIZE - DRAM_MEM_0_SIZE) 54 #endif 55 56 struct xrdc_mrc_config imx8ulp_mrc[] = { 57 { 0, 0, 0x0, 0x30000, {0, 0, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* ROM1 */ 58 { 1, 0, 0x60000000, 0x10000000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* Flexspi2 */ 59 { 2, 0, 0x22020000, 0x40000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM2 */ 60 { 3, 0, 0x22010000, 0x10000, {1, 1, 0, 0, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM0 */ 61 #if defined(SPD_opteed) || defined(SPD_trusty) 62 { 4, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 63 { 4, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfc0, 0} }, /* TEE DRAM for A35, DMA1, USDHC0*/ 64 { 4, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 65 { 5, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 66 { 5, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfc0, 0} }, /* TEE DRAM for NIC_PER */ 67 { 5, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 68 { 6, 0, DRAM_MEM_0_START, DRAM_MEM_0_SIZE, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 69 { 6, 1, DRAM_MEM_1_START, DRAM_MEM_1_SIZE, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfc0, 0} }, /* TEE DRAM for LPAV and RTD*/ 70 { 6, 2, DRAM_MEM_2_START, DRAM_MEM_2_SIZE, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 71 #else 72 { 4, 0, 0x80000000, 0x80000000, {0, 1, 0, 0, 0, 0, 0, 1}, {0xfff, 0} }, /* DRAM for A35, DMA1, USDHC0*/ 73 { 5, 0, 0x80000000, 0x80000000, {0, 1, 0, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for NIC_PER */ 74 { 6, 0, 0x80000000, 0x80000000, {1, 1, 0, 1, 1, 0, 1, 0}, {0xfff, 0} }, /* DRAM for LPAV and RTD*/ 75 #endif 76 { 7, 0, 0x80000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */ 77 { 7, 1, 0x90000000, 0x10000000, {0, 0, 1, 0, 0, 0, 0, 0}, {0xfff, 0} }, /* DRAM for HIFI4 */ 78 { 8, 0, 0x21000000, 0x10000, {1, 1, 1, 1, 1, 0, 1, 1}, {0xfff, 0} }, /* SRAM1 */ 79 { 9, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for HIFI4 */ 80 { 10, 0, 0x1ffc0000, 0xc0000, {0, 0, 0, 0, 0, 0, 0, 0}, {0, 0} }, /* SSRAM for LPAV */ 81 { 11, 0, 0x21170000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {0xfff, SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */ 82 { 11, 1, 0x21180000, 0x10000, {0, 0, 1, 0, 0, 0, 0, 2}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), SP(RW) | SU(RW) | NP(RW)} }, /* HIFI4 TCM */ 83 { 12, 0, 0x2d400000, 0x100000, {0, 0, 0, 0, 0, 0, 0, 1}, {SP(RW) | SU(RW) | NP(RW) | NU(RW), 0} }, /* GIC500 */ 84 }; 85 86 struct xrdc_pac_msc_config imx8ulp_pdac[] = { 87 { 0, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC0 */ 88 { 0, 36, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 36 for CMC1 */ 89 { 0, 41, {0, 0, 0, 0, 0, 0, 7, 7} }, /* PAC0 slot 41 for SIM_AD */ 90 { 1, PAC_SLOT_ALL, {0, 7, 0, 0, 0, 0, 0, 7} }, /* PAC1 */ 91 { 1, 0, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 0 for PCC4 */ 92 { 1, 6, {0, 7, 7, 0, 0, 0, 0, 7} }, /* PAC1 slot 6 for LPUART6 */ 93 { 1, 9, {0, 7, 7, 7, 0, 0, 0, 7} }, /* SAI5 for HIFI4 and eDMA2 */ 94 { 1, 12, {0, 7, 0, 0, 0, 0, 7, 7} }, /* PAC1 slot 12 for IOMUXC1 */ 95 { 2, PAC_SLOT_ALL, {7, 7, 7, 7, 0, 0, 7, 7} }, /* PAC2 */ 96 }; 97 98 struct xrdc_pac_msc_config imx8ulp_msc[] = { 99 { 0, 0, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOE */ 100 { 0, 1, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC0 GPIOF */ 101 { 1, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC1 GPIOD */ 102 { 2, MSC_SLOT_ALL, {0, 0, 0, 0, 0, 0, 7, 7} }, /* MSC2 GPU3D/2D/DCNANO/DDR registers */ 103 }; 104