Merge changes from topic "a80x0_nbx-platform-v1" into integration

* changes:
fix(marvell): work around uutils coreutils truncate -s %SIZE bug
fix(a8k): add XFI params for NBX SFI 10G
fix(a8k):

Merge changes from topic "a80x0_nbx-platform-v1" into integration

* changes:
fix(marvell): work around uutils coreutils truncate -s %SIZE bug
fix(a8k): add XFI params for NBX SFI 10G
fix(a8k): mv_ddr path may not be a git repo
feat(a8k): add a80x0_nbx Free Mobile board
feat(a8k): add user callback for skip_image

show more ...

feat(rza): add initial BL2 support for RZ/A platforms

This patch introduces the initial BL2 support for Renesas RZ/A
platforms. It adds platform-specific sources, drivers, build files,
and memory co

feat(rza): add initial BL2 support for RZ/A platforms

This patch introduces the initial BL2 support for Renesas RZ/A
platforms. It adds platform-specific sources, drivers, build files,
and memory configuration needed to boot via BL2.

Key changes include:
- Board-specific makefiles for RZ/A3M board.
- Platform helpers and BL2 setup routines.
- Drivers for DDR, GPIO, and CPG drivers.
- Platform headers, register definitions, and configuration files.
- Scripts and makefiles for image generation.

Change-Id: I6cea17a76633998d746e7c7c429da9a5bd09ef0c
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>

show more ...

fix(imx9): set GICR frames

For MX9, although the GICR base addresses are discovered as part of the
GIC platform workaround during bl31_platform_setup(), gic_pcpu_init()
(called as part of bl31_main(

fix(imx9): set GICR frames

For MX9, although the GICR base addresses are discovered as part of the
GIC platform workaround during bl31_platform_setup(), gic_pcpu_init()
(called as part of bl31_main()) requires the GICR frames be set.
Not doing so will result in a NULL pointer dereference (or assert failure)

Therefore, make sure GICR frames are set before gic_pcpu_init() gets
executed.

After workaround is finished, make sure GICR base is set to 0 to avoid an
assertion failure during gicv3_rdistif_probe(). GICR base addresses are
discovered using the GICR frames anyways.

Change-Id: I444f2f9cce8fb9e38eed25ff52ed35bff7b12358
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>

show more ...

feat(build): add Mbed TLS submodule

This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building confi

feat(build): add Mbed TLS submodule

This change adds Mbed TLS 3.6.5 as a submodule to the TF-A repository.
It is no longer a requirement to pass `MBEDTLS_DIR` to the build system
when building configurations which require it, as the build system will
now look inside the `contrib` directory if the parameter is missing.

If you cloned TF-A without the `--recurse-submodules` flag, you can
ensure that this submodule is present by running:

git submodule update --init --recursive

BREAKING-CHANGE: Mbed TLS is now included in the TF-A repository, and it
is no longer a requirement to pass `MBEDTLS_DIR` to the build system.
Please run `git submodule update --init --recursive` if you encounter
issues after migrating to the latest version of TF-A.

Change-Id: Iad777e77936d1c373065f17fe5c4aadc45e56b64
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

fix(brcm): fix bad Mbed TLS check

The Broadcom platforms check for the presence of Mbed TLS by chopping
off the final part of `MBEDTLS_DIR`, then searching the Mbed TLS include
directory for it.

Th

fix(brcm): fix bad Mbed TLS check

The Broadcom platforms check for the presence of Mbed TLS by chopping
off the final part of `MBEDTLS_DIR`, then searching the Mbed TLS include
directory for it.

This works only if the stem of `MBEDTLS_DIR` happens to match `mbedtls`,
as Mbed TLS 3.6.5 *does* provide an `include/mbedtls` directory. In the
case where Mbed TLS has been downloaded to any other name, its path is
ignored and the platform builds without support for Trusted Board Boot.

Fix this check by explicitly testing the presence of `$(MBEDTLS_DIR)`.

Change-Id: I0eb24083084d98ed3c5f536c082cc3999086beeb
Signed-off-by: Chris Kay <chris.kay@arm.com>

show more ...

Merge changes from topic "dev/rk3568-ddr-fw" into integration

* changes:
feat(rk3568): protect TF-As memory area with the DDR firewall
feat(rk3568): bring DDR firewall naming in line
feat(rk35

Merge changes from topic "dev/rk3568-ddr-fw" into integration

* changes:
feat(rk3568): protect TF-As memory area with the DDR firewall
feat(rk3568): bring DDR firewall naming in line
feat(rk3568): move existing secure init to separate files
fix(rockchip): fix comment and value about TZRAM_SIZE

show more ...

Merge "fix(stm32mp2): correct ORR instruction in plat_crash_console_init" into integration

Merge "feat(rpi3): use transfer list to carry the event log" into integration

feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the

feat(fvp): implement SP live activation callback

This patch implements the callback for orchestrating live activation
of Secure Partition based on the guidance provided in the Appendix
18.10 of the FF-A v1.3 ALP2 specification.

The callback relies on helper utilities that enable the LSP to send
live activation framework messages to SPMC after performing several
sanity checks.

Change-Id: I2730433ec57c0c1163281eff9de729c6e93f3366
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(fvp): enable discovery of two Secure Partitions for live activation

This patch helps the LFA host to discover the presence of two Secure
Partitions for FVP platform that are capable of being li

feat(fvp): enable discovery of two Secure Partitions for live activation

This patch helps the LFA host to discover the presence of two Secure
Partitions for FVP platform that are capable of being live activated.
Necessary attributes of these two Secure Partitions are defined to
allow the LFA agent to report them to the host when the host performs
initial discovery of LFA support.

BREAKING CHANGE: Temporarily failing to build

Change-Id: Ibf0405559543cf19aaf45637c11ba5cf2e3a1619
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
pla

feat(fvp): introduce SP live activation component manager

This patch introduces SP LFA component manager which provides callbacks
necessary for live activation. Currently, the callbacks are just
placeholders.

Subsequent patches will implement the required functionality.

BREAKING CHANGE: Temporarily fails to build

Change-Id: Id733eaa0e7a300386b720fcce99ea265fd382ab6
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live acti

feat(spmd): helpers for SP live activation framework messages

This patch provides helper functions that enable an LSP to send
appropriate framework messages to SPMC in order to orchestrate
live activation of a physical SP.

BREAKING CHANGE: Temporarily fails to build

Change-Id: I1b7dcf91e08fc7d85b47f2b39330d1351f8294dd
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

chore(fvp): remove the dummy function fvp_get_partition_info

The functionality in this function will be ported to SP live
activation callback implemented in subsequent patches.

BREAKING CHANGE: Tem

chore(fvp): remove the dummy function fvp_get_partition_info

The functionality in this function will be ported to SP live
activation callback implemented in subsequent patches.

BREAKING CHANGE: Temporary fails to build

Change-Id: I49a6941a18d2357092dcebf3e882a86e5ac8991f
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>

show more ...

feat(rpi3): use transfer list to carry the event log

Add support for libtl and event log library.
BL1 initializes secure TL, BL2 appends measurements to the TL.
TL handed off to BL33.
Legacy measure

feat(rpi3): use transfer list to carry the event log

Add support for libtl and event log library.
BL1 initializes secure TL, BL2 appends measurements to the TL.
TL handed off to BL33.
Legacy measured boot support still exists when TRANSFER_LIST flag
turned off.
Memory layout adjusted to accommodate for increased binary size.

Change-Id: I60c84d610b63067b6499957e8d6a79866adfca83
Signed-off-by: Prachotan Bathi <prachotan.bathi@arm.com>

show more ...

Merge "fix(versal2): update IRQ_MAX for SDIO interrupts" into integration

Merge "feat(versal): add support for TFA_NO_PM configuration" into integration

feat(versal): add support for TFA_NO_PM configuration

For Versal APU validation in Zephyr CI it is useful to run only one QEMU
instance and not model PLM (Platform Loader and Manager). That's why
im

feat(versal): add support for TFA_NO_PM configuration

For Versal APU validation in Zephyr CI it is useful to run only one QEMU
instance and not model PLM (Platform Loader and Manager). That's why
implement TFA_NO_PM compilation flag to cover it. That's why don't call
any PM initialization or communication via IPI with PLM. Flag is
aligned with implementations done in Versal NET or Versal Gen 2.

Change-Id: I0a4c4c3789f78b649e2961885c87628a599e5536
Signed-off-by: Michal Simek <michal.simek@amd.com>

show more ...

Merge "fix(st): restore support for multiple entries in DTB_FILE_NAME" into integration

chore(imx8mq): replace a magic number with SCR_FIQ_BIT constant

Aside of obvious readability improvement, this also makes it consistent
with its mirrored use in imx_domain_suspend.

Change-Id: Idcbf

chore(imx8mq): replace a magic number with SCR_FIQ_BIT constant

Aside of obvious readability improvement, this also makes it consistent
with its mirrored use in imx_domain_suspend.

Change-Id: Idcbf195b3bd3902554e795c26bd1ce243368f090
Signed-off-by: Sebastian Krzyszkowiak <sebastian.krzyszkowiak@puri.sm>

show more ...

fix(stm32mp2): correct ORR instruction in plat_crash_console_init

For some cases, the value (DEBUG_UART_TX_GPIO_ALTERNATE <<
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) cannot fit the
p

fix(stm32mp2): correct ORR instruction in plat_crash_console_init

For some cases, the value (DEBUG_UART_TX_GPIO_ALTERNATE <<
((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)) cannot fit the
pattern for immediate value for ORR instruction.
Use a temporary register, filled with mov_imm macro.
While at it change the other ORR or BIC instructions that could have the
same issue.

Change-Id: If4434b910463af7d55b9e4ea6562a67e606b02bb
Signed-off-by: Yann Gautier <yann.gautier@st.com>

show more ...

Merge changes from topic "upstream_ddr_fw_storage" into integration

* changes:
feat(s32g274ardb): add DDR init call
feat(s32g274ardb): map regions used by DDR driver
feat(s32g274ardb): add DDR

Merge changes from topic "upstream_ddr_fw_storage" into integration

* changes:
feat(s32g274ardb): add DDR init call
feat(s32g274ardb): map regions used by DDR driver
feat(s32g274ardb): add DDR FW entry to storage

show more ...

Merge changes from topic "ti-am62l-fwl" into integration

* changes:
feat(k3low): re-configure firewalls for TI AM62L
feat(ti): add support for TISCI firewall APIs

Merge changes from topic "stm32mp23_stm32mp21" into integration

* changes:
feat(stm32mp21-fdts): add STM32MP215F-DK board
feat(fdts): introduce STM32MP21 pinctrl files
feat(stm32mp2): add a ne

Merge changes from topic "stm32mp23_stm32mp21" into integration

* changes:
feat(stm32mp21-fdts): add STM32MP215F-DK board
feat(fdts): introduce STM32MP21 pinctrl files
feat(stm32mp2): add a new stm32mp21 power compatible
feat(stm32mp2): add RIFSC USB configuration for variants
feat(st-rif): add STM32MP2x support in RIFSC driver
feat(stm32mp2): include dedicated RIFSC ID headers
feat(stm32mp21): add RIFSC IDs bindings
feat(stm32mp21): enable USBOTG DFU
feat(st-usb): enable USBOTG DFU for STM32MP21
feat(stm32mp2): manage RISAF MCE key for STM32MP21
feat(st-rif): add RISAF MCE support for STM32MP21
feat(stm32mp2): define UART8 and UART9 under STM32MP25 flag
feat(stm32mp21): display package type
feat(stm32mp21): add SoC part numbers
feat(stm32mp21): update boot API header version
feat(stm32mp2): introduce MCE encryption level in RISAF dt-bindings
feat(stm32mp21): update STM32 header size for STM32MP21
feat(st-bsec): update OTPCR masks for STM32MP21
feat(st-bsec): add STM32MP21 version support
feat(stm32mp21): remove GPIOJ and GPIOK
feat(stm32mp21): update SRAM1 and RETRAM base address
feat(stm32mp21-fdts): add fw-config file
feat(stm32mp21): manage STM32MP21 DT overlays
feat(stm32mp21-fdts): add pinctrl DT file
feat(stm32mp21-fdts): add SoC DT files
feat(stm32image): add header version 2.3 support
docs(changelog): add st-rif scope
docs(changelog): reorder ST drivers scopes
feat(stm32mp23-fdts): add STM32MP235F-DK board
feat(stm32mp23): add RIFSC IDs bindings
feat(stm32mp23-fdts): add SoC DT files
feat(stm32mp23-fdts): add fw-config file
feat(stm32mp23): manage STM32MP23 DT overlays
feat(stm32mp23): display package type
feat(stm32mp23): add SoC part numbers

show more ...

Merge "fix(romlib): gate RSA jump table entries" into integration

fix(romlib): gate RSA jump table entries

This fixes undefined reference to mbedtls_x509_get_rsassa_pss_params
in jump table when build with USE_ROMLIB=1 and KEY_ALG=ecdsa

Change-Id: Ib1d88acf00812

fix(romlib): gate RSA jump table entries

This fixes undefined reference to mbedtls_x509_get_rsassa_pss_params
in jump table when build with USE_ROMLIB=1 and KEY_ALG=ecdsa

Change-Id: Ib1d88acf008126752faec2ab7986e4b1a566b717
Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com>

show more ...