1 /* 2 * Copyright (c) 2022-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_features.h> 8 #include <common/debug.h> 9 #include <common/feat_detect.h> 10 #include <plat/common/platform.h> 11 12 static bool detection_done[PLATFORM_CORE_COUNT] = { false }; 13 14 /******************************************************************************* 15 * Function : check_feature 16 * Check for a valid combination of build time flags (ENABLE_FEAT_xxx) and 17 * feature availability on the hardware. <min> is the smallest feature 18 * ID field value that is required for that feature. 19 * Triggers a panic later if a feature is forcefully enabled, but not 20 * available on the PE. Also will panic if the hardware feature ID field 21 * is larger than the maximum known and supported number, specified by <max>. 22 * 23 * We force inlining here to let the compiler optimise away the whole check 24 * if the feature is disabled at build time (FEAT_STATE_DISABLED). 25 ******************************************************************************/ 26 static inline bool __attribute((__always_inline__)) 27 check_feature(int state, unsigned long field, const char *feat_name, 28 unsigned int min, unsigned int max) 29 { 30 if (state == FEAT_STATE_ALWAYS && field < min) { 31 ERROR("FEAT_%s not supported by the PE\n", feat_name); 32 return true; 33 } 34 if (state >= FEAT_STATE_ALWAYS && field > max) { 35 ERROR("FEAT_%s is version %ld, but is only known up to version %d\n", 36 feat_name, field, max); 37 return true; 38 } 39 40 return false; 41 } 42 43 static unsigned int read_feat_rng_trap_id_field(void) 44 { 45 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT, 46 ID_AA64PFR1_EL1_RNDR_TRAP_MASK); 47 } 48 49 static unsigned int read_feat_bti_id_field(void) 50 { 51 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_BT_SHIFT, 52 ID_AA64PFR1_EL1_BT_MASK); 53 } 54 55 static unsigned int read_feat_sb_id_field(void) 56 { 57 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_SB_SHIFT, 58 ID_AA64ISAR1_SB_MASK); 59 } 60 61 static unsigned int read_feat_csv2_id_field(void) 62 { 63 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_CSV2_SHIFT, 64 ID_AA64PFR0_CSV2_MASK); 65 } 66 67 static unsigned int read_feat_debugv8p9_id_field(void) 68 { 69 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_DEBUGVER_SHIFT, 70 ID_AA64DFR0_DEBUGVER_MASK); 71 } 72 73 static unsigned int read_feat_pmuv3_id_field(void) 74 { 75 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_PMUVER_SHIFT, 76 ID_AA64DFR0_PMUVER_MASK); 77 } 78 79 static unsigned int read_feat_vhe_id_field(void) 80 { 81 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_VHE_SHIFT, 82 ID_AA64MMFR1_EL1_VHE_MASK); 83 } 84 85 static unsigned int read_feat_sve_id_field(void) 86 { 87 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SVE_SHIFT, 88 ID_AA64PFR0_SVE_MASK); 89 } 90 91 static unsigned int read_feat_ras_id_field(void) 92 { 93 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_RAS_SHIFT, 94 ID_AA64PFR0_RAS_MASK); 95 } 96 97 static unsigned int read_feat_dit_id_field(void) 98 { 99 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_DIT_SHIFT, 100 ID_AA64PFR0_DIT_MASK); 101 } 102 103 static unsigned int read_feat_amu_id_field(void) 104 { 105 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_AMU_SHIFT, 106 ID_AA64PFR0_AMU_MASK); 107 } 108 109 static unsigned int read_feat_mpam_version(void) 110 { 111 return (unsigned int)((((read_id_aa64pfr0_el1() >> 112 ID_AA64PFR0_MPAM_SHIFT) & ID_AA64PFR0_MPAM_MASK) << 4) | 113 ((read_id_aa64pfr1_el1() >> 114 ID_AA64PFR1_MPAM_FRAC_SHIFT) & ID_AA64PFR1_MPAM_FRAC_MASK)); 115 } 116 117 static unsigned int read_feat_nv_id_field(void) 118 { 119 return ISOLATE_FIELD(read_id_aa64mmfr2_el1(), ID_AA64MMFR2_EL1_NV_SHIFT, 120 ID_AA64MMFR2_EL1_NV_MASK); 121 } 122 123 static unsigned int read_feat_sel2_id_field(void) 124 { 125 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_SEL2_SHIFT, 126 ID_AA64PFR0_SEL2_MASK); 127 } 128 129 static unsigned int read_feat_trf_id_field(void) 130 { 131 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEFILT_SHIFT, 132 ID_AA64DFR0_TRACEFILT_MASK); 133 } 134 static unsigned int get_armv8_5_mte_support(void) 135 { 136 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_MTE_SHIFT, 137 ID_AA64PFR1_EL1_MTE_MASK); 138 } 139 static unsigned int read_feat_rng_id_field(void) 140 { 141 return ISOLATE_FIELD(read_id_aa64isar0_el1(), ID_AA64ISAR0_RNDR_SHIFT, 142 ID_AA64ISAR0_RNDR_MASK); 143 } 144 static unsigned int read_feat_fgt_id_field(void) 145 { 146 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_FGT_SHIFT, 147 ID_AA64MMFR0_EL1_FGT_MASK); 148 } 149 static unsigned int read_feat_ecv_id_field(void) 150 { 151 return ISOLATE_FIELD(read_id_aa64mmfr0_el1(), ID_AA64MMFR0_EL1_ECV_SHIFT, 152 ID_AA64MMFR0_EL1_ECV_MASK); 153 } 154 static unsigned int read_feat_twed_id_field(void) 155 { 156 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_TWED_SHIFT, 157 ID_AA64MMFR1_EL1_TWED_MASK); 158 } 159 160 static unsigned int read_feat_hcx_id_field(void) 161 { 162 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_HCX_SHIFT, 163 ID_AA64MMFR1_EL1_HCX_MASK); 164 } 165 static unsigned int read_feat_ls64_id_field(void) 166 { 167 return ISOLATE_FIELD(read_id_aa64isar1_el1(), ID_AA64ISAR1_LS64_SHIFT, 168 ID_AA64ISAR1_LS64_MASK); 169 } 170 static unsigned int read_feat_aie_id_field(void) 171 { 172 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_AIE_SHIFT, 173 ID_AA64MMFR3_EL1_AIE_MASK); 174 } 175 static unsigned int read_feat_pfar_id_field(void) 176 { 177 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_PFAR_SHIFT, 178 ID_AA64PFR1_EL1_PFAR_MASK); 179 } 180 static unsigned int read_feat_tcr2_id_field(void) 181 { 182 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_TCRX_SHIFT, 183 ID_AA64MMFR3_EL1_TCRX_MASK); 184 } 185 static unsigned int read_feat_s2pie_id_field(void) 186 { 187 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2PIE_SHIFT, 188 ID_AA64MMFR3_EL1_S2PIE_MASK); 189 } 190 static unsigned int read_feat_s1pie_id_field(void) 191 { 192 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1PIE_SHIFT, 193 ID_AA64MMFR3_EL1_S1PIE_MASK); 194 } 195 static unsigned int read_feat_s2poe_id_field(void) 196 { 197 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S2POE_SHIFT, 198 ID_AA64MMFR3_EL1_S2POE_MASK); 199 } 200 static unsigned int read_feat_s1poe_id_field(void) 201 { 202 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_S1POE_SHIFT, 203 ID_AA64MMFR3_EL1_S1POE_MASK); 204 } 205 static unsigned int read_feat_brbe_id_field(void) 206 { 207 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_BRBE_SHIFT, 208 ID_AA64DFR0_BRBE_MASK); 209 } 210 static unsigned int read_feat_trbe_id_field(void) 211 { 212 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_TRACEBUFFER_SHIFT, 213 ID_AA64DFR0_TRACEBUFFER_MASK); 214 } 215 static unsigned int read_feat_sme_id_field(void) 216 { 217 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_SME_SHIFT, 218 ID_AA64PFR1_EL1_SME_MASK); 219 } 220 static unsigned int read_feat_gcs_id_field(void) 221 { 222 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_GCS_SHIFT, 223 ID_AA64PFR1_EL1_GCS_MASK); 224 } 225 226 static unsigned int read_feat_rme_id_field(void) 227 { 228 return ISOLATE_FIELD(read_id_aa64pfr0_el1(), ID_AA64PFR0_FEAT_RME_SHIFT, 229 ID_AA64PFR0_FEAT_RME_MASK); 230 } 231 232 static unsigned int read_feat_pan_id_field(void) 233 { 234 return ISOLATE_FIELD(read_id_aa64mmfr1_el1(), ID_AA64MMFR1_EL1_PAN_SHIFT, 235 ID_AA64MMFR1_EL1_PAN_MASK); 236 } 237 238 static unsigned int read_feat_mtpmu_id_field(void) 239 { 240 return ISOLATE_FIELD(read_id_aa64dfr0_el1(), ID_AA64DFR0_MTPMU_SHIFT, 241 ID_AA64DFR0_MTPMU_MASK); 242 243 } 244 245 static unsigned int read_feat_the_id_field(void) 246 { 247 return ISOLATE_FIELD(read_id_aa64pfr1_el1(), ID_AA64PFR1_EL1_THE_SHIFT, 248 ID_AA64PFR1_EL1_THE_MASK); 249 } 250 251 static unsigned int read_feat_sctlr2_id_field(void) 252 { 253 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_SCTLR2_SHIFT, 254 ID_AA64MMFR3_EL1_SCTLR2_MASK); 255 } 256 257 static unsigned int read_feat_d128_id_field(void) 258 { 259 return ISOLATE_FIELD(read_id_aa64mmfr3_el1(), ID_AA64MMFR3_EL1_D128_SHIFT, 260 ID_AA64MMFR3_EL1_D128_MASK); 261 } 262 static unsigned int read_feat_gcie_id_field(void) 263 { 264 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_GCIE_SHIFT, 265 ID_AA64PFR2_EL1_GCIE_MASK); 266 } 267 268 static unsigned int read_feat_fpmr_id_field(void) 269 { 270 return ISOLATE_FIELD(read_id_aa64pfr2_el1(), ID_AA64PFR2_EL1_FPMR_SHIFT, 271 ID_AA64PFR2_EL1_FPMR_MASK); 272 } 273 274 static unsigned int read_feat_mops_id_field(void) 275 { 276 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_EL1_MOPS_SHIFT, 277 ID_AA64ISAR2_EL1_MOPS_MASK); 278 } 279 280 static unsigned int read_feat_fgwte3_id_field(void) 281 { 282 return ISOLATE_FIELD(read_id_aa64mmfr4_el1(), ID_AA64MMFR4_EL1_FGWTE3_SHIFT, 283 ID_AA64MMFR4_EL1_FGWTE3_MASK); 284 } 285 286 static unsigned int read_feat_cpa_id_field(void) 287 { 288 return ISOLATE_FIELD(read_id_aa64isar3_el1(), 289 ID_AA64ISAR3_EL1_CPA_SHIFT, 290 ID_AA64ISAR3_EL1_CPA_MASK); 291 } 292 293 static unsigned int read_feat_clrbhb_id_field(void) 294 { 295 return ISOLATE_FIELD(read_id_aa64isar2_el1(), ID_AA64ISAR2_CLRBHB_SHIFT, 296 ID_AA64ISAR2_CLRBHB_MASK); 297 } 298 299 /*********************************************************************************** 300 * TF-A supports many Arm architectural features starting from arch version 301 * (8.0 till 8.7+). These features are mostly enabled through build flags. This 302 * mechanism helps in validating these build flags in the early boot phase 303 * either in BL1 or BL31 depending on the platform and assists in identifying 304 * and notifying the features which are enabled but not supported by the PE. 305 * 306 * It reads all the enabled features ID-registers and ensures the features 307 * are supported by the PE. 308 * In case if they aren't it stops booting at an early phase and logs the error 309 * messages, notifying the platforms about the features that are not supported. 310 * 311 * Further the procedure is implemented with a tri-state approach for each feature: 312 * ENABLE_FEAT_xxx = 0 : The feature is disabled statically at compile time 313 * ENABLE_FEAT_xxx = 1 : The feature is enabled and must be present in hardware. 314 * There will be panic if feature is not present at cold boot. 315 * ENABLE_FEAT_xxx = 2 : The feature is enabled but dynamically enabled at runtime 316 * depending on hardware capability. 317 * 318 * For better readability, state values are defined with macros, namely: 319 * { FEAT_STATE_DISABLED, FEAT_STATE_ALWAYS, FEAT_STATE_CHECK }, taking values 320 * { 0, 1, 2 }, respectively, as their naming. 321 **********************************************************************************/ 322 void detect_arch_features(unsigned int core_pos) 323 { 324 /* No need to keep checking after the first time for each core. */ 325 if (detection_done[core_pos]) { 326 return; 327 } 328 329 bool tainted = false; 330 331 /* v8.0 features */ 332 tainted |= check_feature(ENABLE_FEAT_SB, read_feat_sb_id_field(), 333 "SB", 1, 1); 334 tainted |= check_feature(ENABLE_FEAT_CSV2_2, read_feat_csv2_id_field(), 335 "CSV2_2", 2, 3); 336 tainted |= check_feature(ENABLE_FEAT_CLRBHB, read_feat_clrbhb_id_field(), 337 "CLRBHB", 1, 1); 338 /* 339 * Even though the PMUv3 is an OPTIONAL feature, it is always 340 * implemented and Arm prescribes so. So assume it will be there and do 341 * away with a flag for it. This is used to check minor PMUv3px 342 * revisions so that we catch them as they come along 343 */ 344 tainted |= check_feature(FEAT_STATE_ALWAYS, read_feat_pmuv3_id_field(), 345 "PMUv3", 1, ID_AA64DFR0_PMUVER_PMUV3P9); 346 347 /* v8.1 features */ 348 tainted |= check_feature(ENABLE_FEAT_PAN, read_feat_pan_id_field(), 349 "PAN", 1, 3); 350 tainted |= check_feature(ENABLE_FEAT_VHE, read_feat_vhe_id_field(), 351 "VHE", 1, 1); 352 353 /* v8.2 features */ 354 tainted |= check_feature(ENABLE_SVE_FOR_NS, read_feat_sve_id_field(), 355 "SVE", 1, 1); 356 tainted |= check_feature(ENABLE_FEAT_RAS, read_feat_ras_id_field(), 357 "RAS", 1, 2); 358 359 /* v8.3 features */ 360 /* the PAuth fields are very complicated, no min/max is checked */ 361 tainted |= check_feature(ENABLE_PAUTH, is_feat_pauth_present(), 362 "PAUTH", 1, 1); 363 364 /* v8.4 features */ 365 tainted |= check_feature(ENABLE_FEAT_DIT, read_feat_dit_id_field(), 366 "DIT", 1, 1); 367 tainted |= check_feature(ENABLE_FEAT_AMU, read_feat_amu_id_field(), 368 "AMUv1", 1, 2); 369 tainted |= check_feature(ENABLE_FEAT_MOPS, read_feat_mops_id_field(), 370 "MOPS", 1, 1); 371 tainted |= check_feature(ENABLE_FEAT_MPAM, read_feat_mpam_version(), 372 "MPAM", 1, 17); 373 tainted |= check_feature(CTX_INCLUDE_NEVE_REGS, read_feat_nv_id_field(), 374 "NV2", 2, 2); 375 tainted |= check_feature(ENABLE_FEAT_SEL2, read_feat_sel2_id_field(), 376 "SEL2", 1, 1); 377 tainted |= check_feature(ENABLE_TRF_FOR_NS, read_feat_trf_id_field(), 378 "TRF", 1, 1); 379 380 /* v8.5 features */ 381 tainted |= check_feature(ENABLE_FEAT_MTE2, get_armv8_5_mte_support(), 382 "MTE2", MTE_IMPLEMENTED_ELX, MTE_IMPLEMENTED_ASY); 383 tainted |= check_feature(ENABLE_FEAT_RNG, read_feat_rng_id_field(), 384 "RNG", 1, 1); 385 tainted |= check_feature(ENABLE_BTI, read_feat_bti_id_field(), 386 "BTI", 1, 1); 387 tainted |= check_feature(ENABLE_FEAT_RNG_TRAP, read_feat_rng_trap_id_field(), 388 "RNG_TRAP", 1, 1); 389 390 /* v8.6 features */ 391 tainted |= check_feature(ENABLE_FEAT_AMUv1p1, read_feat_amu_id_field(), 392 "AMUv1p1", 2, 2); 393 tainted |= check_feature(ENABLE_FEAT_FGT, read_feat_fgt_id_field(), 394 "FGT", 1, 2); 395 tainted |= check_feature(ENABLE_FEAT_FGT2, read_feat_fgt_id_field(), 396 "FGT2", 2, 2); 397 tainted |= check_feature(ENABLE_FEAT_ECV, read_feat_ecv_id_field(), 398 "ECV", 1, 2); 399 tainted |= check_feature(ENABLE_FEAT_TWED, read_feat_twed_id_field(), 400 "TWED", 1, 1); 401 402 /* 403 * even though this is a "DISABLE" it does confusingly perform feature 404 * enablement duties like all other flags here. Check it against the HW 405 * feature when we intend to diverge from the default behaviour 406 */ 407 tainted |= check_feature(DISABLE_MTPMU, read_feat_mtpmu_id_field(), 408 "MTPMU", 1, 1); 409 410 /* v8.7 features */ 411 tainted |= check_feature(ENABLE_FEAT_HCX, read_feat_hcx_id_field(), 412 "HCX", 1, 1); 413 tainted |= check_feature(ENABLE_FEAT_LS64_ACCDATA, read_feat_ls64_id_field(), 414 "LS64", 1, 3); 415 416 /* v8.9 features */ 417 tainted |= check_feature(ENABLE_FEAT_TCR2, read_feat_tcr2_id_field(), 418 "TCR2", 1, 1); 419 tainted |= check_feature(ENABLE_FEAT_S2PIE, read_feat_s2pie_id_field(), 420 "S2PIE", 1, 1); 421 tainted |= check_feature(ENABLE_FEAT_S1PIE, read_feat_s1pie_id_field(), 422 "S1PIE", 1, 1); 423 tainted |= check_feature(ENABLE_FEAT_S2POE, read_feat_s2poe_id_field(), 424 "S2POE", 1, 1); 425 tainted |= check_feature(ENABLE_FEAT_S1POE, read_feat_s1poe_id_field(), 426 "S1POE", 1, 1); 427 tainted |= check_feature(ENABLE_FEAT_CSV2_3, read_feat_csv2_id_field(), 428 "CSV2_3", 3, 3); 429 tainted |= check_feature(ENABLE_FEAT_DEBUGV8P9, read_feat_debugv8p9_id_field(), 430 "DEBUGV8P9", 11, 11); 431 tainted |= check_feature(ENABLE_FEAT_THE, read_feat_the_id_field(), 432 "THE", 1, 1); 433 tainted |= check_feature(ENABLE_FEAT_SCTLR2, read_feat_sctlr2_id_field(), 434 "SCTLR2", 1, 1); 435 tainted |= check_feature(ENABLE_FEAT_AIE, read_feat_aie_id_field(), 436 "AIE", 1, 1); 437 tainted |= check_feature(ENABLE_FEAT_PFAR, read_feat_pfar_id_field(), 438 "PFAR", 1, 1); 439 440 /* v9.0 features */ 441 tainted |= check_feature(ENABLE_BRBE_FOR_NS, read_feat_brbe_id_field(), 442 "BRBE", 1, 2); 443 tainted |= check_feature(ENABLE_TRBE_FOR_NS, read_feat_trbe_id_field(), 444 "TRBE", 1, 1); 445 446 /* v9.2 features */ 447 tainted |= check_feature(ENABLE_SME_FOR_NS, read_feat_sme_id_field(), 448 "SME", 1, 2); 449 tainted |= check_feature(ENABLE_SME2_FOR_NS, read_feat_sme_id_field(), 450 "SME2", 2, 2); 451 tainted |= check_feature(ENABLE_FEAT_FPMR, read_feat_fpmr_id_field(), 452 "FPMR", 1, 1); 453 454 /* v9.3 features */ 455 tainted |= check_feature(ENABLE_FEAT_D128, read_feat_d128_id_field(), 456 "D128", 1, 1); 457 tainted |= check_feature(ENABLE_FEAT_GCIE, read_feat_gcie_id_field(), 458 "GCIE", 1, 1); 459 tainted |= check_feature(ENABLE_FEAT_MPAM_PE_BW_CTRL, 460 is_feat_mpam_pe_bw_ctrl_present(), 461 "MPAM_PE_BW_CTRL", 1, 1); 462 463 /* v9.4 features */ 464 tainted |= check_feature(ENABLE_FEAT_GCS, read_feat_gcs_id_field(), 465 "GCS", 1, 1); 466 tainted |= check_feature(ENABLE_RME, read_feat_rme_id_field(), 467 "RME", 1, 1); 468 tainted |= check_feature(ENABLE_FEAT_PAUTH_LR, is_feat_pauth_lr_present(), 469 "PAUTH_LR", 1, 1); 470 tainted |= check_feature(ENABLE_FEAT_FGWTE3, read_feat_fgwte3_id_field(), 471 "FGWTE3", 1, 1); 472 tainted |= check_feature(ENABLE_FEAT_CPA2, read_feat_cpa_id_field(), 473 "CPA2", 2, 2); 474 475 if (tainted) { 476 panic(); 477 } 478 479 detection_done[core_pos] = true; 480 } 481