1# 2# Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved. 3# 4# SPDX-License-Identifier: BSD-3-Clause 5# 6 7include common/fdt_wrappers.mk 8 9# Use the GICv3 driver on the FVP by default 10FVP_USE_GIC_DRIVER := FVP_GICV3 11 12# Default cluster count for FVP 13FVP_CLUSTER_COUNT := 2 14 15# Default number of CPUs per cluster on FVP 16FVP_MAX_CPUS_PER_CLUSTER := 4 17 18# Default number of threads per CPU on FVP 19FVP_MAX_PE_PER_CPU := 1 20 21# Disable redistributor frame of inactive/fused CPU cores by marking it as read 22# only; enable redistributor frames of all CPU cores by default. 23FVP_GICR_REGION_PROTECTION := 0 24 25# Size (in kilobytes) of the Trusted SRAM region to utilize when building for 26# the FVP platform. 27ifeq (${ENABLE_RME},1) 28FVP_TRUSTED_SRAM_SIZE := 384 29else 30FVP_TRUSTED_SRAM_SIZE := 256 31endif 32 33# Macro to enable helpers for running SPM tests. Disabled by default. 34PLAT_TEST_SPM := 0 35 36 37# Enable passing the DT to BL33 in x0 by default. 38USE_KERNEL_DT_CONVENTION := 1 39 40# By default dont build CPUs with no FVP model. 41BUILD_CPUS_WITH_NO_FVP_MODEL ?= 0 42 43ENABLE_FEAT_AMU := 2 44ENABLE_FEAT_AMUv1p1 := 2 45ENABLE_FEAT_HCX := 2 46ENABLE_FEAT_RNG := 2 47ENABLE_FEAT_TWED := 2 48ENABLE_FEAT_GCS := 2 49 50ifeq (${ARCH}, aarch64) 51 52ifeq (${SPM_MM}, 0) 53ifeq (${CTX_INCLUDE_FPREGS}, 0) 54 ENABLE_SME_FOR_NS := 2 55 ENABLE_SME2_FOR_NS := 2 56else 57 ENABLE_SVE_FOR_NS := 0 58 ENABLE_SME_FOR_NS := 0 59 ENABLE_SME2_FOR_NS := 0 60endif 61endif 62 63 ENABLE_BRBE_FOR_NS := 2 64 ENABLE_TRBE_FOR_NS := 2 65 ENABLE_FEAT_D128 := 2 66 ENABLE_FEAT_FPMR := 2 67 ENABLE_FEAT_MOPS := 2 68 ENABLE_FEAT_FGWTE3 := 2 69 ENABLE_FEAT_MPAM_PE_BW_CTRL := 2 70 ENABLE_FEAT_CPA2 := 2 71endif 72 73ENABLE_SYS_REG_TRACE_FOR_NS := 2 74ENABLE_FEAT_CSV2_2 := 2 75ENABLE_FEAT_CSV2_3 := 2 76ENABLE_FEAT_CLRBHB := 2 77ENABLE_FEAT_DEBUGV8P9 := 2 78ENABLE_FEAT_DIT := 2 79ENABLE_FEAT_PAN := 2 80ENABLE_FEAT_VHE := 2 81CTX_INCLUDE_NEVE_REGS := 2 82ENABLE_FEAT_SEL2 := 2 83ENABLE_TRF_FOR_NS := 2 84ENABLE_FEAT_ECV := 2 85ENABLE_FEAT_FGT := 2 86ENABLE_FEAT_FGT2 := 2 87ENABLE_FEAT_THE := 2 88ENABLE_FEAT_TCR2 := 2 89ENABLE_FEAT_S2PIE := 2 90ENABLE_FEAT_S1PIE := 2 91ENABLE_FEAT_S2POE := 2 92ENABLE_FEAT_S1POE := 2 93ENABLE_FEAT_SCTLR2 := 2 94ENABLE_FEAT_MTE2 := 2 95ENABLE_FEAT_LS64_ACCDATA := 2 96ENABLE_FEAT_AIE := 2 97ENABLE_FEAT_PFAR := 2 98 99ifeq (${ENABLE_RME},1) 100 ENABLE_FEAT_MEC := 2 101 RMMD_ENABLE_IDE_KEY_PROG := 1 102endif 103 104# The FVP platform depends on this macro to build with correct GIC driver. 105$(eval $(call add_define,FVP_USE_GIC_DRIVER)) 106 107# Pass FVP_CLUSTER_COUNT to the build system. 108$(eval $(call add_define,FVP_CLUSTER_COUNT)) 109 110# Pass FVP_MAX_CPUS_PER_CLUSTER to the build system. 111$(eval $(call add_define,FVP_MAX_CPUS_PER_CLUSTER)) 112 113# Pass FVP_MAX_PE_PER_CPU to the build system. 114$(eval $(call add_define,FVP_MAX_PE_PER_CPU)) 115 116# Pass FVP_GICR_REGION_PROTECTION to the build system. 117$(eval $(call add_define,FVP_GICR_REGION_PROTECTION)) 118 119# Pass FVP_TRUSTED_SRAM_SIZE to the build system. 120$(eval $(call add_define,FVP_TRUSTED_SRAM_SIZE)) 121 122# Sanity check the cluster count and if FVP_CLUSTER_COUNT <= 2, 123# choose the CCI driver , else the CCN driver 124ifeq ($(FVP_CLUSTER_COUNT), 0) 125$(error "Incorrect cluster count specified for FVP port") 126else ifeq ($(FVP_CLUSTER_COUNT),$(filter $(FVP_CLUSTER_COUNT),1 2)) 127FVP_INTERCONNECT_DRIVER := FVP_CCI 128else 129FVP_INTERCONNECT_DRIVER := FVP_CCN 130endif 131 132$(eval $(call add_define,FVP_INTERCONNECT_DRIVER)) 133 134# Choose the GIC sources depending upon the how the FVP will be invoked 135ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3) 136USE_GIC_DRIVER := 3 137 138# The GIC model (GIC-600 or GIC-500) will be detected at runtime 139GICV3_SUPPORT_GIC600 := 1 140GICV3_OVERRIDE_DISTIF_PWR_OPS := 1 141 142FVP_SECURITY_SOURCES += plat/arm/board/fvp/fvp_gicv3.c 143ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 144BL31_SOURCES += plat/arm/board/fvp/fconf/fconf_gicv3_config_getter.c 145endif 146 147ifeq (${HW_ASSISTED_COHERENCY}, 0) 148FVP_DT_PREFIX := fvp-base-gicv3-psci 149else 150FVP_DT_PREFIX := fvp-base-gicv3-psci-dynamiq 151endif 152else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV5) 153USE_GIC_DRIVER := 5 154ENABLE_FEAT_GCIE := 1 155BL31_SOURCES += plat/arm/board/fvp/fvp_gicv5.c 156FVP_DT_PREFIX := fvp-base-gicv5-psci 157ifneq ($(SPD),none) 158 $(error Error: GICv5 is not compatible with SPDs) 159endif 160ifeq ($(ENABLE_RME),1) 161 $(error Error: GICv5 is not compatible with RME) 162endif 163else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV2) 164USE_GIC_DRIVER := 2 165 166# No GICv4 extension 167GIC_ENABLE_V4_EXTN := 0 168$(eval $(call add_define,GIC_ENABLE_V4_EXTN)) 169 170FVP_DT_PREFIX := fvp-base-gicv2-psci 171else 172$(error "Incorrect GIC driver chosen on FVP port") 173endif 174 175ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCI) 176FVP_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c 177else ifeq (${FVP_INTERCONNECT_DRIVER}, FVP_CCN) 178FVP_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \ 179 plat/arm/common/arm_ccn.c 180else 181$(error "Incorrect CCN driver chosen on FVP port") 182endif 183 184FVP_SECURITY_SOURCES += drivers/arm/tzc/tzc400.c \ 185 plat/arm/board/fvp/fvp_security.c \ 186 plat/arm/common/arm_tzc400.c 187 188 189PLAT_INCLUDES := -Iplat/arm/board/fvp/include \ 190 -Iinclude/lib/psa 191 192 193PLAT_BL_COMMON_SOURCES := plat/arm/board/fvp/fvp_common.c 194 195FVP_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S 196 197ifeq (${ARCH}, aarch64) 198 199# select a different set of CPU files, depending on whether we compile for 200# hardware assisted coherency cores or not 201ifeq (${HW_ASSISTED_COHERENCY}, 0) 202# Cores used without DSU 203 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \ 204 lib/cpus/aarch64/cortex_a53.S \ 205 lib/cpus/aarch64/cortex_a57.S \ 206 lib/cpus/aarch64/cortex_a72.S \ 207 lib/cpus/aarch64/cortex_a73.S 208else 209# Cores used with DSU only 210 ifeq (${CTX_INCLUDE_AARCH32_REGS}, 0) 211 # AArch64-only cores 212 # TODO: add all cores to the appropriate lists 213 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a65.S \ 214 lib/cpus/aarch64/cortex_a65ae.S \ 215 lib/cpus/aarch64/cortex_a76.S \ 216 lib/cpus/aarch64/cortex_a76ae.S \ 217 lib/cpus/aarch64/cortex_a77.S \ 218 lib/cpus/aarch64/cortex_a78.S \ 219 lib/cpus/aarch64/cortex_a78_ae.S \ 220 lib/cpus/aarch64/cortex_a78c.S \ 221 lib/cpus/aarch64/cortex_a710.S \ 222 lib/cpus/aarch64/cortex_a715.S \ 223 lib/cpus/aarch64/cortex_a720.S \ 224 lib/cpus/aarch64/cortex_a720_ae.S \ 225 lib/cpus/aarch64/neoverse_n1.S \ 226 lib/cpus/aarch64/neoverse_n2.S \ 227 lib/cpus/aarch64/neoverse_v1.S \ 228 lib/cpus/aarch64/neoverse_e1.S \ 229 lib/cpus/aarch64/cortex_x2.S \ 230 lib/cpus/aarch64/cortex_x4.S 231 endif 232 # AArch64/AArch32 cores 233 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \ 234 lib/cpus/aarch64/cortex_a75.S 235endif 236 237#Include all CPUs to build to support all-errata build. 238ifeq (${ENABLE_ERRATA_ALL},1) 239 BUILD_CPUS_WITH_NO_FVP_MODEL = 1 240 FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a320.S \ 241 lib/cpus/aarch64/cortex_a510.S \ 242 lib/cpus/aarch64/cortex_a520.S \ 243 lib/cpus/aarch64/cortex_a725.S \ 244 lib/cpus/aarch64/cortex_x1.S \ 245 lib/cpus/aarch64/cortex_x3.S \ 246 lib/cpus/aarch64/cortex_x925.S \ 247 lib/cpus/aarch64/neoverse_n3.S \ 248 lib/cpus/aarch64/neoverse_v2.S \ 249 lib/cpus/aarch64/neoverse_v3.S 250endif 251 252#Build AArch64-only CPUs with no FVP model yet. 253ifeq (${BUILD_CPUS_WITH_NO_FVP_MODEL},1) 254 ERRATA_SME_POWER_DOWN := 1 255 FVP_CPU_LIBS += lib/cpus/aarch64/c1_pro.S \ 256 lib/cpus/aarch64/c1_nano.S \ 257 lib/cpus/aarch64/c1_ultra.S \ 258 lib/cpus/aarch64/c1_premium.S \ 259 lib/cpus/aarch64/canyon.S \ 260 lib/cpus/aarch64/caddo.S \ 261 lib/cpus/aarch64/veymont.S \ 262 lib/cpus/aarch64/dionysus.S 263endif 264 265else 266FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \ 267 lib/cpus/aarch32/cortex_a57.S \ 268 lib/cpus/aarch32/cortex_a53.S 269endif 270 271BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \ 272 drivers/arm/sp805/sp805.c \ 273 drivers/delay_timer/delay_timer.c \ 274 drivers/io/io_semihosting.c \ 275 lib/semihosting/semihosting.c \ 276 lib/semihosting/${ARCH}/semihosting_call.S \ 277 plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 278 plat/arm/board/fvp/fvp_bl1_setup.c \ 279 plat/arm/board/fvp/fvp_cpu_pwr.c \ 280 plat/arm/board/fvp/fvp_err.c \ 281 plat/arm/board/fvp/fvp_io_storage.c \ 282 plat/arm/board/fvp/fvp_topology.c \ 283 ${FVP_CPU_LIBS} \ 284 ${FVP_INTERCONNECT_SOURCES} 285 286ifeq (${USE_SP804_TIMER},1) 287BL1_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 288else 289BL1_SOURCES += drivers/delay_timer/generic_delay_timer.c 290endif 291 292 293BL2_SOURCES += drivers/arm/sp805/sp805.c \ 294 drivers/io/io_semihosting.c \ 295 lib/utils/mem_region.c \ 296 lib/semihosting/semihosting.c \ 297 lib/semihosting/${ARCH}/semihosting_call.S \ 298 plat/arm/board/fvp/fvp_bl2_setup.c \ 299 plat/arm/board/fvp/fvp_err.c \ 300 plat/arm/board/fvp/fvp_io_storage.c \ 301 plat/arm/common/arm_nor_psci_mem_protect.c \ 302 ${FVP_SECURITY_SOURCES} 303 304 305ifeq (${COT_DESC_IN_DTB},1) 306BL2_SOURCES += plat/arm/common/fconf/fconf_nv_cntr_getter.c 307endif 308 309ifeq (${ENABLE_RME},1) 310BL2_SOURCES += plat/arm/board/fvp/aarch64/fvp_helpers.S \ 311 plat/arm/board/fvp/fvp_cpu_pwr.c 312 313BL31_SOURCES += plat/arm/board/fvp/fvp_plat_attest_token.c \ 314 plat/arm/board/fvp/fvp_realm_attest_key.c \ 315 plat/arm/board/fvp/fvp_el3_token_sign.c \ 316 plat/arm/board/fvp/fvp_ide_keymgmt.c \ 317 plat/arm/common/plat_rmm_mem_carveout.c 318endif 319 320ifneq (${ENABLE_FEAT_RNG_TRAP},0) 321BL31_SOURCES += plat/arm/board/fvp/fvp_sync_traps.c 322endif 323 324ifeq (${RESET_TO_BL2},1) 325BL2_SOURCES += plat/arm/board/fvp/${ARCH}/fvp_helpers.S \ 326 plat/arm/board/fvp/fvp_cpu_pwr.c \ 327 plat/arm/board/fvp/fvp_bl2_el3_setup.c \ 328 ${FVP_CPU_LIBS} \ 329 ${FVP_INTERCONNECT_SOURCES} 330endif 331 332ifeq (${USE_SP804_TIMER},1) 333BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 334endif 335 336BL2U_SOURCES += plat/arm/board/fvp/fvp_bl2u_setup.c \ 337 ${FVP_SECURITY_SOURCES} 338 339ifeq (${USE_SP804_TIMER},1) 340BL2U_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 341endif 342 343BL31_SOURCES += drivers/arm/fvp/fvp_pwrc.c \ 344 drivers/arm/smmu/smmu_v3.c \ 345 drivers/delay_timer/delay_timer.c \ 346 drivers/cfi/v2m/v2m_flash.c \ 347 lib/utils/mem_region.c \ 348 plat/arm/board/fvp/fvp_bl31_setup.c \ 349 plat/arm/board/fvp/fvp_console.c \ 350 plat/arm/board/fvp/fvp_pm.c \ 351 plat/arm/board/fvp/fvp_topology.c \ 352 plat/arm/board/fvp/aarch64/fvp_helpers.S \ 353 plat/arm/board/fvp/fvp_cpu_pwr.c \ 354 plat/arm/common/arm_nor_psci_mem_protect.c \ 355 ${FVP_CPU_LIBS} \ 356 ${FVP_INTERCONNECT_SOURCES} \ 357 ${FVP_SECURITY_SOURCES} 358 359# Support for fconf in BL31 360# Added separately from the above list for better readability 361ifeq ($(filter 1,${RESET_TO_BL2} ${RESET_TO_BL31}),) 362BL31_SOURCES += lib/fconf/fconf.c \ 363 lib/fconf/fconf_dyn_cfg_getter.c \ 364 plat/arm/board/fvp/fconf/fconf_hw_config_getter.c 365 366BL31_SOURCES += ${FDT_WRAPPERS_SOURCES} 367 368ifeq (${SEC_INT_DESC_IN_FCONF},1) 369BL31_SOURCES += plat/arm/common/fconf/fconf_sec_intr_config.c 370endif 371 372endif 373 374ifeq (${USE_SP804_TIMER},1) 375BL31_SOURCES += drivers/arm/sp804/sp804_delay_timer.c 376else 377BL31_SOURCES += drivers/delay_timer/generic_delay_timer.c 378endif 379 380# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) 381FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts 382 383FDT_SOURCES += ${FVP_HW_CONFIG_DTS} 384$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) 385HW_CONFIG := ${FVP_HW_CONFIG} 386 387HW_CONFIG_BASE ?= 0x82000000 388 389# Set default initrd base 128MiB offset of the default kernel address in FVP 390INITRD_BASE ?= 0x90000000 391 392# Kernel base address supports Linux kernels before v5.7 393# DTB base 1MiB before normal base kernel address in FVP (0x88000000) 394ifeq (${ARM_LINUX_KERNEL_AS_BL33},1) 395 PRELOADED_BL33_BASE ?= 0x80080000 396 ifeq (${RESET_TO_BL31},1) 397 ARM_PRELOADED_DTB_BASE ?= 0x87F00000 398 endif 399endif 400 401ifeq (${TRANSFER_LIST}, 0) 402FDT_SOURCES += $(addprefix plat/arm/board/fvp/fdts/, \ 403 ${PLAT}_fw_config.dts \ 404 ${PLAT}_tb_fw_config.dts \ 405 ${PLAT}_soc_fw_config.dts \ 406 ${PLAT}_nt_fw_config.dts \ 407 ) 408 409FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb 410FVP_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_fw_config.dtb 411FVP_SOC_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_soc_fw_config.dtb 412FVP_NT_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_nt_fw_config.dtb 413 414ifeq (${SPD},tspd) 415FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tsp_fw_config.dts 416FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tsp_fw_config.dtb 417 418# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 419$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 420endif 421 422# Add the SOC_FW_CONFIG to FIP and specify the same to certtool 423$(eval $(call TOOL_ADD_PAYLOAD,${FVP_SOC_FW_CONFIG},--soc-fw-config,${FVP_SOC_FW_CONFIG})) 424# Add the NT_FW_CONFIG to FIP and specify the same to certtool 425$(eval $(call TOOL_ADD_PAYLOAD,${FVP_NT_FW_CONFIG},--nt-fw-config,${FVP_NT_FW_CONFIG})) 426endif 427 428ifeq (${SPD},spmd) 429 430ifeq ($(ARM_SPMC_MANIFEST_DTS),) 431ARM_SPMC_MANIFEST_DTS := plat/arm/board/fvp/fdts/${PLAT}_spmc_manifest.dts 432endif 433 434FDT_SOURCES += ${ARM_SPMC_MANIFEST_DTS} 435FVP_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/$(notdir $(basename ${ARM_SPMC_MANIFEST_DTS})).dtb 436 437# Add the TOS_FW_CONFIG to FIP and specify the same to certtool 438$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TOS_FW_CONFIG},--tos-fw-config,${FVP_TOS_FW_CONFIG})) 439endif 440 441# Add the HW_CONFIG to FIP and specify the same to certtool 442$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config,${FVP_HW_CONFIG})) 443 444ifeq (${TRANSFER_LIST}, 1) 445 446ifeq ($(RESET_TO_BL31), 1) 447FW_HANDOFF_SIZE := 20000 448 449TRANSFER_LIST_DTB_OFFSET := 0x20 450$(eval $(call add_define,TRANSFER_LIST_DTB_OFFSET)) 451endif 452endif 453 454ifeq (${HOB_LIST}, 1) 455include lib/hob/hob.mk 456endif 457 458# Enable dynamic mitigation support by default 459DYNAMIC_WORKAROUND_CVE_2018_3639 := 1 460 461ifneq (${ENABLE_FEAT_AMU},0) 462BL31_SOURCES += lib/cpus/aarch64/cpuamu.c \ 463 lib/cpus/aarch64/cpuamu_helpers.S 464 465ifeq (${HW_ASSISTED_COHERENCY}, 1) 466BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ 467 lib/cpus/aarch64/neoverse_n1_pubsub.c 468endif 469endif 470 471ifeq (${HANDLE_EA_EL3_FIRST_NS},1) 472 ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP},1) 473 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_lsp_ras_sp.c 474 endif 475 BL31_SOURCES += plat/arm/board/fvp/aarch64/fvp_ras.c \ 476 plat/arm/board/fvp/aarch64/fvp_ea.c 477endif 478 479ifneq (${ENABLE_STACK_PROTECTOR},0) 480PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_stack_protector.c 481endif 482 483# Enable the dynamic translation tables library. 484ifeq ($(filter 1,${RESET_TO_BL2} ${ARM_XLAT_TABLES_LIB_V1}),) 485 ifeq (${ARCH},aarch32) 486 BL32_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 487 else # AArch64 488 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 489 endif 490endif 491 492ifeq (${ALLOW_RO_XLAT_TABLES}, 1) 493 ifeq (${ARCH},aarch32) 494 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 495 else # AArch64 496 BL31_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 497 ifeq (${SPD},tspd) 498 BL32_CPPFLAGS += -DPLAT_RO_XLAT_TABLES 499 endif 500 endif 501endif 502 503ifeq (${USE_DEBUGFS},1) 504 BL31_CPPFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC 505endif 506 507# Add support for platform supplied linker script for BL31 build 508PLAT_EXTRA_LD_SCRIPT := 1 509 510ifneq (${RESET_TO_BL2}, 0) 511 override BL1_SOURCES = 512endif 513 514include plat/arm/board/common/board_common.mk 515include plat/arm/common/arm_common.mk 516 517ifeq (${MEASURED_BOOT},1) 518BL1_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 519 plat/arm/board/fvp/fvp_bl1_measured_boot.c \ 520 lib/psa/measured_boot.c 521 522BL2_SOURCES += plat/arm/board/fvp/fvp_common_measured_boot.c \ 523 plat/arm/board/fvp/fvp_bl2_measured_boot.c \ 524 lib/psa/measured_boot.c 525endif 526 527ifeq (${DRTM_SUPPORT}, 1) 528BL31_SOURCES += plat/arm/board/fvp/fvp_drtm_addr.c \ 529 plat/arm/board/fvp/fvp_drtm_dma_prot.c \ 530 plat/arm/board/fvp/fvp_drtm_err.c \ 531 plat/arm/board/fvp/fvp_drtm_measurement.c \ 532 plat/arm/board/fvp/fvp_drtm_stub.c \ 533 plat/arm/common/arm_dyn_cfg.c \ 534 plat/arm/board/fvp/fvp_err.c 535endif 536 537ifeq (${TRUSTED_BOARD_BOOT}, 1) 538BL1_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 539BL2_SOURCES += plat/arm/board/fvp/fvp_trusted_boot.c 540 541# FVP being a development platform, enable capability to disable Authentication 542# dynamically if TRUSTED_BOARD_BOOT is set. 543DYN_DISABLE_AUTH := 1 544endif 545 546ifeq (${SPMC_AT_EL3}, 1) 547PLAT_BL_COMMON_SOURCES += plat/arm/board/fvp/fvp_el3_spmc.c 548endif 549 550PSCI_OS_INIT_MODE := 1 551 552ifeq (${SPD},spmd) 553BL31_SOURCES += plat/arm/board/fvp/fvp_spmd.c 554endif 555 556# Test specific macros, keep them at bottom of this file 557$(eval $(call add_define,PLATFORM_TEST_EA_FFH)) 558ifeq (${PLATFORM_TEST_EA_FFH}, 1) 559 ifeq (${FFH_SUPPORT}, 0) 560 $(error "PLATFORM_TEST_EA_FFH expects FFH_SUPPORT to be 1") 561 endif 562 563endif 564 565PLATFORM_TEST_RAS_FFH ?= 0 566$(eval $(call add_define,PLATFORM_TEST_RAS_FFH)) 567ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 568 ifeq (${ENABLE_FEAT_RAS}, 0) 569 $(error "PLATFORM_TEST_RAS_FFH expects ENABLE_FEAT_RAS to be 1") 570 endif 571 ifeq (${SDEI_SUPPORT}, 0) 572 $(error "PLATFORM_TEST_RAS_FFH expects SDEI_SUPPORT to be 1") 573 endif 574 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 575 $(error "PLATFORM_TEST_RAS_FFH expects HANDLE_EA_EL3_FIRST_NS to be 1") 576 endif 577endif 578 579$(eval $(call add_define,PLATFORM_TEST_FFH_LSP_RAS_SP)) 580ifeq (${PLATFORM_TEST_FFH_LSP_RAS_SP}, 1) 581 ifeq (${PLATFORM_TEST_RAS_FFH}, 1) 582 $(error "PLATFORM_TEST_RAS_FFH is incompatible with PLATFORM_TEST_FFH_LSP_RAS_SP") 583 endif 584 ifeq (${ENABLE_SPMD_LP}, 0) 585 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_SPMD_LP to be 1") 586 endif 587 ifeq (${ENABLE_FEAT_RAS}, 0) 588 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects ENABLE_FEAT_RAS to be 1") 589 endif 590 ifeq (${HANDLE_EA_EL3_FIRST_NS}, 0) 591 $(error "PLATFORM_TEST_FFH_LSP_RAS_SP expects HANDLE_EA_EL3_FIRST_NS to be 1") 592 endif 593endif 594 595ifeq (${ERRATA_ABI_SUPPORT}, 1) 596include plat/arm/board/fvp/fvp_cpu_errata.mk 597endif 598 599# Build macro necessary for running SPM tests on FVP platform 600$(eval $(call add_define,PLAT_TEST_SPM)) 601 602ifeq (${LFA_SUPPORT},1) 603BL31_SOURCES += plat/arm/board/fvp/fvp_lfa.c 604endif 605 606# This is set to 1 by default when the firmware update 607# support is enabled. Since the BL2 image is not updatable 608ifeq ($(PSA_FWU_SUPPORT),1) 609 SEPARATE_BL2_FIP := 1 610endif 611 612ifeq (${TRANSFER_LIST}, 0) 613ifeq (${SEPARATE_BL2_FIP},1) 614$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG},BL2_)) 615$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG},BL2_)) 616else 617$(eval $(call TOOL_ADD_PAYLOAD,${FVP_FW_CONFIG},--fw-config,${FVP_FW_CONFIG})) 618$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config,${FVP_TB_FW_CONFIG})) 619endif 620endif 621