1 /* 2 * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <string.h> 9 10 #include <arch_helpers.h> 11 #include <common/debug.h> 12 #include <common/desc_image_load.h> 13 #include <drivers/fwu/fwu.h> 14 #include <drivers/fwu/fwu_metadata.h> 15 #include <drivers/io/io_block.h> 16 #include <drivers/io/io_driver.h> 17 #include <drivers/io/io_encrypted.h> 18 #include <drivers/io/io_fip.h> 19 #include <drivers/io/io_memmap.h> 20 #include <drivers/io/io_mtd.h> 21 #include <drivers/io/io_storage.h> 22 #include <drivers/mmc.h> 23 #include <drivers/partition/efi.h> 24 #include <drivers/partition/partition.h> 25 #include <drivers/raw_nand.h> 26 #include <drivers/spi_nand.h> 27 #include <drivers/spi_nor.h> 28 #include <drivers/st/stm32_fmc2_nand.h> 29 #include <drivers/st/stm32_qspi.h> 30 #include <drivers/st/stm32_sdmmc2.h> 31 #include <drivers/usb_device.h> 32 #include <lib/fconf/fconf.h> 33 #include <lib/mmio.h> 34 #include <lib/utils.h> 35 #include <plat/common/platform.h> 36 #include <tools_share/firmware_image_package.h> 37 #include <platform_def.h> 38 #include <stm32cubeprogrammer.h> 39 #include <stm32mp_efi.h> 40 #include <stm32mp_fconf_getter.h> 41 #include <stm32mp_io_storage.h> 42 #include <usb_dfu.h> 43 44 /* IO devices */ 45 uintptr_t fip_dev_handle; 46 uintptr_t storage_dev_handle; 47 48 static const io_dev_connector_t *fip_dev_con; 49 static uint32_t nand_block_sz __maybe_unused; 50 51 #ifndef DECRYPTION_SUPPORT_none 52 static const io_dev_connector_t *enc_dev_con; 53 uintptr_t enc_dev_handle; 54 #endif 55 56 #if STM32MP_SDMMC || STM32MP_EMMC 57 static struct mmc_device_info mmc_info; 58 59 static uint8_t block_buffer[MMC_BLOCK_SIZE] __aligned(MMC_BLOCK_SIZE); 60 61 static io_block_dev_spec_t mmc_block_dev_spec = { 62 /* It's used as temp buffer in block driver */ 63 .buffer = { 64 .offset = (size_t)&block_buffer, 65 .length = MMC_BLOCK_SIZE, 66 }, 67 .ops = { 68 .read = mmc_read_blocks, 69 .write = NULL, 70 }, 71 .block_size = MMC_BLOCK_SIZE, 72 }; 73 74 static const io_dev_connector_t *mmc_dev_con; 75 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 76 77 #if STM32MP_SPI_NOR 78 static io_mtd_dev_spec_t spi_nor_dev_spec = { 79 .ops = { 80 .init = spi_nor_init, 81 .read = spi_nor_read, 82 }, 83 }; 84 #endif 85 86 #if STM32MP_RAW_NAND 87 static io_mtd_dev_spec_t nand_dev_spec = { 88 .ops = { 89 .init = nand_raw_init, 90 .read = nand_read, 91 .seek = nand_seek_bb 92 }, 93 }; 94 95 static const io_dev_connector_t *nand_dev_con; 96 #endif 97 98 #if STM32MP_SPI_NAND 99 static io_mtd_dev_spec_t spi_nand_dev_spec = { 100 .ops = { 101 .init = spi_nand_init, 102 .read = nand_read, 103 .seek = nand_seek_bb 104 }, 105 }; 106 #endif 107 108 #if STM32MP_SPI_NAND || STM32MP_SPI_NOR 109 static const io_dev_connector_t *spi_dev_con; 110 #endif 111 112 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 113 static const io_dev_connector_t *memmap_dev_con; 114 #endif 115 116 io_block_spec_t image_block_spec = { 117 .offset = 0U, 118 .length = 0U, 119 }; 120 121 int open_fip(const uintptr_t spec) 122 { 123 return io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID); 124 } 125 126 #ifndef DECRYPTION_SUPPORT_none 127 int open_enc_fip(const uintptr_t spec) 128 { 129 int result; 130 uintptr_t local_image_handle; 131 132 result = io_dev_init(enc_dev_handle, (uintptr_t)ENC_IMAGE_ID); 133 if (result != 0) { 134 return result; 135 } 136 137 result = io_open(enc_dev_handle, spec, &local_image_handle); 138 if (result != 0) { 139 return result; 140 } 141 142 VERBOSE("Using encrypted FIP\n"); 143 io_close(local_image_handle); 144 145 return 0; 146 } 147 #endif 148 149 int open_storage(const uintptr_t spec) 150 { 151 return io_dev_init(storage_dev_handle, 0); 152 } 153 154 #if STM32MP_EMMC_BOOT 155 static uint32_t get_boot_part_fip_header(void) 156 { 157 io_block_spec_t emmc_boot_fip_block_spec = { 158 .offset = STM32MP_EMMC_BOOT_FIP_OFFSET, 159 .length = MMC_BLOCK_SIZE, /* We are interested only in first 4 bytes */ 160 }; 161 uint32_t magic = 0U; 162 int io_result; 163 size_t bytes_read; 164 uintptr_t fip_hdr_handle; 165 166 io_result = io_open(storage_dev_handle, (uintptr_t)&emmc_boot_fip_block_spec, 167 &fip_hdr_handle); 168 assert(io_result == 0); 169 170 io_result = io_read(fip_hdr_handle, (uintptr_t)&magic, sizeof(magic), 171 &bytes_read); 172 if ((io_result != 0) || (bytes_read != sizeof(magic))) { 173 panic(); 174 } 175 176 io_close(fip_hdr_handle); 177 178 VERBOSE("%s: eMMC boot magic at offset 256K: %08x\n", 179 __func__, magic); 180 181 return magic; 182 } 183 #endif 184 185 static void print_boot_device(boot_api_context_t *boot_context) 186 { 187 switch (boot_context->boot_interface_selected) { 188 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 189 INFO("Using SDMMC\n"); 190 break; 191 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 192 INFO("Using EMMC\n"); 193 break; 194 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 195 INFO("Using SPI NOR\n"); 196 break; 197 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 198 INFO("Using FMC NAND\n"); 199 break; 200 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 201 INFO("Using SPI NAND\n"); 202 break; 203 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 204 INFO("Using UART\n"); 205 break; 206 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 207 INFO("Using USB\n"); 208 break; 209 default: 210 ERROR("Boot interface %u not found\n", 211 boot_context->boot_interface_selected); 212 panic(); 213 break; 214 } 215 216 if (boot_context->boot_interface_instance != 0U) { 217 INFO(" Instance %d\n", boot_context->boot_interface_instance); 218 } 219 } 220 221 #if STM32MP_SDMMC || STM32MP_EMMC 222 static void boot_mmc(enum mmc_device_type mmc_dev_type, 223 uint16_t boot_interface_instance) 224 { 225 int io_result __maybe_unused; 226 struct stm32_sdmmc2_params params; 227 228 zeromem(¶ms, sizeof(struct stm32_sdmmc2_params)); 229 230 mmc_info.mmc_dev_type = mmc_dev_type; 231 232 switch (boot_interface_instance) { 233 case 1: 234 params.reg_base = STM32MP_SDMMC1_BASE; 235 break; 236 case 2: 237 params.reg_base = STM32MP_SDMMC2_BASE; 238 break; 239 case 3: 240 params.reg_base = STM32MP_SDMMC3_BASE; 241 break; 242 default: 243 WARN("SDMMC instance not found, using default\n"); 244 if (mmc_dev_type == MMC_IS_SD) { 245 params.reg_base = STM32MP_SDMMC1_BASE; 246 } else { 247 params.reg_base = STM32MP_SDMMC2_BASE; 248 } 249 break; 250 } 251 252 if (mmc_dev_type != MMC_IS_EMMC) { 253 params.flags = MMC_FLAG_SD_CMD6; 254 } 255 256 params.device_info = &mmc_info; 257 if (stm32_sdmmc2_mmc_init(¶ms) != 0) { 258 ERROR("SDMMC%u init failed\n", boot_interface_instance); 259 panic(); 260 } 261 262 /* Open MMC as a block device to read FIP */ 263 io_result = register_io_dev_block(&mmc_dev_con); 264 if (io_result != 0) { 265 panic(); 266 } 267 268 io_result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_block_dev_spec, 269 &storage_dev_handle); 270 assert(io_result == 0); 271 272 #if STM32MP_EMMC_BOOT 273 if (mmc_dev_type == MMC_IS_EMMC) { 274 io_result = mmc_part_switch_current_boot(); 275 assert(io_result == 0); 276 277 if (get_boot_part_fip_header() != TOC_HEADER_NAME) { 278 WARN("%s: Can't find FIP header on eMMC boot partition. Trying GPT\n", 279 __func__); 280 io_result = mmc_part_switch_user(); 281 assert(io_result == 0); 282 return; 283 } 284 285 VERBOSE("%s: FIP header found on eMMC boot partition\n", 286 __func__); 287 image_block_spec.offset = STM32MP_EMMC_BOOT_FIP_OFFSET; 288 image_block_spec.length = mmc_boot_part_size() - STM32MP_EMMC_BOOT_FIP_OFFSET; 289 } 290 #endif 291 } 292 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 293 294 #if STM32MP_SPI_NOR 295 static void boot_spi_nor(boot_api_context_t *boot_context) 296 { 297 int io_result __maybe_unused; 298 299 io_result = stm32_qspi_init(); 300 assert(io_result == 0); 301 302 io_result = register_io_dev_mtd(&spi_dev_con); 303 assert(io_result == 0); 304 305 /* Open connections to device */ 306 io_result = io_dev_open(spi_dev_con, 307 (uintptr_t)&spi_nor_dev_spec, 308 &storage_dev_handle); 309 assert(io_result == 0); 310 } 311 #endif /* STM32MP_SPI_NOR */ 312 313 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 314 /* 315 * This function returns 0 if it can find an alternate 316 * image to be loaded or a negative errno otherwise. 317 */ 318 static int try_nand_backup_partitions(unsigned int image_id) 319 { 320 static unsigned int backup_id; 321 static unsigned int backup_block_nb; 322 323 /* Check if NAND storage used */ 324 if (nand_block_sz == 0U) { 325 return -ENODEV; 326 } 327 328 if (backup_id != image_id) { 329 backup_block_nb = PLATFORM_MTD_MAX_PART_SIZE / nand_block_sz; 330 backup_id = image_id; 331 } 332 333 if (backup_block_nb-- == 0U) { 334 return -ENOSPC; 335 } 336 337 #if PSA_FWU_SUPPORT 338 if (((image_block_spec.offset < STM32MP_NAND_FIP_B_OFFSET) && 339 ((image_block_spec.offset + nand_block_sz) >= STM32MP_NAND_FIP_B_OFFSET)) || 340 (image_block_spec.offset + nand_block_sz >= STM32MP_NAND_FIP_B_MAX_OFFSET)) { 341 return 0; 342 } 343 #endif 344 345 image_block_spec.offset += nand_block_sz; 346 347 return 0; 348 } 349 350 static const struct plat_try_images_ops try_img_ops = { 351 .next_instance = try_nand_backup_partitions, 352 }; 353 #endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */ 354 355 #if STM32MP_RAW_NAND 356 static void boot_fmc2_nand(boot_api_context_t *boot_context) 357 { 358 int io_result __maybe_unused; 359 360 plat_setup_try_img_ops(&try_img_ops); 361 362 io_result = stm32_fmc2_init(); 363 assert(io_result == 0); 364 365 /* Register the IO device on this platform */ 366 io_result = register_io_dev_mtd(&nand_dev_con); 367 assert(io_result == 0); 368 369 /* Open connections to device */ 370 io_result = io_dev_open(nand_dev_con, (uintptr_t)&nand_dev_spec, 371 &storage_dev_handle); 372 assert(io_result == 0); 373 374 nand_block_sz = nand_dev_spec.erase_size; 375 } 376 #endif /* STM32MP_RAW_NAND */ 377 378 #if STM32MP_SPI_NAND 379 static void boot_spi_nand(boot_api_context_t *boot_context) 380 { 381 int io_result __maybe_unused; 382 383 plat_setup_try_img_ops(&try_img_ops); 384 385 io_result = stm32_qspi_init(); 386 assert(io_result == 0); 387 388 io_result = register_io_dev_mtd(&spi_dev_con); 389 assert(io_result == 0); 390 391 /* Open connections to device */ 392 io_result = io_dev_open(spi_dev_con, 393 (uintptr_t)&spi_nand_dev_spec, 394 &storage_dev_handle); 395 assert(io_result == 0); 396 397 nand_block_sz = spi_nand_dev_spec.erase_size; 398 } 399 #endif /* STM32MP_SPI_NAND */ 400 401 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 402 static void mmap_io_setup(void) 403 { 404 int io_result __maybe_unused; 405 406 io_result = register_io_dev_memmap(&memmap_dev_con); 407 assert(io_result == 0); 408 409 io_result = io_dev_open(memmap_dev_con, (uintptr_t)NULL, 410 &storage_dev_handle); 411 assert(io_result == 0); 412 } 413 414 #if STM32MP_UART_PROGRAMMER 415 static void stm32cubeprogrammer_uart(uint8_t phase, uintptr_t base, size_t len) 416 { 417 int ret __maybe_unused; 418 boot_api_context_t *boot_context = 419 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 420 uintptr_t uart_base; 421 422 uart_base = get_uart_address(boot_context->boot_interface_instance); 423 ret = stm32cubeprog_uart_load(uart_base, phase, base, len); 424 assert(ret == 0); 425 } 426 #endif 427 428 #if STM32MP_USB_PROGRAMMER 429 static void stm32cubeprogrammer_usb(uint8_t phase, uintptr_t base, size_t len) 430 { 431 int ret __maybe_unused; 432 struct usb_handle *pdev; 433 434 /* Init USB on platform */ 435 pdev = usb_dfu_plat_init(); 436 437 ret = stm32cubeprog_usb_load(pdev, phase, base, len); 438 assert(ret == 0); 439 } 440 #endif 441 #endif /* STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER */ 442 443 void stm32mp_io_setup(void) 444 { 445 int io_result __maybe_unused; 446 boot_api_context_t *boot_context = 447 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 448 449 print_boot_device(boot_context); 450 451 if ((boot_context->boot_partition_used_toboot == 1U) || 452 (boot_context->boot_partition_used_toboot == 2U)) { 453 INFO("Boot used partition fsbl%u\n", 454 boot_context->boot_partition_used_toboot); 455 } 456 457 io_result = register_io_dev_fip(&fip_dev_con); 458 assert(io_result == 0); 459 460 io_result = io_dev_open(fip_dev_con, (uintptr_t)NULL, &fip_dev_handle); 461 462 #ifndef DECRYPTION_SUPPORT_none 463 io_result = register_io_dev_enc(&enc_dev_con); 464 assert(io_result == 0); 465 466 io_result = io_dev_open(enc_dev_con, (uintptr_t)NULL, &enc_dev_handle); 467 assert(io_result == 0); 468 #endif 469 470 switch (boot_context->boot_interface_selected) { 471 #if STM32MP_SDMMC 472 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 473 dmbsy(); 474 boot_mmc(MMC_IS_SD, boot_context->boot_interface_instance); 475 break; 476 #endif 477 #if STM32MP_EMMC 478 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 479 dmbsy(); 480 boot_mmc(MMC_IS_EMMC, boot_context->boot_interface_instance); 481 break; 482 #endif 483 #if STM32MP_SPI_NOR 484 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 485 dmbsy(); 486 boot_spi_nor(boot_context); 487 break; 488 #endif 489 #if STM32MP_RAW_NAND 490 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 491 dmbsy(); 492 boot_fmc2_nand(boot_context); 493 break; 494 #endif 495 #if STM32MP_SPI_NAND 496 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 497 dmbsy(); 498 boot_spi_nand(boot_context); 499 break; 500 #endif 501 #if STM32MP_UART_PROGRAMMER || STM32MP_USB_PROGRAMMER 502 #if STM32MP_UART_PROGRAMMER 503 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 504 #endif 505 #if STM32MP_USB_PROGRAMMER 506 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 507 #endif 508 dmbsy(); 509 mmap_io_setup(); 510 break; 511 #endif 512 513 default: 514 ERROR("Boot interface %d not supported\n", 515 boot_context->boot_interface_selected); 516 panic(); 517 break; 518 } 519 } 520 521 int bl2_plat_handle_pre_image_load(unsigned int image_id) 522 { 523 static bool gpt_init_done __maybe_unused; 524 uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 525 526 switch (boot_itf) { 527 #if STM32MP_SDMMC || STM32MP_EMMC 528 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 529 #if STM32MP_EMMC_BOOT 530 if (image_block_spec.offset == STM32MP_EMMC_BOOT_FIP_OFFSET) { 531 break; 532 } 533 #endif 534 /* fallthrough */ 535 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 536 if (!gpt_init_done) { 537 /* 538 * With FWU Multi Bank feature enabled, the selection of 539 * the image to boot will be done by fwu_init calling the 540 * platform hook, plat_fwu_set_images_source. 541 */ 542 #if !PSA_FWU_SUPPORT 543 const partition_entry_t *entry; 544 const struct efi_guid fip_guid = STM32MP_FIP_GUID; 545 546 partition_init(GPT_IMAGE_ID); 547 entry = get_partition_entry_by_type(&fip_guid); 548 if (entry == NULL) { 549 entry = get_partition_entry(FIP_IMAGE_NAME); 550 if (entry == NULL) { 551 ERROR("Could NOT find the %s partition!\n", 552 FIP_IMAGE_NAME); 553 554 return -ENOENT; 555 } 556 } 557 558 image_block_spec.offset = entry->start; 559 image_block_spec.length = entry->length; 560 #endif 561 gpt_init_done = true; 562 } else { 563 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 564 565 assert(bl_mem_params != NULL); 566 567 mmc_block_dev_spec.buffer.offset = bl_mem_params->image_info.image_base; 568 mmc_block_dev_spec.buffer.length = bl_mem_params->image_info.image_max_size; 569 } 570 571 break; 572 #endif 573 574 #if STM32MP_RAW_NAND || STM32MP_SPI_NAND 575 #if STM32MP_RAW_NAND 576 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 577 #endif 578 #if STM32MP_SPI_NAND 579 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 580 #endif 581 /* 582 * With FWU Multi Bank feature enabled, the selection of 583 * the image to boot will be done by fwu_init calling the 584 * platform hook, plat_fwu_set_images_source. 585 */ 586 #if !PSA_FWU_SUPPORT 587 image_block_spec.offset = STM32MP_NAND_FIP_OFFSET; 588 #endif 589 break; 590 #endif 591 592 #if STM32MP_SPI_NOR 593 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 594 /* 595 * With FWU Multi Bank feature enabled, the selection of 596 * the image to boot will be done by fwu_init calling the 597 * platform hook, plat_fwu_set_images_source. 598 */ 599 #if !PSA_FWU_SUPPORT 600 image_block_spec.offset = STM32MP_NOR_FIP_OFFSET; 601 #endif 602 break; 603 #endif 604 605 #if STM32MP_UART_PROGRAMMER 606 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_UART: 607 if (image_id == FW_CONFIG_ID) { 608 stm32cubeprogrammer_uart(PHASE_SSBL, DWL_BUFFER_BASE, 609 DWL_BUFFER_SIZE); 610 /* FIP loaded at DWL address */ 611 image_block_spec.offset = DWL_BUFFER_BASE; 612 image_block_spec.length = DWL_BUFFER_SIZE; 613 } 614 break; 615 #endif 616 #if STM32MP_USB_PROGRAMMER 617 case BOOT_API_CTX_BOOT_INTERFACE_SEL_SERIAL_USB: 618 if (image_id == FW_CONFIG_ID) { 619 stm32cubeprogrammer_usb(PHASE_SSBL, DWL_BUFFER_BASE, 620 DWL_BUFFER_SIZE); 621 /* FIP loaded at DWL address */ 622 image_block_spec.offset = DWL_BUFFER_BASE; 623 image_block_spec.length = DWL_BUFFER_SIZE; 624 } 625 break; 626 #endif 627 628 default: 629 ERROR("FIP Not found\n"); 630 panic(); 631 } 632 633 return 0; 634 } 635 636 /* 637 * Return an IO device handle and specification which can be used to access 638 * an image. Use this to enforce platform load policy. 639 */ 640 int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle, 641 uintptr_t *image_spec) 642 { 643 int rc; 644 const struct plat_io_policy *policy; 645 646 policy = FCONF_GET_PROPERTY(stm32mp, io_policies, image_id); 647 rc = policy->check(policy->image_spec); 648 if (rc == 0) { 649 *image_spec = policy->image_spec; 650 *dev_handle = *(policy->dev_handle); 651 } 652 653 return rc; 654 } 655 656 #if PSA_FWU_SUPPORT 657 /* 658 * In each boot in non-trial mode, we set the BKP register to 659 * FWU_MAX_TRIAL_REBOOT, and return the active_index from metadata. 660 * 661 * As long as the update agent didn't update the "accepted" field in metadata 662 * (i.e. we are in trial mode), we select the new active_index. 663 * To avoid infinite boot loop at trial boot we decrement a BKP register. 664 * If this counter is 0: 665 * - an unexpected TAMPER event raised (that resets the BKP registers to 0) 666 * - a power-off occurs before the update agent was able to update the 667 * "accepted' field 668 * - we already boot FWU_MAX_TRIAL_REBOOT times in trial mode. 669 * we select the previous_active_index. 670 */ 671 uint32_t plat_fwu_get_boot_idx(void) 672 { 673 /* 674 * Select boot index and update boot counter only once per boot 675 * even if this function is called several times. 676 */ 677 static uint32_t boot_idx = INVALID_BOOT_IDX; 678 679 if (boot_idx == INVALID_BOOT_IDX) { 680 const struct fwu_metadata *data = fwu_get_metadata(); 681 682 boot_idx = data->active_index; 683 684 if (data->bank_state[boot_idx] == FWU_BANK_STATE_VALID) { 685 if (stm32_get_and_dec_fwu_trial_boot_cnt() == 0U) { 686 WARN("Trial FWU fails %u times\n", 687 FWU_MAX_TRIAL_REBOOT); 688 boot_idx = fwu_get_alternate_boot_bank(); 689 } 690 } else if (data->bank_state[boot_idx] == 691 FWU_BANK_STATE_ACCEPTED) { 692 stm32_set_max_fwu_trial_boot_cnt(); 693 } else { 694 ERROR("The active bank(%u) of the platform is in Invalid State.\n", 695 boot_idx); 696 boot_idx = fwu_get_alternate_boot_bank(); 697 stm32_clear_fwu_trial_boot_cnt(); 698 } 699 } 700 701 return boot_idx; 702 } 703 704 static void *stm32_get_image_spec(const struct efi_guid *img_type_guid) 705 { 706 unsigned int i; 707 708 for (i = 0U; i < MAX_NUMBER_IDS; i++) { 709 if ((guidcmp(&policies[i].img_type_guid, img_type_guid)) == 0) { 710 return (void *)policies[i].image_spec; 711 } 712 } 713 714 return NULL; 715 } 716 717 void plat_fwu_set_images_source(const struct fwu_metadata *metadata) 718 { 719 unsigned int i; 720 uint32_t boot_idx; 721 const partition_entry_t *entry __maybe_unused; 722 const struct fwu_image_entry *img_entry; 723 const void *img_type_guid; 724 const void *img_guid; 725 io_block_spec_t *image_spec; 726 const uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 727 728 boot_idx = plat_fwu_get_boot_idx(); 729 assert(boot_idx < NR_OF_FW_BANKS); 730 VERBOSE("Selecting to boot from bank %u\n", boot_idx); 731 732 img_entry = (void *)&metadata->fw_desc.img_entry; 733 for (i = 0U; i < NR_OF_IMAGES_IN_FW_BANK; i++) { 734 img_type_guid = &img_entry[i].img_type_guid; 735 736 img_guid = &img_entry[i].img_bank_info[boot_idx].img_guid; 737 738 image_spec = stm32_get_image_spec(img_type_guid); 739 if (image_spec == NULL) { 740 ERROR("Unable to get image spec for the image in the metadata\n"); 741 panic(); 742 } 743 744 switch (boot_itf) { 745 #if (STM32MP_SDMMC || STM32MP_EMMC) 746 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 747 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 748 entry = get_partition_entry_by_guid(img_guid); 749 if (entry == NULL) { 750 ERROR("No partition with the uuid mentioned in metadata\n"); 751 panic(); 752 } 753 754 image_spec->offset = entry->start; 755 image_spec->length = entry->length; 756 break; 757 #endif 758 #if STM32MP_SPI_NOR 759 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 760 if (guidcmp(img_guid, &STM32MP_NOR_FIP_A_GUID) == 0) { 761 image_spec->offset = STM32MP_NOR_FIP_A_OFFSET; 762 } else if (guidcmp(img_guid, &STM32MP_NOR_FIP_B_GUID) == 0) { 763 image_spec->offset = STM32MP_NOR_FIP_B_OFFSET; 764 } else { 765 ERROR("Invalid uuid mentioned in metadata\n"); 766 panic(); 767 } 768 break; 769 #endif 770 #if (STM32MP_RAW_NAND || STM32MP_SPI_NAND) 771 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 772 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 773 if (guidcmp(img_guid, &STM32MP_NAND_FIP_A_GUID) == 0) { 774 image_spec->offset = STM32MP_NAND_FIP_A_OFFSET; 775 } else if (guidcmp(img_guid, &STM32MP_NAND_FIP_B_GUID) == 0) { 776 image_spec->offset = STM32MP_NAND_FIP_B_OFFSET; 777 } else { 778 ERROR("Invalid uuid mentioned in metadata\n"); 779 panic(); 780 } 781 break; 782 #endif 783 default: 784 panic(); 785 break; 786 } 787 } 788 } 789 790 static int set_metadata_image_source(unsigned int image_id, 791 uintptr_t *handle, 792 uintptr_t *image_spec) 793 { 794 struct plat_io_policy *policy; 795 io_block_spec_t *spec __maybe_unused; 796 const partition_entry_t *entry __maybe_unused; 797 const uint16_t boot_itf = stm32mp_get_boot_itf_selected(); 798 799 policy = &policies[image_id]; 800 spec = (io_block_spec_t *)policy->image_spec; 801 802 switch (boot_itf) { 803 #if (STM32MP_SDMMC || STM32MP_EMMC) 804 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_SD: 805 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC: 806 partition_init(GPT_IMAGE_ID); 807 808 if (image_id == FWU_METADATA_IMAGE_ID) { 809 entry = get_partition_entry(METADATA_PART_1); 810 } else { 811 entry = get_partition_entry(METADATA_PART_2); 812 } 813 814 if (entry == NULL) { 815 ERROR("Unable to find a metadata partition\n"); 816 return -ENOENT; 817 } 818 819 spec->offset = entry->start; 820 spec->length = entry->length; 821 break; 822 #endif 823 824 #if STM32MP_SPI_NOR 825 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NOR_SPI: 826 if (image_id == FWU_METADATA_IMAGE_ID) { 827 spec->offset = STM32MP_NOR_METADATA1_OFFSET; 828 } else { 829 spec->offset = STM32MP_NOR_METADATA2_OFFSET; 830 } 831 832 spec->length = sizeof(struct fwu_metadata); 833 break; 834 #endif 835 836 #if (STM32MP_RAW_NAND || STM32MP_SPI_NAND) 837 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_FMC: 838 case BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_NAND_SPI: 839 if (image_id == FWU_METADATA_IMAGE_ID) { 840 spec->offset = STM32MP_NAND_METADATA1_OFFSET; 841 } else { 842 spec->offset = STM32MP_NAND_METADATA2_OFFSET; 843 } 844 845 spec->length = sizeof(struct fwu_metadata); 846 break; 847 #endif 848 default: 849 panic(); 850 break; 851 } 852 853 *image_spec = policy->image_spec; 854 *handle = *policy->dev_handle; 855 856 return 0; 857 } 858 859 int plat_fwu_set_metadata_image_source(unsigned int image_id, 860 uintptr_t *handle, 861 uintptr_t *image_spec) 862 { 863 assert((image_id == FWU_METADATA_IMAGE_ID) || 864 (image_id == BKUP_FWU_METADATA_IMAGE_ID)); 865 866 return set_metadata_image_source(image_id, handle, image_spec); 867 } 868 #endif /* PSA_FWU_SUPPORT */ 869