| 26f2f24c | 14-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge changes from topic "cot-dt2c" into integration
* changes: feat(arm): update documentation for cot-dt2c feat(arm): remove the bl2 static c file feat(arm): generate tbbr c file CoT dt2c
Merge changes from topic "cot-dt2c" into integration
* changes: feat(arm): update documentation for cot-dt2c feat(arm): remove the bl2 static c file feat(arm): generate tbbr c file CoT dt2c feat(arm): makefile invoke CoT dt2c feat(auth): standalone CoT dt2c tool refactor(auth): separate bl1 and bl2 CoT refactor(st): align the NV counter naming refactor(fvp): align the NV counter naming
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| 97a689bb | 13-Aug-2024 |
Madhukar Pappireddy <madhukar.pappireddy@arm.com> |
Merge "feat(spm): change UART0-1 to NS device region" into integration |
| 04150fee | 25-Jun-2023 |
XiaoDong Huang <derrick.huang@rock-chips.com> |
feat(rk3588): support SCMI for clock/reset domain
rockchip scmi clock controls clocks which only available in secure mode.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I5
feat(rk3588): support SCMI for clock/reset domain
rockchip scmi clock controls clocks which only available in secure mode.
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I5b983877a5b4e8acababbf7e0a3e2725e6479e08
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| e3ec6ff4 | 26-Jun-2023 |
XiaoDong Huang <derrick.huang@rock-chips.com> |
feat(rk3588): support rk3588
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4
feat(rk3588): support rk3588
rk3588 is an Octa-core soc with Cortex-a55/a76 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com> Change-Id: I598109f15a2efd5b33aedd176cf708c08cb1dcf4
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| a846a235 | 22-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): load fw-config file
Add FW_CONFIG_ID entry in bl2_mem_params_descs to be loaded, and add its parsing in bl2_plat_handle_post_image_load().
Signed-off-by: Yann Gautier <yann.gautier@
feat(stm32mp2): load fw-config file
Add FW_CONFIG_ID entry in bl2_mem_params_descs to be loaded, and add its parsing in bl2_plat_handle_post_image_load().
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I151289474325067204ffae62e17c2e1e00f79b1c
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| 5af9369c | 22-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): add fw-config compilation
The DT file will be in the FIP, and loaded at the beginning of SYSRAM. The info for hw-config (U-Boot DT by default) is also added, it will be loaded just a
feat(stm32mp2): add fw-config compilation
The DT file will be in the FIP, and loaded at the beginning of SYSRAM. The info for hw-config (U-Boot DT by default) is also added, it will be loaded just after BL33 (U-Boot binary).
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I9d58428c2d911c5c16cae5164122bf833a847a7d
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| 5e0be8c0 | 21-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks in RCC_DDRCPCFGR register. Call this ddr_sub_system_clk_init() just before clock driver
feat(stm32mp2): enable DDR sub-system clock
Create a DDR helper files, and add a function to enable DDR clocks in RCC_DDRCPCFGR register. Call this ddr_sub_system_clk_init() just before clock driver init, as it needs to be done before enabling DDR PLL clock (PLL2).
Change-Id: I365d6aa034363d0c036ce2d9f944f077ba86e193 Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| c3a75341 | 21-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): add fixed regulators support
Call fixed_regulator_register() in bl2_el3_plat_arch_setup() to configure fixed regulators, if any are present in device tree.
Signed-off-by: Yann Gauti
feat(stm32mp2): add fixed regulators support
Call fixed_regulator_register() in bl2_el3_plat_arch_setup() to configure fixed regulators, if any are present in device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: Iab2d3a4b6b294727b2b6722a6a13bf3f194ec0f9
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| cdaced36 | 15-Apr-2022 |
Yann Gautier <yann.gautier@foss.st.com> |
feat(stm32mp2): print board info
Call stm32mp_print_boardinfo() during BL2 setup. As for STM32MP1, the board info is taken in the dedicated OTP fuse. This fuse will be taken from device tree.
Signe
feat(stm32mp2): print board info
Call stm32mp_print_boardinfo() during BL2 setup. As for STM32MP1, the board info is taken in the dedicated OTP fuse. This fuse will be taken from device tree.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I2de0199378562b459b27427109ce66239316b8d9
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| 381b2a6b | 21-Jun-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): display CPU info
Print information about CPU type, package and revision. SoC revision ID of MP2 family are defined with the OTP 102.
Signed-off-by: Maxime Méré <maxime.mere@foss.st.
feat(stm32mp2): display CPU info
Print information about CPU type, package and revision. SoC revision ID of MP2 family are defined with the OTP 102.
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I14a95c8a7cb9b06ce32c2e592ae69a1741067e8d
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| 154e6e62 | 21-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): get chip ID
Add a function to get chip ID from SYSCFG peripheral.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: I32b15fca00e52d31f253e02873ab01b804399658 |
| db77f8bf | 21-May-2024 |
Yann Gautier <yann.gautier@st.com> |
feat(stm32mp2): add BL2 boot first steps
Configure the first steps for STM32MP2 BL2 platform boot: - Save boot context address for later use - Configure BL2 MMU - Load and use BL2 DT - Reset backup
feat(stm32mp2): add BL2 boot first steps
Configure the first steps for STM32MP2 BL2 platform boot: - Save boot context address for later use - Configure BL2 MMU - Load and use BL2 DT - Reset backup domain - Initialize clocks - Configure UART for console - Print some info about board and reset reason - Setup storage (only SD-card for the moment)
The platform boot stops at BL2 image load, as bl2_mem_params_descs[] is still empty.
Signed-off-by: Yann Gautier <yann.gautier@st.com> Change-Id: If6127cfbf77825a03afe8d65ba47c8c0661de496
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| d2d1da5f | 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal2): add dummy implementation for SCMI PD" into integration |
| a71f11ba | 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "fix(versal2): add ufs specific features support" into integration |
| 2e1db2b4 | 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge "feat(versal): deprecate build time arg VERSAL_PLATFORM" into integration |
| 778e2452 | 12-Aug-2024 |
Joanna Farley <joanna.farley@arm.com> |
Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration
* changes: docs(xilinx): update SMC documentation in TF-A feat(xilinx): add feature check function for TF-A specific
Merge changes from topic "xlnx_tfa_passthrough_plm_ipi_cmd" into integration
* changes: docs(xilinx): update SMC documentation in TF-A feat(xilinx): add feature check function for TF-A specific APIs feat(xilinx): update SiP SVC version number feat(xilinx): update TF-A to passthrough all PLM commands fix(xilinx): fix logic to read ipi response
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| b9c20e5d | 29-Jul-2024 |
Amit Nagal <amit.nagal@amd.com> |
fix(versal2): add ufs specific features support
Following IOCTL IDs are required for UFS specific functionalities.
IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET) This gives the Tx_Rx_config_rdy_signal_mo
fix(versal2): add ufs specific features support
Following IOCTL IDs are required for UFS specific functionalities.
IOCTL ID - 40(IOCTL_UFS_TXRX_CFGRDY_GET) This gives the Tx_Rx_config_rdy_signal_mon(0xF1061054) register value which contains the Tx and Rx lanes configuration ready signal information.
IOCTL ID - 41(IOCTL_UFS_SRAM_CSR_SEL) Select - 0(IOCTL_UFS_SRAM_CSR_SET) This will allow to set sram control and status register (0xF106104C) with the value provided by driver.
Select - 1(IOCTL_UFS_SRAM_CSR_GET) This should return the sram control and status register (0xF106104C) value to the driver.
UFS Host reset assert/de-assert(using SCMI) support is added. register address : 0xF1260340
UFS PHY reset assert/de-assert(using SCMI) support is added. register address : 0xF1061050
Change-Id: I5368cc7251350946bd5ddb3a4c817b75e1d4a43e Signed-off-by: Amit Nagal <amit.nagal@amd.com>
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| 095a20a7 | 02-Feb-2024 |
Michal Simek <michal.simek@amd.com> |
feat(versal2): add dummy implementation for SCMI PD
Add dummy implementation of power domain. There is dwc3 usb driver which requires power domain to be setup and make sense to have interface prepar
feat(versal2): add dummy implementation for SCMI PD
Add dummy implementation of power domain. There is dwc3 usb driver which requires power domain to be setup and make sense to have interface prepared even it is not doing anything. When this runs on real HW functionality will be extended.
Change-Id: I68151edc3ab817da3308e7c21af57a3355a17d37 Signed-off-by: Michal Simek <michal.simek@amd.com>
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| 479c833a | 10-Jul-2024 |
Xialin Liu <Xialin.Liu@ARM.com> |
feat(arm): generate tbbr c file CoT dt2c
Integrate the cot-dt2c tool into build process for TBBR configuration
Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa Signed-off-by: Xialin Liu <Xialin
feat(arm): generate tbbr c file CoT dt2c
Integrate the cot-dt2c tool into build process for TBBR configuration
Change-Id: I42ccbc96c5c8fd21266200e427306a80236a78aa Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
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| 0e0fab0c | 28-Jun-2024 |
Xialin Liu <Xialin.Liu@ARM.com> |
feat(arm): makefile invoke CoT dt2c
Change the makefile to call the cot-dt2c tool during the build for Arm platform
Change-Id: Idb7c02cca6b9ddd87f575a42c88e7b2660b896e0 Signed-off-by: Xialin Liu <X
feat(arm): makefile invoke CoT dt2c
Change the makefile to call the cot-dt2c tool during the build for Arm platform
Change-Id: Idb7c02cca6b9ddd87f575a42c88e7b2660b896e0 Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
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| 3146a70a | 27-Jun-2024 |
Xialin Liu <Xialin.Liu@ARM.com> |
refactor(auth): separate bl1 and bl2 CoT
Separate the bl1 and bl2 CoT into individual C files for the upcoming tool, i.e. the CoT device tree-to-source file generator.
Change-Id: I0d24791991b3539c7
refactor(auth): separate bl1 and bl2 CoT
Separate the bl1 and bl2 CoT into individual C files for the upcoming tool, i.e. the CoT device tree-to-source file generator.
Change-Id: I0d24791991b3539c7aef9a562920dc62fecdc69a Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
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| 04d02a9c | 13-Jun-2024 |
Xialin Liu <Xialin.Liu@ARM.com> |
refactor(fvp): align the NV counter naming
Align the naming of nv_counter to nv_ctr in the DTBs so that they match with the static C files. Update the binding documentation accordingly. This renamin
refactor(fvp): align the NV counter naming
Align the naming of nv_counter to nv_ctr in the DTBs so that they match with the static C files. Update the binding documentation accordingly. This renaming is beneficial for the upcoming conversion tool that will convert CoT DT files to C files.
Change-Id: If65d51ad9fc6445b1ae9937f1691becf8742cf01 Signed-off-by: Xialin Liu <Xialin.Liu@ARM.com>
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| a3eef39f | 02-Aug-2024 |
Jaylyn Ren <Jaylyn.Ren2@arm.com> |
fix(rdv3): remove NEED_* from RD-V3 makefile
As the NEED_* are internal flags used in the build system and are not meant to be used by platforms, remove them from the RD-V3 makefile.
Signed-off-by:
fix(rdv3): remove NEED_* from RD-V3 makefile
As the NEED_* are internal flags used in the build system and are not meant to be used by platforms, remove them from the RD-V3 makefile.
Signed-off-by: Jaylyn Ren <Jaylyn.Ren2@arm.com> Change-Id: If7144b9d72c16e8025f929f2546abd96194615ce
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| 88bc65d7 | 12-Mar-2024 |
Yang Xiwen <forbidden405@foxmail.com> |
fix(poplar): shutdown wdt0 before powering off
Shut down watchdog0 before panic() to avoid the system being reset by it.
Signed-off-by: Yang Xiwen <forbidden405@foxmail.com> Change-Id: I4982202db92
fix(poplar): shutdown wdt0 before powering off
Shut down watchdog0 before panic() to avoid the system being reset by it.
Signed-off-by: Yang Xiwen <forbidden405@foxmail.com> Change-Id: I4982202db9252b42312bd5f0f6e0729024a157df
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| 5cc5ded8 | 06-Aug-2024 |
Manish V Badarkhe <manish.badarkhe@arm.com> |
Merge "fix(ast2700): fix mpll calculate statement" into integration |