1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cdefs.h> 9 #include <errno.h> 10 #include <stdint.h> 11 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/clk.h> 15 #include <drivers/mmc.h> 16 #include <drivers/st/regulator_fixed.h> 17 #include <drivers/st/stm32mp2_ddr_helpers.h> 18 #include <lib/fconf/fconf.h> 19 #include <lib/fconf/fconf_dyn_cfg_getter.h> 20 #include <lib/mmio.h> 21 #include <lib/xlat_tables/xlat_tables_v2.h> 22 #include <plat/common/platform.h> 23 24 #include <platform_def.h> 25 #include <stm32mp_common.h> 26 #include <stm32mp_dt.h> 27 28 #define BOOT_CTX_ADDR 0x0e000020UL 29 30 static void print_reset_reason(void) 31 { 32 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 33 34 if (rstsr == 0U) { 35 WARN("Reset reason unknown\n"); 36 return; 37 } 38 39 INFO("Reset reason (0x%x):\n", rstsr); 40 41 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 42 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 43 INFO("System exits from Standby for CA35\n"); 44 return; 45 } 46 47 if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 48 INFO("D1 domain exits from DStandby\n"); 49 return; 50 } 51 } 52 53 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 54 INFO(" Power-on Reset (rst_por)\n"); 55 return; 56 } 57 58 if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 59 INFO(" Brownout Reset (rst_bor)\n"); 60 return; 61 } 62 63 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) { 64 INFO(" System reset (SYSRST) by M33\n"); 65 return; 66 } 67 68 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) { 69 INFO(" System reset (SYSRST) by A35\n"); 70 return; 71 } 72 73 if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 74 INFO(" Clock failure on HSE\n"); 75 return; 76 } 77 78 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) { 79 INFO(" IWDG1 system reset (rst_iwdg1)\n"); 80 return; 81 } 82 83 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) { 84 INFO(" IWDG2 system reset (rst_iwdg2)\n"); 85 return; 86 } 87 88 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) { 89 INFO(" IWDG3 system reset (rst_iwdg3)\n"); 90 return; 91 } 92 93 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) { 94 INFO(" IWDG4 system reset (rst_iwdg4)\n"); 95 return; 96 } 97 98 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) { 99 INFO(" IWDG5 system reset (rst_iwdg5)\n"); 100 return; 101 } 102 103 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 104 INFO(" A35 processor core 1 reset\n"); 105 return; 106 } 107 108 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 109 INFO(" Pad Reset from NRST\n"); 110 return; 111 } 112 113 if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) { 114 INFO(" Reset due to a failure of VDD_CORE\n"); 115 return; 116 } 117 118 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 119 INFO(" A35 processor reset\n"); 120 return; 121 } 122 123 ERROR(" Unidentified reset reason\n"); 124 } 125 126 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 127 u_register_t arg1 __unused, 128 u_register_t arg2 __unused, 129 u_register_t arg3 __unused) 130 { 131 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 132 } 133 134 void bl2_platform_setup(void) 135 { 136 } 137 138 static void reset_backup_domain(void) 139 { 140 uintptr_t pwr_base = stm32mp_pwr_base(); 141 uintptr_t rcc_base = stm32mp_rcc_base(); 142 143 /* 144 * Disable the backup domain write protection. 145 * The protection is enable at each reset by hardware 146 * and must be disabled by software. 147 */ 148 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 149 150 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 151 ; 152 } 153 154 /* Reset backup domain on cold boot cases */ 155 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 156 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 157 158 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 159 ; 160 } 161 162 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 163 } 164 } 165 166 void bl2_el3_plat_arch_setup(void) 167 { 168 const char *board_model; 169 boot_api_context_t *boot_context = 170 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 171 172 if (stm32_otp_probe() != 0U) { 173 EARLY_ERROR("OTP probe failed\n"); 174 panic(); 175 } 176 177 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 178 BL_CODE_END - BL_CODE_BASE, 179 MT_CODE | MT_SECURE); 180 181 configure_mmu(); 182 183 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 184 panic(); 185 } 186 187 reset_backup_domain(); 188 189 /* 190 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2), 191 * and so before stm32mp2_clk_init(). 192 */ 193 ddr_sub_system_clk_init(); 194 195 if (stm32mp2_clk_init() < 0) { 196 panic(); 197 } 198 199 stm32_save_boot_info(boot_context); 200 201 if (stm32mp_uart_console_setup() != 0) { 202 goto skip_console_init; 203 } 204 205 stm32mp_print_cpuinfo(); 206 207 board_model = dt_get_board_model(); 208 if (board_model != NULL) { 209 NOTICE("Model: %s\n", board_model); 210 } 211 212 stm32mp_print_boardinfo(); 213 214 print_reset_reason(); 215 216 skip_console_init: 217 if (fixed_regulator_register() != 0) { 218 panic(); 219 } 220 221 fconf_populate("TB_FW", STM32MP_DTB_BASE); 222 223 stm32mp_io_setup(); 224 } 225 226 /******************************************************************************* 227 * This function can be used by the platforms to update/use image 228 * information for given `image_id`. 229 ******************************************************************************/ 230 int bl2_plat_handle_post_image_load(unsigned int image_id) 231 { 232 int err = 0; 233 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 234 const struct dyn_cfg_dtb_info_t *config_info; 235 unsigned int i; 236 const unsigned int image_ids[] = { 237 BL31_IMAGE_ID, 238 }; 239 240 assert(bl_mem_params != NULL); 241 242 #if STM32MP_SDMMC || STM32MP_EMMC 243 /* 244 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 245 * We take the worst case which is 2 MMC blocks. 246 */ 247 if ((image_id != FW_CONFIG_ID) && 248 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 249 inv_dcache_range(bl_mem_params->image_info.image_base + 250 bl_mem_params->image_info.image_size, 251 2U * MMC_BLOCK_SIZE); 252 } 253 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 254 255 switch (image_id) { 256 case FW_CONFIG_ID: 257 /* Set global DTB info for fixed fw_config information */ 258 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, 259 FW_CONFIG_ID); 260 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 261 262 /* Iterate through all the fw config IDs */ 263 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 264 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 265 assert(bl_mem_params != NULL); 266 267 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 268 if (config_info == NULL) { 269 continue; 270 } 271 272 bl_mem_params->image_info.image_base = config_info->config_addr; 273 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 274 275 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 276 277 switch (image_ids[i]) { 278 case BL31_IMAGE_ID: 279 bl_mem_params->ep_info.pc = config_info->config_addr; 280 break; 281 default: 282 return -EINVAL; 283 } 284 } 285 286 /* 287 * After this step, the BL2 device tree area will be overwritten 288 * with BL31 binary, no other data should be read from BL2 DT. 289 */ 290 291 break; 292 293 default: 294 /* Do nothing in default case */ 295 break; 296 } 297 298 return err; 299 } 300