1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 9 #include <lib/xlat_tables/xlat_tables_v2.h> 10 11 #include <platform_def.h> 12 13 #define BKPR_BOOT_MODE 96U 14 15 #if defined(IMAGE_BL31) 16 /* BL31 only uses the first half of the SYSRAM */ 17 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 18 STM32MP_SYSRAM_SIZE / 2U, \ 19 MT_MEMORY | \ 20 MT_RW | \ 21 MT_SECURE | \ 22 MT_EXECUTE_NEVER) 23 #else 24 #define MAP_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \ 25 STM32MP_SYSRAM_SIZE, \ 26 MT_MEMORY | \ 27 MT_RW | \ 28 MT_SECURE | \ 29 MT_EXECUTE_NEVER) 30 #endif 31 32 #define MAP_DEVICE MAP_REGION_FLAT(STM32MP_DEVICE_BASE, \ 33 STM32MP_DEVICE_SIZE, \ 34 MT_DEVICE | \ 35 MT_RW | \ 36 MT_SECURE | \ 37 MT_EXECUTE_NEVER) 38 39 #if defined(IMAGE_BL2) 40 static const mmap_region_t stm32mp2_mmap[] = { 41 MAP_SYSRAM, 42 MAP_DEVICE, 43 {0} 44 }; 45 #endif 46 #if defined(IMAGE_BL31) 47 static const mmap_region_t stm32mp2_mmap[] = { 48 MAP_SYSRAM, 49 MAP_DEVICE, 50 {0} 51 }; 52 #endif 53 54 void configure_mmu(void) 55 { 56 mmap_add(stm32mp2_mmap); 57 init_xlat_tables(); 58 59 enable_mmu_el3(0); 60 } 61 62 uintptr_t stm32_get_gpio_bank_base(unsigned int bank) 63 { 64 if (bank == GPIO_BANK_Z) { 65 return GPIOZ_BASE; 66 } 67 68 assert(bank <= GPIO_BANK_K); 69 70 return GPIOA_BASE + (bank * GPIO_BANK_OFFSET); 71 } 72 73 uint32_t stm32_get_gpio_bank_offset(unsigned int bank) 74 { 75 if (bank == GPIO_BANK_Z) { 76 return 0; 77 } 78 79 assert(bank <= GPIO_BANK_K); 80 81 return bank * GPIO_BANK_OFFSET; 82 } 83 84 unsigned long stm32_get_gpio_bank_clock(unsigned int bank) 85 { 86 if (bank == GPIO_BANK_Z) { 87 return CK_BUS_GPIOZ; 88 } 89 90 assert(bank <= GPIO_BANK_K); 91 92 return CK_BUS_GPIOA + (bank - GPIO_BANK_A); 93 } 94 95 uint32_t stm32mp_get_chip_version(void) 96 { 97 static uint32_t rev; 98 99 if (rev != 0U) { 100 return rev; 101 } 102 103 if (stm32_get_otp_value(REVISION_OTP, &rev) != 0) { 104 panic(); 105 } 106 107 return rev; 108 } 109 110 uint32_t stm32mp_get_chip_dev_id(void) 111 { 112 return stm32mp_syscfg_get_chip_dev_id(); 113 } 114 115 static uint32_t get_part_number(void) 116 { 117 static uint32_t part_number; 118 119 if (part_number != 0U) { 120 return part_number; 121 } 122 123 if (stm32_get_otp_value(PART_NUMBER_OTP, &part_number) != 0) { 124 panic(); 125 } 126 127 return part_number; 128 } 129 130 static uint32_t get_cpu_package(void) 131 { 132 static uint32_t package = UINT32_MAX; 133 134 if (package == UINT32_MAX) { 135 if (stm32_get_otp_value(PACKAGE_OTP, &package) != 0) { 136 panic(); 137 } 138 } 139 140 return (package & PACKAGE_OTP_PKG_MASK) >> PACKAGE_OTP_PKG_SHIFT; 141 } 142 143 void stm32mp_get_soc_name(char name[STM32_SOC_NAME_SIZE]) 144 { 145 char *cpu_s, *cpu_r, *pkg; 146 147 /* MPUs Part Numbers */ 148 switch (get_part_number()) { 149 case STM32MP251A_PART_NB: 150 cpu_s = "251A"; 151 break; 152 case STM32MP251C_PART_NB: 153 cpu_s = "251C"; 154 break; 155 case STM32MP251D_PART_NB: 156 cpu_s = "251D"; 157 break; 158 case STM32MP251F_PART_NB: 159 cpu_s = "251F"; 160 break; 161 case STM32MP253A_PART_NB: 162 cpu_s = "253A"; 163 break; 164 case STM32MP253C_PART_NB: 165 cpu_s = "253C"; 166 break; 167 case STM32MP253D_PART_NB: 168 cpu_s = "253D"; 169 break; 170 case STM32MP253F_PART_NB: 171 cpu_s = "253F"; 172 break; 173 case STM32MP255A_PART_NB: 174 cpu_s = "255A"; 175 break; 176 case STM32MP255C_PART_NB: 177 cpu_s = "255C"; 178 break; 179 case STM32MP255D_PART_NB: 180 cpu_s = "255D"; 181 break; 182 case STM32MP255F_PART_NB: 183 cpu_s = "255F"; 184 break; 185 case STM32MP257A_PART_NB: 186 cpu_s = "257A"; 187 break; 188 case STM32MP257C_PART_NB: 189 cpu_s = "257C"; 190 break; 191 case STM32MP257D_PART_NB: 192 cpu_s = "257D"; 193 break; 194 case STM32MP257F_PART_NB: 195 cpu_s = "257F"; 196 break; 197 default: 198 cpu_s = "????"; 199 break; 200 } 201 202 /* Package */ 203 switch (get_cpu_package()) { 204 case STM32MP25_PKG_CUSTOM: 205 pkg = "XX"; 206 break; 207 case STM32MP25_PKG_AL_VFBGA361: 208 pkg = "AL"; 209 break; 210 case STM32MP25_PKG_AK_VFBGA424: 211 pkg = "AK"; 212 break; 213 case STM32MP25_PKG_AI_TFBGA436: 214 pkg = "AI"; 215 break; 216 default: 217 pkg = "??"; 218 break; 219 } 220 221 /* REVISION */ 222 switch (stm32mp_get_chip_version()) { 223 case STM32MP2_REV_A: 224 cpu_r = "A"; 225 break; 226 case STM32MP2_REV_B: 227 cpu_r = "B"; 228 break; 229 case STM32MP2_REV_X: 230 cpu_r = "X"; 231 break; 232 case STM32MP2_REV_Y: 233 cpu_r = "Y"; 234 break; 235 case STM32MP2_REV_Z: 236 cpu_r = "Z"; 237 break; 238 default: 239 cpu_r = "?"; 240 break; 241 } 242 243 snprintf(name, STM32_SOC_NAME_SIZE, 244 "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r); 245 } 246 247 void stm32mp_print_cpuinfo(void) 248 { 249 char name[STM32_SOC_NAME_SIZE]; 250 251 stm32mp_get_soc_name(name); 252 NOTICE("CPU: %s\n", name); 253 } 254 255 void stm32mp_print_boardinfo(void) 256 { 257 uint32_t board_id = 0U; 258 259 if (stm32_get_otp_value(BOARD_ID_OTP, &board_id) != 0) { 260 return; 261 } 262 263 if (board_id != 0U) { 264 stm32_display_board_info(board_id); 265 } 266 } 267 268 uintptr_t stm32_get_bkpr_boot_mode_addr(void) 269 { 270 return tamp_bkpr(BKPR_BOOT_MODE); 271 } 272