1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <assert.h> 8 #include <cdefs.h> 9 #include <errno.h> 10 #include <stdint.h> 11 12 #include <common/debug.h> 13 #include <common/desc_image_load.h> 14 #include <drivers/clk.h> 15 #include <drivers/mmc.h> 16 #include <drivers/st/regulator_fixed.h> 17 #include <drivers/st/stm32mp2_ddr_helpers.h> 18 #include <drivers/st/stm32mp_risab_regs.h> 19 #include <lib/fconf/fconf.h> 20 #include <lib/fconf/fconf_dyn_cfg_getter.h> 21 #include <lib/mmio.h> 22 #include <lib/xlat_tables/xlat_tables_v2.h> 23 #include <plat/common/platform.h> 24 25 #include <platform_def.h> 26 #include <stm32mp_common.h> 27 #include <stm32mp_dt.h> 28 29 #define BOOT_CTX_ADDR 0x0e000020UL 30 31 static void print_reset_reason(void) 32 { 33 uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_C1BOOTRSTSCLRR); 34 35 if (rstsr == 0U) { 36 WARN("Reset reason unknown\n"); 37 return; 38 } 39 40 INFO("Reset reason (0x%x):\n", rstsr); 41 42 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) == 0U) { 43 if ((rstsr & RCC_C1BOOTRSTSCLRR_STBYC1RSTF) != 0U) { 44 INFO("System exits from Standby for CA35\n"); 45 return; 46 } 47 48 if ((rstsr & RCC_C1BOOTRSTSCLRR_D1STBYRSTF) != 0U) { 49 INFO("D1 domain exits from DStandby\n"); 50 return; 51 } 52 } 53 54 if ((rstsr & RCC_C1BOOTRSTSCLRR_PORRSTF) != 0U) { 55 INFO(" Power-on Reset (rst_por)\n"); 56 return; 57 } 58 59 if ((rstsr & RCC_C1BOOTRSTSCLRR_BORRSTF) != 0U) { 60 INFO(" Brownout Reset (rst_bor)\n"); 61 return; 62 } 63 64 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC2RSTF) != 0U) { 65 INFO(" System reset (SYSRST) by M33\n"); 66 return; 67 } 68 69 if ((rstsr & RCC_C1BOOTRSTSSETR_SYSC1RSTF) != 0U) { 70 INFO(" System reset (SYSRST) by A35\n"); 71 return; 72 } 73 74 if ((rstsr & RCC_C1BOOTRSTSCLRR_HCSSRSTF) != 0U) { 75 INFO(" Clock failure on HSE\n"); 76 return; 77 } 78 79 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF) != 0U) { 80 INFO(" IWDG1 system reset (rst_iwdg1)\n"); 81 return; 82 } 83 84 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF) != 0U) { 85 INFO(" IWDG2 system reset (rst_iwdg2)\n"); 86 return; 87 } 88 89 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF) != 0U) { 90 INFO(" IWDG3 system reset (rst_iwdg3)\n"); 91 return; 92 } 93 94 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF) != 0U) { 95 INFO(" IWDG4 system reset (rst_iwdg4)\n"); 96 return; 97 } 98 99 if ((rstsr & RCC_C1BOOTRSTSCLRR_IWDG5SYSRSTF) != 0U) { 100 INFO(" IWDG5 system reset (rst_iwdg5)\n"); 101 return; 102 } 103 104 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1P1RSTF) != 0U) { 105 INFO(" A35 processor core 1 reset\n"); 106 return; 107 } 108 109 if ((rstsr & RCC_C1BOOTRSTSCLRR_PADRSTF) != 0U) { 110 INFO(" Pad Reset from NRST\n"); 111 return; 112 } 113 114 if ((rstsr & RCC_C1BOOTRSTSCLRR_VCORERSTF) != 0U) { 115 INFO(" Reset due to a failure of VDD_CORE\n"); 116 return; 117 } 118 119 if ((rstsr & RCC_C1BOOTRSTSCLRR_C1RSTF) != 0U) { 120 INFO(" A35 processor reset\n"); 121 return; 122 } 123 124 ERROR(" Unidentified reset reason\n"); 125 } 126 127 void bl2_el3_early_platform_setup(u_register_t arg0 __unused, 128 u_register_t arg1 __unused, 129 u_register_t arg2 __unused, 130 u_register_t arg3 __unused) 131 { 132 stm32mp_save_boot_ctx_address(BOOT_CTX_ADDR); 133 } 134 135 void bl2_platform_setup(void) 136 { 137 } 138 139 static void reset_backup_domain(void) 140 { 141 uintptr_t pwr_base = stm32mp_pwr_base(); 142 uintptr_t rcc_base = stm32mp_rcc_base(); 143 144 /* 145 * Disable the backup domain write protection. 146 * The protection is enable at each reset by hardware 147 * and must be disabled by software. 148 */ 149 mmio_setbits_32(pwr_base + PWR_BDCR1, PWR_BDCR1_DBD3P); 150 151 while ((mmio_read_32(pwr_base + PWR_BDCR1) & PWR_BDCR1_DBD3P) == 0U) { 152 ; 153 } 154 155 /* Reset backup domain on cold boot cases */ 156 if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCCKEN) == 0U) { 157 mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 158 159 while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) == 0U) { 160 ; 161 } 162 163 mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST); 164 } 165 } 166 167 void bl2_el3_plat_arch_setup(void) 168 { 169 const char *board_model; 170 boot_api_context_t *boot_context = 171 (boot_api_context_t *)stm32mp_get_boot_ctx_address(); 172 173 if (stm32_otp_probe() != 0U) { 174 EARLY_ERROR("OTP probe failed\n"); 175 panic(); 176 } 177 178 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, 179 BL_CODE_END - BL_CODE_BASE, 180 MT_CODE | MT_SECURE); 181 182 configure_mmu(); 183 184 if (dt_open_and_check(STM32MP_DTB_BASE) < 0) { 185 panic(); 186 } 187 188 reset_backup_domain(); 189 190 /* 191 * Initialize DDR sub-system clock. This needs to be done before enabling DDR PLL (PLL2), 192 * and so before stm32mp2_clk_init(). 193 */ 194 ddr_sub_system_clk_init(); 195 196 if (stm32mp2_clk_init() < 0) { 197 panic(); 198 } 199 200 #if STM32MP_DDR_FIP_IO_STORAGE 201 /* 202 * RISAB3 setup (dedicated for SRAM1) 203 * 204 * Allow secure read/writes data accesses to non-secure 205 * blocks or pages, all RISAB registers are writable. 206 * DDR firmwares are saved there before being loaded in DDRPHY memory. 207 */ 208 mmio_write_32(RISAB3_BASE + RISAB_CR, RISAB_CR_SRWIAD); 209 #endif 210 211 stm32_save_boot_info(boot_context); 212 213 if (stm32mp_uart_console_setup() != 0) { 214 goto skip_console_init; 215 } 216 217 stm32mp_print_cpuinfo(); 218 219 board_model = dt_get_board_model(); 220 if (board_model != NULL) { 221 NOTICE("Model: %s\n", board_model); 222 } 223 224 stm32mp_print_boardinfo(); 225 226 print_reset_reason(); 227 228 skip_console_init: 229 if (fixed_regulator_register() != 0) { 230 panic(); 231 } 232 233 fconf_populate("TB_FW", STM32MP_DTB_BASE); 234 235 stm32mp_io_setup(); 236 } 237 238 /******************************************************************************* 239 * This function can be used by the platforms to update/use image 240 * information for given `image_id`. 241 ******************************************************************************/ 242 int bl2_plat_handle_post_image_load(unsigned int image_id) 243 { 244 int err = 0; 245 bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id); 246 const struct dyn_cfg_dtb_info_t *config_info; 247 unsigned int i; 248 const unsigned int image_ids[] = { 249 BL31_IMAGE_ID, 250 }; 251 252 assert(bl_mem_params != NULL); 253 254 #if STM32MP_SDMMC || STM32MP_EMMC 255 /* 256 * Invalidate remaining data read from MMC but not flushed by load_image_flush(). 257 * We take the worst case which is 2 MMC blocks. 258 */ 259 if ((image_id != FW_CONFIG_ID) && 260 ((bl_mem_params->image_info.h.attr & IMAGE_ATTRIB_SKIP_LOADING) == 0U)) { 261 inv_dcache_range(bl_mem_params->image_info.image_base + 262 bl_mem_params->image_info.image_size, 263 2U * MMC_BLOCK_SIZE); 264 } 265 #endif /* STM32MP_SDMMC || STM32MP_EMMC */ 266 267 switch (image_id) { 268 case FW_CONFIG_ID: 269 /* Set global DTB info for fixed fw_config information */ 270 set_config_info(STM32MP_FW_CONFIG_BASE, ~0UL, STM32MP_FW_CONFIG_MAX_SIZE, 271 FW_CONFIG_ID); 272 fconf_populate("FW_CONFIG", STM32MP_FW_CONFIG_BASE); 273 274 /* Iterate through all the fw config IDs */ 275 for (i = 0U; i < ARRAY_SIZE(image_ids); i++) { 276 bl_mem_params = get_bl_mem_params_node(image_ids[i]); 277 assert(bl_mem_params != NULL); 278 279 config_info = FCONF_GET_PROPERTY(dyn_cfg, dtb, image_ids[i]); 280 if (config_info == NULL) { 281 continue; 282 } 283 284 bl_mem_params->image_info.image_base = config_info->config_addr; 285 bl_mem_params->image_info.image_max_size = config_info->config_max_size; 286 287 bl_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; 288 289 switch (image_ids[i]) { 290 case BL31_IMAGE_ID: 291 bl_mem_params->ep_info.pc = config_info->config_addr; 292 break; 293 default: 294 return -EINVAL; 295 } 296 } 297 298 /* 299 * After this step, the BL2 device tree area will be overwritten 300 * with BL31 binary, no other data should be read from BL2 DT. 301 */ 302 303 break; 304 305 default: 306 /* Do nothing in default case */ 307 break; 308 } 309 310 return err; 311 } 312