1 /* 2 * Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef STM32MP2_DEF_H 8 #define STM32MP2_DEF_H 9 10 #include <common/tbbr/tbbr_img_def.h> 11 #ifndef __ASSEMBLER__ 12 #include <drivers/st/bsec.h> 13 #endif 14 #include <drivers/st/stm32mp25_rcc.h> 15 #ifndef __ASSEMBLER__ 16 #include <drivers/st/stm32mp2_clk.h> 17 #endif 18 #include <drivers/st/stm32mp2_pwr.h> 19 #include <dt-bindings/clock/stm32mp25-clks.h> 20 #include <dt-bindings/clock/stm32mp25-clksrc.h> 21 #include <dt-bindings/gpio/stm32-gpio.h> 22 #include <dt-bindings/reset/stm32mp25-resets.h> 23 24 #ifndef __ASSEMBLER__ 25 #include <boot_api.h> 26 #include <stm32mp2_private.h> 27 #include <stm32mp_common.h> 28 #include <stm32mp_dt.h> 29 #include <stm32mp_shared_resources.h> 30 #endif 31 32 /******************************************************************************* 33 * CHIP ID 34 ******************************************************************************/ 35 #define STM32MP2_CHIP_ID U(0x505) 36 37 #define STM32MP251A_PART_NB U(0x400B3E6D) 38 #define STM32MP251C_PART_NB U(0x000B306D) 39 #define STM32MP251D_PART_NB U(0xC00B3E6D) 40 #define STM32MP251F_PART_NB U(0x800B306D) 41 #define STM32MP253A_PART_NB U(0x400B3E0C) 42 #define STM32MP253C_PART_NB U(0x000B300C) 43 #define STM32MP253D_PART_NB U(0xC00B3E0C) 44 #define STM32MP253F_PART_NB U(0x800B300C) 45 #define STM32MP255A_PART_NB U(0x40082E00) 46 #define STM32MP255C_PART_NB U(0x00082000) 47 #define STM32MP255D_PART_NB U(0xC0082E00) 48 #define STM32MP255F_PART_NB U(0x80082000) 49 #define STM32MP257A_PART_NB U(0x40002E00) 50 #define STM32MP257C_PART_NB U(0x00002000) 51 #define STM32MP257D_PART_NB U(0xC0002E00) 52 #define STM32MP257F_PART_NB U(0x80002000) 53 54 #define STM32MP2_REV_A U(0x08) 55 #define STM32MP2_REV_B U(0x10) 56 #define STM32MP2_REV_X U(0x12) 57 #define STM32MP2_REV_Y U(0x11) 58 #define STM32MP2_REV_Z U(0x09) 59 60 /******************************************************************************* 61 * PACKAGE ID 62 ******************************************************************************/ 63 #define STM32MP25_PKG_CUSTOM U(0) 64 #define STM32MP25_PKG_AL_VFBGA361 U(1) 65 #define STM32MP25_PKG_AK_VFBGA424 U(3) 66 #define STM32MP25_PKG_AI_TFBGA436 U(5) 67 #define STM32MP25_PKG_UNKNOWN U(7) 68 69 /******************************************************************************* 70 * STM32MP2 memory map related constants 71 ******************************************************************************/ 72 #define STM32MP_SYSRAM_BASE U(0x0E000000) 73 #define STM32MP_SYSRAM_SIZE U(0x00040000) 74 #define SRAM1_BASE U(0x0E040000) 75 #define SRAM1_SIZE_FOR_TFA U(0x00010000) 76 #define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE 77 78 /* DDR configuration */ 79 #define STM32MP_DDR_BASE U(0x80000000) 80 #define STM32MP_DDR_MAX_SIZE UL(0x100000000) /* Max 4GB */ 81 82 /* DDR power initializations */ 83 #ifndef __ASSEMBLER__ 84 enum ddr_type { 85 STM32MP_DDR3, 86 STM32MP_DDR4, 87 STM32MP_LPDDR4 88 }; 89 #endif 90 91 /* Section used inside TF binaries */ 92 #define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */ 93 /* 512 Bytes reserved for header */ 94 #define STM32MP_HEADER_SIZE U(0x00000200) 95 #define STM32MP_HEADER_BASE (STM32MP_SYSRAM_BASE + \ 96 STM32MP_PARAM_LOAD_SIZE) 97 98 /* round_up(STM32MP_PARAM_LOAD_SIZE + STM32MP_HEADER_SIZE, PAGE_SIZE) */ 99 #define STM32MP_HEADER_RESERVED_SIZE U(0x3000) 100 101 #define STM32MP_BINARY_BASE (STM32MP_SYSRAM_BASE + \ 102 STM32MP_PARAM_LOAD_SIZE + \ 103 STM32MP_HEADER_SIZE) 104 105 #define STM32MP_BINARY_SIZE (STM32MP_SYSRAM_SIZE - \ 106 (STM32MP_PARAM_LOAD_SIZE + \ 107 STM32MP_HEADER_SIZE)) 108 109 #define STM32MP_BL2_RO_SIZE U(0x00020000) /* 128 KB */ 110 #define STM32MP_BL2_SIZE U(0x00029000) /* 164 KB for BL2 */ 111 112 /* Allocate remaining sysram to BL31 */ 113 #define STM32MP_BL31_SIZE (STM32MP_SEC_SYSRAM_SIZE - \ 114 STM32MP_BL2_SIZE) 115 116 #define STM32MP_BL2_BASE (STM32MP_SYSRAM_BASE + \ 117 STM32MP_SYSRAM_SIZE - \ 118 STM32MP_BL2_SIZE) 119 120 #define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE 121 122 #define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \ 123 STM32MP_BL2_RO_SIZE) 124 125 #define STM32MP_BL2_RW_SIZE (STM32MP_SYSRAM_BASE + \ 126 STM32MP_SYSRAM_SIZE - \ 127 STM32MP_BL2_RW_BASE) 128 129 /* BL2 and BL32/sp_min require 4 tables */ 130 #define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */ 131 132 /* 133 * MAX_MMAP_REGIONS is usually: 134 * BL stm32mp2_mmap size + mmap regions in *_plat_arch_setup 135 */ 136 #define MAX_MMAP_REGIONS 6 137 138 /* DTB initialization value */ 139 #define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */ 140 141 #define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \ 142 STM32MP_BL2_DTB_SIZE) 143 144 #if defined(IMAGE_BL2) 145 #define STM32MP_DTB_SIZE STM32MP_BL2_DTB_SIZE 146 #define STM32MP_DTB_BASE STM32MP_BL2_DTB_BASE 147 #endif 148 149 #if STM32MP_DDR_FIP_IO_STORAGE 150 #define STM32MP_DDR_FW_BASE SRAM1_BASE 151 #define STM32MP_DDR_FW_MAX_SIZE U(0x8800) 152 #endif 153 154 #define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE 155 #define STM32MP_FW_CONFIG_BASE STM32MP_SYSRAM_BASE 156 157 #define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x04000000)) 158 #define STM32MP_BL33_MAX_SIZE U(0x400000) 159 #define STM32MP_HW_CONFIG_BASE (STM32MP_BL33_BASE + \ 160 STM32MP_BL33_MAX_SIZE) 161 #define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) 162 163 /******************************************************************************* 164 * STM32MP2 device/io map related constants (used for MMU) 165 ******************************************************************************/ 166 #define STM32MP_DEVICE_BASE U(0x40000000) 167 #define STM32MP_DEVICE_SIZE U(0x40000000) 168 169 /******************************************************************************* 170 * STM32MP2 RCC 171 ******************************************************************************/ 172 #define RCC_BASE U(0x44200000) 173 174 /******************************************************************************* 175 * STM32MP2 PWR 176 ******************************************************************************/ 177 #define PWR_BASE U(0x44210000) 178 179 /******************************************************************************* 180 * STM32MP2 GPIO 181 ******************************************************************************/ 182 #define GPIOA_BASE U(0x44240000) 183 #define GPIOB_BASE U(0x44250000) 184 #define GPIOC_BASE U(0x44260000) 185 #define GPIOD_BASE U(0x44270000) 186 #define GPIOE_BASE U(0x44280000) 187 #define GPIOF_BASE U(0x44290000) 188 #define GPIOG_BASE U(0x442A0000) 189 #define GPIOH_BASE U(0x442B0000) 190 #define GPIOI_BASE U(0x442C0000) 191 #define GPIOJ_BASE U(0x442D0000) 192 #define GPIOK_BASE U(0x442E0000) 193 #define GPIOZ_BASE U(0x46200000) 194 #define GPIO_BANK_OFFSET U(0x10000) 195 196 #define STM32MP_GPIOS_PIN_MAX_COUNT 16 197 #define STM32MP_GPIOZ_PIN_MAX_COUNT 8 198 199 /******************************************************************************* 200 * STM32MP2 UART 201 ******************************************************************************/ 202 #define USART1_BASE U(0x40330000) 203 #define USART2_BASE U(0x400E0000) 204 #define USART3_BASE U(0x400F0000) 205 #define UART4_BASE U(0x40100000) 206 #define UART5_BASE U(0x40110000) 207 #define USART6_BASE U(0x40220000) 208 #define UART7_BASE U(0x40370000) 209 #define UART8_BASE U(0x40380000) 210 #define UART9_BASE U(0x402C0000) 211 #define STM32MP_NB_OF_UART U(9) 212 213 /* For UART crash console */ 214 #define STM32MP_DEBUG_USART_CLK_FRQ 64000000 215 /* USART2 on HSI@64MHz, TX on GPIOA4 Alternate 6 */ 216 #define STM32MP_DEBUG_USART_BASE USART2_BASE 217 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOA_BASE 218 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_GPIOACFGR 219 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_GPIOxCFGR_GPIOxEN 220 #define DEBUG_UART_TX_GPIO_PORT 4 221 #define DEBUG_UART_TX_GPIO_ALTERNATE 6 222 #define DEBUG_UART_TX_CLKSRC_REG RCC_XBAR8CFGR 223 #define DEBUG_UART_TX_CLKSRC XBAR_SRC_HSI 224 #define DEBUG_UART_TX_EN_REG RCC_USART2CFGR 225 #define DEBUG_UART_TX_EN RCC_UARTxCFGR_UARTxEN 226 #define DEBUG_UART_RST_REG RCC_USART2CFGR 227 #define DEBUG_UART_RST_BIT RCC_UARTxCFGR_UARTxRST 228 #define DEBUG_UART_PREDIV_CFGR RCC_PREDIV8CFGR 229 #define DEBUG_UART_FINDIV_CFGR RCC_FINDIV8CFGR 230 231 /******************************************************************************* 232 * STM32MP2 SDMMC 233 ******************************************************************************/ 234 #define STM32MP_SDMMC1_BASE U(0x48220000) 235 #define STM32MP_SDMMC2_BASE U(0x48230000) 236 #define STM32MP_SDMMC3_BASE U(0x48240000) 237 238 /******************************************************************************* 239 * STM32MP2 BSEC / OTP 240 ******************************************************************************/ 241 /* 242 * 367 available OTPs, the other are masked 243 * - ECIES key: 368 to 375 (only readable by bootrom) 244 * - HWKEY: 376 to 383 (never reloadable or readable) 245 */ 246 #define STM32MP2_OTP_MAX_ID U(0x16F) 247 #define STM32MP2_MID_OTP_START U(0x80) 248 #define STM32MP2_UPPER_OTP_START U(0x100) 249 250 /* OTP labels */ 251 #define PART_NUMBER_OTP "part-number-otp" 252 #define REVISION_OTP "rev_otp" 253 #define PACKAGE_OTP "package-otp" 254 #define HCONF1_OTP "otp124" 255 #define NAND_OTP "otp16" 256 #define NAND2_OTP "otp20" 257 #define BOARD_ID_OTP "board-id" 258 #define UID_OTP "uid-otp" 259 #define LIFECYCLE2_OTP "otp18" 260 #define PKH_OTP "otp144" 261 #define ENCKEY_OTP "otp260" 262 263 /* OTP mask */ 264 /* PACKAGE */ 265 #define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0) 266 #define PACKAGE_OTP_PKG_SHIFT U(0) 267 268 /* IWDG OTP */ 269 #define HCONF1_OTP_IWDG_HW_POS U(0) 270 #define HCONF1_OTP_IWDG_FZ_STOP_POS U(1) 271 #define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2) 272 273 /* NAND OTP */ 274 /* NAND parameter storage flag */ 275 #define NAND_PARAM_STORED_IN_OTP BIT_32(31) 276 277 /* NAND page size in bytes */ 278 #define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29) 279 #define NAND_PAGE_SIZE_SHIFT U(29) 280 #define NAND_PAGE_SIZE_2K U(0) 281 #define NAND_PAGE_SIZE_4K U(1) 282 #define NAND_PAGE_SIZE_8K U(2) 283 284 /* NAND block size in pages */ 285 #define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27) 286 #define NAND_BLOCK_SIZE_SHIFT U(27) 287 #define NAND_BLOCK_SIZE_64_PAGES U(0) 288 #define NAND_BLOCK_SIZE_128_PAGES U(1) 289 #define NAND_BLOCK_SIZE_256_PAGES U(2) 290 291 /* NAND number of block (in unit of 256 blocks) */ 292 #define NAND_BLOCK_NB_MASK GENMASK_32(26, 19) 293 #define NAND_BLOCK_NB_SHIFT U(19) 294 #define NAND_BLOCK_NB_UNIT U(256) 295 296 /* NAND bus width in bits */ 297 #define NAND_WIDTH_MASK BIT_32(18) 298 #define NAND_WIDTH_SHIFT U(18) 299 300 /* NAND number of ECC bits per 512 bytes */ 301 #define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15) 302 #define NAND_ECC_BIT_NB_SHIFT U(15) 303 #define NAND_ECC_BIT_NB_UNSET U(0) 304 #define NAND_ECC_BIT_NB_1_BITS U(1) 305 #define NAND_ECC_BIT_NB_4_BITS U(2) 306 #define NAND_ECC_BIT_NB_8_BITS U(3) 307 #define NAND_ECC_ON_DIE U(4) 308 309 /* NAND number of planes */ 310 #define NAND_PLANE_BIT_NB_MASK BIT_32(14) 311 312 /* NAND2 OTP */ 313 #define NAND2_PAGE_SIZE_SHIFT U(16) 314 315 /* NAND2 config distribution */ 316 #define NAND2_CONFIG_DISTRIB BIT_32(0) 317 #define NAND2_PNAND_NAND2_SNAND_NAND1 U(0) 318 #define NAND2_PNAND_NAND1_SNAND_NAND2 U(1) 319 320 /* MONOTONIC OTP */ 321 #define MAX_MONOTONIC_VALUE U(32) 322 323 /* UID OTP */ 324 #define UID_WORD_NB U(3) 325 326 /* Lifecycle OTP */ 327 #define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0) 328 329 /******************************************************************************* 330 * STM32MP2 TAMP 331 ******************************************************************************/ 332 #define PLAT_MAX_TAMP_INT U(5) 333 #define PLAT_MAX_TAMP_EXT U(3) 334 #define TAMP_BASE U(0x46010000) 335 #define TAMP_SMCR (TAMP_BASE + U(0x20)) 336 #define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100)) 337 #define TAMP_BKP_REG_CLK CK_BUS_RTC 338 #define TAMP_BKP_SEC_NUMBER U(10) 339 #define TAMP_COUNTR U(0x40) 340 341 #if !(defined(__LINKER__) || defined(__ASSEMBLER__)) 342 static inline uintptr_t tamp_bkpr(uint32_t idx) 343 { 344 return TAMP_BKP_REGISTER_BASE + (idx << 2); 345 } 346 #endif 347 348 /******************************************************************************* 349 * STM32MP2 DDRCTRL 350 ******************************************************************************/ 351 #define DDRCTRL_BASE U(0x48040000) 352 353 /******************************************************************************* 354 * STM32MP2 DDRDBG 355 ******************************************************************************/ 356 #define DDRDBG_BASE U(0x48050000) 357 358 /******************************************************************************* 359 * STM32MP2 DDRPHYC 360 ******************************************************************************/ 361 #define DDRPHYC_BASE U(0x48C00000) 362 363 /******************************************************************************* 364 * Miscellaneous STM32MP1 peripherals base address 365 ******************************************************************************/ 366 #define BSEC_BASE U(0x44000000) 367 #define DBGMCU_BASE U(0x4A010000) 368 #define HASH_BASE U(0x42010000) 369 #define RTC_BASE U(0x46000000) 370 #define STGEN_BASE U(0x48080000) 371 #define SYSCFG_BASE U(0x44230000) 372 373 /******************************************************************************* 374 * STM32MP RIF 375 ******************************************************************************/ 376 #define RISAB3_BASE U(0x42110000) 377 378 /******************************************************************************* 379 * STM32MP CA35SSC 380 ******************************************************************************/ 381 #define A35SSC_BASE U(0x48800000) 382 383 /******************************************************************************* 384 * REGULATORS 385 ******************************************************************************/ 386 /* 3 PWR + 1 VREFBUF + 14 PMIC regulators + 1 FIXED */ 387 #define PLAT_NB_RDEVS U(19) 388 /* 2 FIXED */ 389 #define PLAT_NB_FIXED_REGUS U(2) 390 /* No GPIO regu */ 391 #define PLAT_NB_GPIO_REGUS U(0) 392 393 /******************************************************************************* 394 * Device Tree defines 395 ******************************************************************************/ 396 #define DT_BSEC_COMPAT "st,stm32mp25-bsec" 397 #define DT_DDR_COMPAT "st,stm32mp2-ddr" 398 #define DT_PWR_COMPAT "st,stm32mp25-pwr" 399 #define DT_RCC_CLK_COMPAT "st,stm32mp25-rcc" 400 #define DT_SDMMC2_COMPAT "st,stm32mp25-sdmmc2" 401 #define DT_UART_COMPAT "st,stm32h7-uart" 402 403 #endif /* STM32MP2_DEF_H */ 404